kernel/irq/generic-chip.c

   1 /*
   2  * Library implementing the most common irq chip callback functions
   3  *
   4  * Copyright (C) 2011, Thomas Gleixner
   5  */
   6 #include <linux/io.h>
   7 #include <linux/irq.h>
   8 #include <linux/slab.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/kernel_stat.h>
  11 #include <linux/syscore_ops.h>
  12
  13 #include "internals.h"
  14
  15 static LIST_HEAD(gc_list);
  16 static DEFINE_RAW_SPINLOCK(gc_lock);
  17
  18 static inline struct irq_chip_regs *cur_regs(struct irq_data *d)
  19 {
  20         return &container_of(d->chip, struct irq_chip_type, chip)->regs;
  21 }
  22
  23 /**
  24  * irq_gc_noop - NOOP function
  25  * @d: irq_data
  26  */
  27 void irq_gc_noop(struct irq_data *d)
  28 {
  29 }
  30
  31 /**
  32  * irq_gc_mask_disable_reg - Mask chip via disable register
  33  * @d: irq_data
  34  *
  35  * Chip has separate enable/disable registers instead of a single mask
  36  * register.
  37  */
  38 void irq_gc_mask_disable_reg(struct irq_data *d)
  39 {
  40         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  41         u32 mask = 1 << (d->irq - gc->irq_base);
  42
  43         irq_gc_lock(gc);
  44         irq_reg_writel(mask, gc->reg_base + cur_regs(d)->disable);
  45         gc->mask_cache &= ~mask;
  46         irq_gc_unlock(gc);
  47 }
  48
  49 /**
  50  * irq_gc_mask_set_mask_bit - Mask chip via setting bit in mask register
  51  * @d: irq_data
  52  *
  53  * Chip has a single mask register. Values of this register are cached
  54  * and protected by gc->lock
  55  */
  56 void irq_gc_mask_set_bit(struct irq_data *d)
  57 {
  58         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  59         u32 mask = 1 << (d->irq - gc->irq_base);
  60
  61         irq_gc_lock(gc);
  62         gc->mask_cache |= mask;
  63         irq_reg_writel(gc->mask_cache, gc->reg_base + cur_regs(d)->mask);
  64         irq_gc_unlock(gc);
  65 }
  66
  67 /**
  68  * irq_gc_mask_set_mask_bit - Mask chip via clearing bit in mask register
  69  * @d: irq_data
  70  *
  71  * Chip has a single mask register. Values of this register are cached
  72  * and protected by gc->lock
  73  */
  74 void irq_gc_mask_clr_bit(struct irq_data *d)
  75 {
  76         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  77         u32 mask = 1 << (d->irq - gc->irq_base);
  78
  79         irq_gc_lock(gc);
  80         gc->mask_cache &= ~mask;
  81         irq_reg_writel(gc->mask_cache, gc->reg_base + cur_regs(d)->mask);
  82         irq_gc_unlock(gc);
  83 }
  84
  85 /**
  86  * irq_gc_unmask_enable_reg - Unmask chip via enable register
  87  * @d: irq_data
  88  *
  89  * Chip has separate enable/disable registers instead of a single mask
  90  * register.
  91  */
  92 void irq_gc_unmask_enable_reg(struct irq_data *d)
  93 {
  94         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  95         u32 mask = 1 << (d->irq - gc->irq_base);
  96
  97         irq_gc_lock(gc);
  98         irq_reg_writel(mask, gc->reg_base + cur_regs(d)->enable);
  99         gc->mask_cache |= mask;
 100         irq_gc_unlock(gc);
 101 }
 102
 103 /**
 104  * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
 105  * @d: irq_data
 106  */
 107 void irq_gc_ack_set_bit(struct irq_data *d)
 108 {
 109         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 110         u32 mask = 1 << (d->irq - gc->irq_base);
 111
 112         irq_gc_lock(gc);
 113         irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
 114         irq_gc_unlock(gc);
 115 }
 116
 117 /**
 118  * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
 119  * @d: irq_data
 120  */
 121 void irq_gc_ack_clr_bit(struct irq_data *d)
 122 {
 123         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 124         u32 mask = ~(1 << (d->irq - gc->irq_base));
 125
 126         irq_gc_lock(gc);
 127         irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
 128         irq_gc_unlock(gc);
 129 }
 130
 131 /**
 132  * irq_gc_mask_disable_reg_and_ack- Mask and ack pending interrupt
 133  * @d: irq_data
 134  */
 135 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
 136 {
 137         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 138         u32 mask = 1 << (d->irq - gc->irq_base);
 139
 140         irq_gc_lock(gc);
 141         irq_reg_writel(mask, gc->reg_base + cur_regs(d)->mask);
 142         irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
 143         irq_gc_unlock(gc);
 144 }
 145
 146 /**
 147  * irq_gc_eoi - EOI interrupt
 148  * @d: irq_data
 149  */
 150 void irq_gc_eoi(struct irq_data *d)
 151 {
 152         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 153         u32 mask = 1 << (d->irq - gc->irq_base);
 154
 155         irq_gc_lock(gc);
 156         irq_reg_writel(mask, gc->reg_base + cur_regs(d)->eoi);
 157         irq_gc_unlock(gc);
 158 }
 159
 160 /**
 161  * irq_gc_set_wake - Set/clr wake bit for an interrupt
 162  * @d: irq_data
 163  *
 164  * For chips where the wake from suspend functionality is not
 165  * configured in a separate register and the wakeup active state is
 166  * just stored in a bitmask.
 167  */
 168 int irq_gc_set_wake(struct irq_data *d, unsigned int on)
 169 {
 170         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 171         u32 mask = 1 << (d->irq - gc->irq_base);
 172
 173         if (!(mask & gc->wake_enabled))
 174                 return -EINVAL;
 175
 176         irq_gc_lock(gc);
 177         if (on)
 178                 gc->wake_active |= mask;
 179         else
 180                 gc->wake_active &= ~mask;
 181         irq_gc_unlock(gc);
 182         return 0;
 183 }
 184
 185 /**
 186  * irq_alloc_generic_chip - Allocate a generic chip and initialize it
 187  * @name:       Name of the irq chip
 188  * @num_ct:     Number of irq_chip_type instances associated with this
 189  * @irq_base:   Interrupt base nr for this chip
 190  * @reg_base:   Register base address (virtual)
 191  * @handler:    Default flow handler associated with this chip
 192  *
 193  * Returns an initialized irq_chip_generic structure. The chip defaults
 194  * to the primary (index 0) irq_chip_type and @handler
 195  */
 196 struct irq_chip_generic *
 197 irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
 198                        void __iomem *reg_base, irq_flow_handler_t handler)
 199 {
 200         struct irq_chip_generic *gc;
 201         unsigned long sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
 202
 203         gc = kzalloc(sz, GFP_KERNEL);
 204         if (gc) {
 205                 raw_spin_lock_init(&gc->lock);
 206                 gc->num_ct = num_ct;
 207                 gc->irq_base = irq_base;
 208                 gc->reg_base = reg_base;
 209                 gc->chip_types->chip.name = name;
 210                 gc->chip_types->handler = handler;
 211         }
 212         return gc;
 213 }
 214 EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);
 215
 216 /*
 217  * Separate lockdep class for interrupt chip which can nest irq_desc
 218  * lock.
 219  */
 220 static struct lock_class_key irq_nested_lock_class;
 221
 222 /**
 223  * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
 224  * @gc:         Generic irq chip holding all data
 225  * @msk:        Bitmask holding the irqs to initialize relative to gc->irq_base
 226  * @flags:      Flags for initialization
 227  * @clr:        IRQ_* bits to clear
 228  * @set:        IRQ_* bits to set
 229  *
 230  * Set up max. 32 interrupts starting from gc->irq_base. Note, this
 231  * initializes all interrupts to the primary irq_chip_type and its
 232  * associated handler.
 233  */
 234 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
 235                             enum irq_gc_flags flags, unsigned int clr,
 236                             unsigned int set)
 237 {
 238         struct irq_chip_type *ct = gc->chip_types;
 239         unsigned int i;
 240
 241         raw_spin_lock(&gc_lock);
 242         list_add_tail(&gc->list, &gc_list);
 243         raw_spin_unlock(&gc_lock);
 244
 245         /* Init mask cache ? */
 246         if (flags & IRQ_GC_INIT_MASK_CACHE)
 247                 gc->mask_cache = irq_reg_readl(gc->reg_base + ct->regs.mask);
 248
 249         for (i = gc->irq_base; msk; msk >>= 1, i++) {
 250                 if (!(msk & 0x01))
 251                         continue;
 252
 253                 if (flags & IRQ_GC_INIT_NESTED_LOCK)
 254                         irq_set_lockdep_class(i, &irq_nested_lock_class);
 255
 256                 irq_set_chip_and_handler(i, &ct->chip, ct->handler);
 257                 irq_set_chip_data(i, gc);
 258                 irq_modify_status(i, clr, set);
 259         }
 260         gc->irq_cnt = i - gc->irq_base;
 261 }
 262 EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
 263
 264 /**
 265  * irq_setup_alt_chip - Switch to alternative chip
 266  * @d:          irq_data for this interrupt
 267  * @type        Flow type to be initialized
 268  *
 269  * Only to be called from chip->irq_set_type() callbacks.
 270  */
 271 int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
 272 {
 273         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 274         struct irq_chip_type *ct = gc->chip_types;
 275         unsigned int i;
 276
 277         for (i = 0; i < gc->num_ct; i++, ct++) {
 278                 if (ct->type & type) {
 279                         d->chip = &ct->chip;
 280                         irq_data_to_desc(d)->handle_irq = ct->handler;
 281                         return 0;
 282                 }
 283         }
 284         return -EINVAL;
 285 }
 286 EXPORT_SYMBOL_GPL(irq_setup_alt_chip);
 287
 288 /**
 289  * irq_remove_generic_chip - Remove a chip
 290  * @gc:         Generic irq chip holding all data
 291  * @msk:        Bitmask holding the irqs to initialize relative to gc->irq_base
 292  * @clr:        IRQ_* bits to clear
 293  * @set:        IRQ_* bits to set
 294  *
 295  * Remove up to 32 interrupts starting from gc->irq_base.
 296  */
 297 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
 298                              unsigned int clr, unsigned int set)
 299 {
 300         unsigned int i = gc->irq_base;
 301
 302         raw_spin_lock(&gc_lock);
 303         list_del(&gc->list);
 304         raw_spin_unlock(&gc_lock);
 305
 306         for (; msk; msk >>= 1, i++) {
 307                 if (!(msk & 0x01))
 308                         continue;
 309
 310                 /* Remove handler first. That will mask the irq line */
 311                 irq_set_handler(i, NULL);
 312                 irq_set_chip(i, &no_irq_chip);
 313                 irq_set_chip_data(i, NULL);
 314                 irq_modify_status(i, clr, set);
 315         }
 316 }
 317 EXPORT_SYMBOL_GPL(irq_remove_generic_chip);
 318
 319 #ifdef CONFIG_PM
 320 static int irq_gc_suspend(void)
 321 {
 322         struct irq_chip_generic *gc;
 323
 324         list_for_each_entry(gc, &gc_list, list) {
 325                 struct irq_chip_type *ct = gc->chip_types;
 326
 327                 if (ct->chip.irq_suspend)
 328                         ct->chip.irq_suspend(irq_get_irq_data(gc->irq_base));
 329         }
 330         return 0;
 331 }
 332
 333 static void irq_gc_resume(void)
 334 {
 335         struct irq_chip_generic *gc;
 336
 337         list_for_each_entry(gc, &gc_list, list) {
 338                 struct irq_chip_type *ct = gc->chip_types;
 339
 340                 if (ct->chip.irq_resume)
 341                         ct->chip.irq_resume(irq_get_irq_data(gc->irq_base));
 342         }
 343 }
 344 #else
 345 #define irq_gc_suspend NULL
 346 #define irq_gc_resume NULL
 347 #endif
 348
 349 static void irq_gc_shutdown(void)
 350 {
 351         struct irq_chip_generic *gc;
 352
 353         list_for_each_entry(gc, &gc_list, list) {
 354                 struct irq_chip_type *ct = gc->chip_types;
 355
 356                 if (ct->chip.irq_pm_shutdown)
 357                         ct->chip.irq_pm_shutdown(irq_get_irq_data(gc->irq_base));
 358         }
 359 }
 360
 361 static struct syscore_ops irq_gc_syscore_ops = {
 362         .suspend = irq_gc_suspend,
 363         .resume = irq_gc_resume,
 364         .shutdown = irq_gc_shutdown,
 365 };
 366
 367 static int __init irq_gc_init_ops(void)
 368 {
 369         register_syscore_ops(&irq_gc_syscore_ops);
 370         return 0;
 371 }
 372 device_initcall(irq_gc_init_ops);