[ARM] Update bfd's Tag_CPU_arch knowledge
[deliverable/binutils-gdb.git] / ld / testsuite / ld-arm / tls-longplt-lib.d
1 .*: file format elf32-.*arm
2 architecture: armv6t2, flags 0x00000150:
3 HAS_SYMS, DYNAMIC, D_PAGED
4 start address 0x.*
5
6 Disassembly of section .plt:
7
8 00008170 <.plt>:
9 .*: e52de004 push {lr} ; .*
10 .*: e59fe004 ldr lr, \[pc, #4\] ; .*
11 .*: e08fe00e add lr, pc, lr
12 .*: e5bef008 ldr pc, \[lr, #8\]!
13 .*: 000080e0 .word 0x000080e0
14 .*: e08e0000 add r0, lr, r0
15 .*: e5901004 ldr r1, \[r0, #4\]
16 .*: e12fff11 bx r1
17 .*: e52d2004 push {r2} ; .*
18 .*: e59f200c ldr r2, \[pc, #12\] ; .*
19 .*: e59f100c ldr r1, \[pc, #12\] ; .*
20 .*: e79f2002 ldr r2, \[pc, r2\]
21 .*: e081100f add r1, r1, pc
22 .*: e12fff12 bx r2
23 .*: 000080d8 .word 0x000080d8
24 .*: 000080b8 .word 0x000080b8
25
26 Disassembly of section .text:
27
28 000081b0 <text>:
29 .*: e59f0004 ldr r0, \[pc, #4\] ; .*
30 .*: fafffff2 blx .* <\.plt\+0x14>
31 .*: e1a00000 nop ; .*
32 .*: 000080b4 .word 0x000080b4
33 .*: 4801 ldr r0, \[pc, #4\] ; .*
34 .*: f7ff efe0 blx .* <\.plt\+0x14>
35 .*: bf00 nop
36 .*: 000080a5 .word 0x000080a5
37
38 Disassembly of section .foo:
39
40 04001000 <foo>:
41 .*: e59f0004 ldr r0, \[pc, #4\] ; .*
42 .*: fa000009 blx 4001030 .*
43 .*: e1a00000 nop ; .*
44 .*: fc00f264 .word 0xfc00f264
45 .*: e59f0004 ldr r0, \[pc, #4\] ; .*
46 .*: fa000005 blx 4001030 .*
47 .*: e1a00000 nop ; .*
48 .*: fc00f25c .word 0xfc00f25c
49 .*: 4801 ldr r0, \[pc, #4\] ; .*
50 .*: f000 e806 blx 4001030 .*
51 .*: bf00 nop
52 .*: fc00f245 .word 0xfc00f245
53 .*: 00000000 .word 0x00000000
54
55 04001030 <__unnamed_veneer>:
56 .*: e59f1000 ldr r1, \[pc\] ; .*
57 .*: e08ff001 add pc, pc, r1
58 .*: fc007148 .word 0xfc007148
59 .*: 00000000 .word 0x00000000
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