ld/testsuite/ld-powerpc/relbrlt.d

   1 #source: relbrlt.s
   2 #as: -a64
   3 #ld: -melf64ppc --no-plt-align --speculate-indirect-jumps --no-ld-generated-unwind-info --emit-relocs
   4 #objdump: -Dr
   5
   6 .*
   7
   8 Disassembly of section \.text:
   9
  10 0*100000c0 <_start>:
  11 [0-9a-f  ]*:    (49 bf 00 21|21 00 bf 49)       bl      .*
  12 [0-9a-f  ]*: R_PPC64_REL24      \.text\+0x37e003c
  13 [0-9a-f  ]*:    (60 00 00 00|00 00 00 60)       nop
  14 [0-9a-f  ]*:    (49 bf 00 1d|1d 00 bf 49)       bl      .*
  15 [0-9a-f  ]*: R_PPC64_REL24      \.text\+0x3bf002c
  16 [0-9a-f  ]*:    (60 00 00 00|00 00 00 60)       nop
  17 [0-9a-f  ]*:    (49 bf 00 21|21 00 bf 49)       bl      .*
  18 [0-9a-f  ]*: R_PPC64_REL24      \.text\+0x57e0030
  19 [0-9a-f  ]*:    (60 00 00 00|00 00 00 60)       nop
  20 [0-9a-f  ]*:    00 00 00 00     \.long 0x0
  21 [0-9a-f  ]*:    (4b ff ff e4|e4 ff ff 4b)       b       .* <_start>
  22         \.\.\.
  23
  24 [0-9a-f  ]*<.*long_branch.*>:
  25 [0-9a-f  ]*:    (49 bf 00 1c|1c 00 bf 49)       b       .* <far>
  26 [0-9a-f  ]*: R_PPC64_REL24      \*ABS\*\+0x137e00fc
  27
  28 [0-9a-f  ]*<.*plt_branch.*>:
  29 [0-9a-f  ]*:    (e9 82 80 f8|f8 80 82 e9)       ld      r12,-32520\(r2\)
  30 [0-9a-f  ]*: R_PPC64_TOC16_DS   \*ABS\*\+0x157f00f8
  31 [0-9a-f  ]*:    (7d 89 03 a6|a6 03 89 7d)       mtctr   r12
  32 [0-9a-f  ]*:    (4e 80 04 20|20 04 80 4e)       bctr
  33
  34 [0-9a-f  ]*<.*plt_branch.*>:
  35 [0-9a-f  ]*:    (e9 82 81 00|00 81 82 e9)       ld      r12,-32512\(r2\)
  36 [0-9a-f  ]*: R_PPC64_TOC16_DS   \*ABS\*\+0x157f0100
  37 [0-9a-f  ]*:    (7d 89 03 a6|a6 03 89 7d)       mtctr   r12
  38 [0-9a-f  ]*:    (4e 80 04 20|20 04 80 4e)       bctr
  39         \.\.\.
  40
  41 0*137e00fc <far>:
  42 [0-9a-f  ]*:    (4e 80 00 20|20 00 80 4e)       blr
  43         \.\.\.
  44
  45 0*13bf00ec <far2far>:
  46 [0-9a-f  ]*:    (4e 80 00 20|20 00 80 4e)       blr
  47         \.\.\.
  48
  49 0*157e00f0 <huge>:
  50 [0-9a-f  ]*:    (4e 80 00 20|20 00 80 4e)       blr
  51
  52 Disassembly of section \.branch_lt:
  53
  54 0*157f00f8 .*:
  55 [0-9a-f  ]*:    (00 00 00 00|ec 00 bf 13) .*
  56 [0-9a-f  ]*: R_PPC64_RELATIVE   \*ABS\*\+0x13bf00ec
  57 [0-9a-f  ]*:    (13 bf 00 ec|00 00 00 00) .*
  58 [0-9a-f  ]*:    (00 00 00 00|f0 00 7e 15) .*
  59 [0-9a-f  ]*: R_PPC64_RELATIVE   \*ABS\*\+0x157e00f0
  60 [0-9a-f  ]*:    (15 7e 00 f0|00 00 00 00) .*