1 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
3 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
4 * i386-init.h : Regenerated.
6 2018-05-25 Alan Modra <amodra@gmail.com>
8 * Makefile.in: Regenerate.
9 * po/POTFILES.in: Regenerate.
11 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
13 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
14 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
15 (insert_bab, extract_bab, insert_btab, extract_btab,
16 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
17 (BAT, BBA VBA RBS XB6S): Delete macros.
18 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
19 (BB, BD, RBX, XC6): Update for new macros.
20 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
21 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
22 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
23 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
25 2018-05-18 John Darrington <john@darrington.wattle.id.au>
27 * Makefile.am: Add support for s12z architecture.
28 * configure.ac: Likewise.
29 * disassemble.c: Likewise.
30 * disassemble.h: Likewise.
31 * Makefile.in: Regenerate.
32 * configure: Regenerate.
33 * s12z-dis.c: New file.
36 2018-05-18 Alan Modra <amodra@gmail.com>
38 * nfp-dis.c: Don't #include libbfd.h.
39 (init_nfp3200_priv): Use bfd_get_section_contents.
40 (nit_nfp6000_mecsr_sec): Likewise.
42 2018-05-17 Nick Clifton <nickc@redhat.com>
44 * po/zh_CN.po: Updated simplified Chinese translation.
46 2018-05-16 Tamar Christina <tamar.christina@arm.com>
49 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
50 * aarch64-dis-2.c: Regenerate.
52 2018-05-15 Tamar Christina <tamar.christina@arm.com>
55 * aarch64-asm.c (opintl.h): Include.
56 (aarch64_ins_sysreg): Enforce read/write constraints.
57 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
58 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
59 (F_REG_READ, F_REG_WRITE): New.
60 * aarch64-opc.c (aarch64_print_operand): Generate notes for
62 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
63 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
64 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
65 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
66 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
67 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
68 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
69 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
70 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
71 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
72 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
73 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
74 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
75 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
76 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
77 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
78 msr (F_SYS_WRITE), mrs (F_SYS_READ).
80 2018-05-15 Tamar Christina <tamar.christina@arm.com>
83 * aarch64-dis.c (no_notes: New.
84 (parse_aarch64_dis_option): Support notes.
85 (aarch64_decode_insn, print_operands): Likewise.
86 (print_aarch64_disassembler_options): Document notes.
87 * aarch64-opc.c (aarch64_print_operand): Support notes.
89 2018-05-15 Tamar Christina <tamar.christina@arm.com>
92 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
93 and take error struct.
94 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
95 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
96 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
97 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
98 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
99 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
100 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
101 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
102 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
103 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
104 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
105 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
106 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
107 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
108 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
109 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
110 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
111 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
112 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
113 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
114 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
115 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
116 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
117 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
118 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
119 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
120 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
121 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
122 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
123 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
124 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
125 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
126 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
127 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
128 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
129 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
130 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
131 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
132 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
133 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
134 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
135 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
136 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
137 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
138 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
139 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
140 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
141 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
142 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
143 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
144 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
145 (determine_disassembling_preference, aarch64_decode_insn,
146 print_insn_aarch64_word, print_insn_data): Take errors struct.
147 (print_insn_aarch64): Use errors.
148 * aarch64-asm-2.c: Regenerate.
149 * aarch64-dis-2.c: Regenerate.
150 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
151 boolean in aarch64_insert_operan.
152 (print_operand_extractor): Likewise.
153 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
155 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
157 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
159 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
161 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
163 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
165 * cr16-opc.c (cr16_instruction): Comment typo fix.
166 * hppa-dis.c (print_insn_hppa): Likewise.
168 2018-05-08 Jim Wilson <jimw@sifive.com>
170 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
171 (match_c_slli64, match_srxi_as_c_srxi): New.
172 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
173 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
174 <c.slli, c.srli, c.srai>: Use match_s_slli.
175 <c.slli64, c.srli64, c.srai64>: New.
177 2018-05-08 Alan Modra <amodra@gmail.com>
179 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
180 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
181 partition opcode space for index lookup.
183 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
185 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
186 <insn_length>: ...with this. Update usage.
187 Remove duplicate call to *info->memory_error_func.
189 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
190 H.J. Lu <hongjiu.lu@intel.com>
192 * i386-dis.c (Gva): New.
193 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
194 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
195 (prefix_table): New instructions (see prefix above).
196 (mod_table): New instructions (see prefix above).
197 (OP_G): Handle va_mode.
198 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
200 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
201 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
202 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
203 * i386-opc.tbl: Add movidir{i,64b}.
204 * i386-init.h: Regenerated.
205 * i386-tbl.h: Likewise.
207 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
209 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
211 * i386-opc.h (AddrPrefixOp0): Renamed to ...
212 (AddrPrefixOpReg): This.
213 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
214 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
216 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
218 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
219 (vle_num_opcodes): Likewise.
220 (spe2_num_opcodes): Likewise.
221 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
223 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
224 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
227 2018-05-01 Tamar Christina <tamar.christina@arm.com>
229 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
231 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
233 Makefile.am: Added nfp-dis.c.
234 configure.ac: Added bfd_nfp_arch.
235 disassemble.h: Added print_insn_nfp prototype.
236 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
237 nfp-dis.c: New, for NFP support.
238 po/POTFILES.in: Added nfp-dis.c to the list.
239 Makefile.in: Regenerate.
240 configure: Regenerate.
242 2018-04-26 Jan Beulich <jbeulich@suse.com>
244 * i386-opc.tbl: Fold various non-memory operand AVX512VL
245 templates into their base ones.
246 * i386-tlb.h: Re-generate.
248 2018-04-26 Jan Beulich <jbeulich@suse.com>
250 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
251 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
252 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
253 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
254 * i386-init.h: Re-generate.
256 2018-04-26 Jan Beulich <jbeulich@suse.com>
258 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
259 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
260 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
261 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
263 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
265 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
267 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
268 cpuregzmm, and cpuregmask.
269 * i386-init.h: Re-generate.
270 * i386-tbl.h: Re-generate.
272 2018-04-26 Jan Beulich <jbeulich@suse.com>
274 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
275 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
276 * i386-init.h: Re-generate.
278 2018-04-26 Jan Beulich <jbeulich@suse.com>
280 * i386-gen.c (VexImmExt): Delete.
281 * i386-opc.h (VexImmExt, veximmext): Delete.
282 * i386-opc.tbl: Drop all VexImmExt uses.
283 * i386-tlb.h: Re-generate.
285 2018-04-25 Jan Beulich <jbeulich@suse.com>
287 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
289 * i386-tlb.h: Re-generate.
291 2018-04-25 Tamar Christina <tamar.christina@arm.com>
293 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
295 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
297 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
299 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
300 (cpu_flags): Add CpuCLDEMOTE.
301 * i386-init.h: Regenerate.
302 * i386-opc.h (enum): Add CpuCLDEMOTE,
303 (i386_cpu_flags): Add cpucldemote.
304 * i386-opc.tbl: Add cldemote.
305 * i386-tbl.h: Regenerate.
307 2018-04-16 Alan Modra <amodra@gmail.com>
309 * Makefile.am: Remove sh5 and sh64 support.
310 * configure.ac: Likewise.
311 * disassemble.c: Likewise.
312 * disassemble.h: Likewise.
313 * sh-dis.c: Likewise.
314 * sh64-dis.c: Delete.
315 * sh64-opc.c: Delete.
316 * sh64-opc.h: Delete.
317 * Makefile.in: Regenerate.
318 * configure: Regenerate.
319 * po/POTFILES.in: Regenerate.
321 2018-04-16 Alan Modra <amodra@gmail.com>
323 * Makefile.am: Remove w65 support.
324 * configure.ac: Likewise.
325 * disassemble.c: Likewise.
326 * disassemble.h: Likewise.
329 * Makefile.in: Regenerate.
330 * configure: Regenerate.
331 * po/POTFILES.in: Regenerate.
333 2018-04-16 Alan Modra <amodra@gmail.com>
335 * configure.ac: Remove we32k support.
336 * configure: Regenerate.
338 2018-04-16 Alan Modra <amodra@gmail.com>
340 * Makefile.am: Remove m88k support.
341 * configure.ac: Likewise.
342 * disassemble.c: Likewise.
343 * disassemble.h: Likewise.
344 * m88k-dis.c: Delete.
345 * Makefile.in: Regenerate.
346 * configure: Regenerate.
347 * po/POTFILES.in: Regenerate.
349 2018-04-16 Alan Modra <amodra@gmail.com>
351 * Makefile.am: Remove i370 support.
352 * configure.ac: Likewise.
353 * disassemble.c: Likewise.
354 * disassemble.h: Likewise.
355 * i370-dis.c: Delete.
356 * i370-opc.c: Delete.
357 * Makefile.in: Regenerate.
358 * configure: Regenerate.
359 * po/POTFILES.in: Regenerate.
361 2018-04-16 Alan Modra <amodra@gmail.com>
363 * Makefile.am: Remove h8500 support.
364 * configure.ac: Likewise.
365 * disassemble.c: Likewise.
366 * disassemble.h: Likewise.
367 * h8500-dis.c: Delete.
368 * h8500-opc.h: Delete.
369 * Makefile.in: Regenerate.
370 * configure: Regenerate.
371 * po/POTFILES.in: Regenerate.
373 2018-04-16 Alan Modra <amodra@gmail.com>
375 * configure.ac: Remove tahoe support.
376 * configure: Regenerate.
378 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
380 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
382 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
384 * i386-tbl.h: Regenerated.
386 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
388 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
389 PREFIX_MOD_1_0FAE_REG_6.
391 (OP_E_register): Use va_mode.
392 * i386-dis-evex.h (prefix_table):
393 New instructions (see prefixes above).
394 * i386-gen.c (cpu_flag_init): Add WAITPKG.
395 (cpu_flags): Likewise.
396 * i386-opc.h (enum): Likewise.
397 (i386_cpu_flags): Likewise.
398 * i386-opc.tbl: Add umonitor, umwait, tpause.
399 * i386-init.h: Regenerate.
400 * i386-tbl.h: Likewise.
402 2018-04-11 Alan Modra <amodra@gmail.com>
404 * opcodes/i860-dis.c: Delete.
405 * opcodes/i960-dis.c: Delete.
406 * Makefile.am: Remove i860 and i960 support.
407 * configure.ac: Likewise.
408 * disassemble.c: Likewise.
409 * disassemble.h: Likewise.
410 * Makefile.in: Regenerate.
411 * configure: Regenerate.
412 * po/POTFILES.in: Regenerate.
414 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
417 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
419 (print_insn): Clear vex instead of vex.evex.
421 2018-04-04 Nick Clifton <nickc@redhat.com>
423 * po/es.po: Updated Spanish translation.
425 2018-03-28 Jan Beulich <jbeulich@suse.com>
427 * i386-gen.c (opcode_modifiers): Delete VecESize.
428 * i386-opc.h (VecESize): Delete.
429 (struct i386_opcode_modifier): Delete vecesize.
430 * i386-opc.tbl: Drop VecESize.
431 * i386-tlb.h: Re-generate.
433 2018-03-28 Jan Beulich <jbeulich@suse.com>
435 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
436 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
437 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
438 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
439 * i386-tlb.h: Re-generate.
441 2018-03-28 Jan Beulich <jbeulich@suse.com>
443 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
445 * i386-tlb.h: Re-generate.
447 2018-03-28 Jan Beulich <jbeulich@suse.com>
449 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
450 (vex_len_table): Drop Y for vcvt*2si.
451 (putop): Replace plain 'Y' handling by abort().
453 2018-03-28 Nick Clifton <nickc@redhat.com>
456 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
457 instructions with only a base address register.
458 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
459 handle AARHC64_OPND_SVE_ADDR_R.
460 (aarch64_print_operand): Likewise.
461 * aarch64-asm-2.c: Regenerate.
462 * aarch64_dis-2.c: Regenerate.
463 * aarch64-opc-2.c: Regenerate.
465 2018-03-22 Jan Beulich <jbeulich@suse.com>
467 * i386-opc.tbl: Drop VecESize from register only insn forms and
468 memory forms not allowing broadcast.
469 * i386-tlb.h: Re-generate.
471 2018-03-22 Jan Beulich <jbeulich@suse.com>
473 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
474 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
475 sha256*): Drop Disp<N>.
477 2018-03-22 Jan Beulich <jbeulich@suse.com>
479 * i386-dis.c (EbndS, bnd_swap_mode): New.
480 (prefix_table): Use EbndS.
481 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
482 * i386-opc.tbl (bndmov): Move misplaced Load.
483 * i386-tlb.h: Re-generate.
485 2018-03-22 Jan Beulich <jbeulich@suse.com>
487 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
488 templates allowing memory operands and folded ones for register
490 * i386-tlb.h: Re-generate.
492 2018-03-22 Jan Beulich <jbeulich@suse.com>
494 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
495 256-bit templates. Drop redundant leftover Disp<N>.
496 * i386-tlb.h: Re-generate.
498 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
500 * riscv-opc.c (riscv_insn_types): New.
502 2018-03-13 Nick Clifton <nickc@redhat.com>
504 * po/pt_BR.po: Updated Brazilian Portuguese translation.
506 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
508 * i386-opc.tbl: Add Optimize to clr.
509 * i386-tbl.h: Regenerated.
511 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
513 * i386-gen.c (opcode_modifiers): Remove OldGcc.
514 * i386-opc.h (OldGcc): Removed.
515 (i386_opcode_modifier): Remove oldgcc.
516 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
517 instructions for old (<= 2.8.1) versions of gcc.
518 * i386-tbl.h: Regenerated.
520 2018-03-08 Jan Beulich <jbeulich@suse.com>
522 * i386-opc.h (EVEXDYN): New.
523 * i386-opc.tbl: Fold various AVX512VL templates.
524 * i386-tlb.h: Re-generate.
526 2018-03-08 Jan Beulich <jbeulich@suse.com>
528 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
529 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
530 vpexpandd, vpexpandq): Fold AFX512VF templates.
531 * i386-tlb.h: Re-generate.
533 2018-03-08 Jan Beulich <jbeulich@suse.com>
535 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
536 Fold 128- and 256-bit VEX-encoded templates.
537 * i386-tlb.h: Re-generate.
539 2018-03-08 Jan Beulich <jbeulich@suse.com>
541 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
542 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
543 vpexpandd, vpexpandq): Fold AVX512F templates.
544 * i386-tlb.h: Re-generate.
546 2018-03-08 Jan Beulich <jbeulich@suse.com>
548 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
549 64-bit templates. Drop Disp<N>.
550 * i386-tlb.h: Re-generate.
552 2018-03-08 Jan Beulich <jbeulich@suse.com>
554 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
555 and 256-bit templates.
556 * i386-tlb.h: Re-generate.
558 2018-03-08 Jan Beulich <jbeulich@suse.com>
560 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
561 * i386-tlb.h: Re-generate.
563 2018-03-08 Jan Beulich <jbeulich@suse.com>
565 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
567 * i386-tlb.h: Re-generate.
569 2018-03-08 Jan Beulich <jbeulich@suse.com>
571 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
572 * i386-tlb.h: Re-generate.
574 2018-03-08 Jan Beulich <jbeulich@suse.com>
576 * i386-gen.c (opcode_modifiers): Delete FloatD.
577 * i386-opc.h (FloatD): Delete.
578 (struct i386_opcode_modifier): Delete floatd.
579 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
581 * i386-tlb.h: Re-generate.
583 2018-03-08 Jan Beulich <jbeulich@suse.com>
585 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
587 2018-03-08 Jan Beulich <jbeulich@suse.com>
589 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
590 * i386-tlb.h: Re-generate.
592 2018-03-08 Jan Beulich <jbeulich@suse.com>
594 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
596 * i386-tlb.h: Re-generate.
598 2018-03-07 Alan Modra <amodra@gmail.com>
600 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
602 * disassemble.h (print_insn_rs6000): Delete.
603 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
604 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
605 (print_insn_rs6000): Delete.
607 2018-03-03 Alan Modra <amodra@gmail.com>
609 * sysdep.h (opcodes_error_handler): Define.
610 (_bfd_error_handler): Declare.
611 * Makefile.am: Remove stray #.
612 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
614 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
615 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
616 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
617 opcodes_error_handler to print errors. Standardize error messages.
618 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
619 and include opintl.h.
620 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
621 * i386-gen.c: Standardize error messages.
622 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
623 * Makefile.in: Regenerate.
624 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
625 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
626 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
627 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
628 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
629 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
630 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
631 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
632 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
633 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
634 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
635 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
636 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
638 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
640 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
641 vpsub[bwdq] instructions.
642 * i386-tbl.h: Regenerated.
644 2018-03-01 Alan Modra <amodra@gmail.com>
646 * configure.ac (ALL_LINGUAS): Sort.
647 * configure: Regenerate.
649 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
651 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
652 macro by assignements.
654 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
657 * i386-gen.c (opcode_modifiers): Add Optimize.
658 * i386-opc.h (Optimize): New enum.
659 (i386_opcode_modifier): Add optimize.
660 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
661 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
662 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
663 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
664 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
666 * i386-tbl.h: Regenerated.
668 2018-02-26 Alan Modra <amodra@gmail.com>
670 * crx-dis.c (getregliststring): Allocate a large enough buffer
671 to silence false positive gcc8 warning.
673 2018-02-22 Shea Levy <shea@shealevy.com>
675 * disassemble.c (ARCH_riscv): Define if ARCH_all.
677 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
679 * i386-opc.tbl: Add {rex},
680 * i386-tbl.h: Regenerated.
682 2018-02-20 Maciej W. Rozycki <macro@mips.com>
684 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
685 (mips16_opcodes): Replace `M' with `m' for "restore".
687 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
689 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
691 2018-02-13 Maciej W. Rozycki <macro@mips.com>
693 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
694 variable to `function_index'.
696 2018-02-13 Nick Clifton <nickc@redhat.com>
699 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
700 about truncation of printing.
702 2018-02-12 Henry Wong <henry@stuffedcow.net>
704 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
706 2018-02-05 Nick Clifton <nickc@redhat.com>
708 * po/pt_BR.po: Updated Brazilian Portuguese translation.
710 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
712 * i386-dis.c (enum): Add pconfig.
713 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
714 (cpu_flags): Add CpuPCONFIG.
715 * i386-opc.h (enum): Add CpuPCONFIG.
716 (i386_cpu_flags): Add cpupconfig.
717 * i386-opc.tbl: Add PCONFIG instruction.
718 * i386-init.h: Regenerate.
719 * i386-tbl.h: Likewise.
721 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
723 * i386-dis.c (enum): Add PREFIX_0F09.
724 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
725 (cpu_flags): Add CpuWBNOINVD.
726 * i386-opc.h (enum): Add CpuWBNOINVD.
727 (i386_cpu_flags): Add cpuwbnoinvd.
728 * i386-opc.tbl: Add WBNOINVD instruction.
729 * i386-init.h: Regenerate.
730 * i386-tbl.h: Likewise.
732 2018-01-17 Jim Wilson <jimw@sifive.com>
734 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
736 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
738 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
739 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
740 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
741 (cpu_flags): Add CpuIBT, CpuSHSTK.
742 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
743 (i386_cpu_flags): Add cpuibt, cpushstk.
744 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
745 * i386-init.h: Regenerate.
746 * i386-tbl.h: Likewise.
748 2018-01-16 Nick Clifton <nickc@redhat.com>
750 * po/pt_BR.po: Updated Brazilian Portugese translation.
751 * po/de.po: Updated German translation.
753 2018-01-15 Jim Wilson <jimw@sifive.com>
755 * riscv-opc.c (match_c_nop): New.
756 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
758 2018-01-15 Nick Clifton <nickc@redhat.com>
760 * po/uk.po: Updated Ukranian translation.
762 2018-01-13 Nick Clifton <nickc@redhat.com>
764 * po/opcodes.pot: Regenerated.
766 2018-01-13 Nick Clifton <nickc@redhat.com>
768 * configure: Regenerate.
770 2018-01-13 Nick Clifton <nickc@redhat.com>
774 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
776 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
777 * i386-tbl.h: Regenerate.
779 2018-01-10 Jan Beulich <jbeulich@suse.com>
781 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
782 * i386-tbl.h: Re-generate.
784 2018-01-10 Jan Beulich <jbeulich@suse.com>
786 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
787 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
788 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
789 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
790 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
791 Disp8MemShift of AVX512VL forms.
792 * i386-tbl.h: Re-generate.
794 2018-01-09 Jim Wilson <jimw@sifive.com>
796 * riscv-dis.c (maybe_print_address): If base_reg is zero,
797 then the hi_addr value is zero.
799 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
801 * arm-dis.c (arm_opcodes): Add csdb.
802 (thumb32_opcodes): Add csdb.
804 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
806 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
807 * aarch64-asm-2.c: Regenerate.
808 * aarch64-dis-2.c: Regenerate.
809 * aarch64-opc-2.c: Regenerate.
811 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
814 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
815 Remove AVX512 vmovd with 64-bit operands.
816 * i386-tbl.h: Regenerated.
818 2018-01-05 Jim Wilson <jimw@sifive.com>
820 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
823 2018-01-03 Alan Modra <amodra@gmail.com>
825 Update year range in copyright notice of all files.
827 2018-01-02 Jan Beulich <jbeulich@suse.com>
829 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
830 and OPERAND_TYPE_REGZMM entries.
832 For older changes see ChangeLog-2017
834 Copyright (C) 2018 Free Software Foundation, Inc.
836 Copying and distribution of this file, with or without modification,
837 are permitted in any medium without royalty provided the copyright
838 notice and this notice are preserved.
844 version-control: never