1 2018-11-12 Sudakshina Das <sudi.das@arm.com>
3 * aarch64-opc.c (aarch64_sys_regs_dc): New entries for
4 IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
5 IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
7 (aarch64_sys_ins_reg_supported_p): New check for above.
9 2018-11-12 Sudakshina Das <sudi.das@arm.com>
11 * aarch64-opc.c (aarch64_sys_regs): New entries for TCO,
12 TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12,
14 (aarch64_sys_reg_supported_p): New check for above.
15 (aarch64_pstatefields): New entry for TCO.
16 (aarch64_pstatefield_supported_p): New check for above.
18 2018-11-12 Sudakshina Das <sudi.das@arm.com>
20 * aarch64-asm.c (aarch64_ins_addr_simple_2): New.
21 * aarch64-asm.h (ins_addr_simple_2): Declare the above.
22 * aarch64-dis.c (aarch64_ext_addr_simple_2): New.
23 * aarch64-dis.h (ext_addr_simple_2): Declare the above.
24 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
25 AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
26 (aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2.
27 * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
28 (AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
29 * aarch64-asm-2.c: Regenerated.
30 * aarch64-dis-2.c: Regenerated.
31 * aarch64-opc-2.c: Regenerated.
33 2018-11-12 Sudakshina Das <sudi.das@arm.com>
35 * aarch64-tbl.h (QL_LDG): New.
36 (aarch64_opcode_table): Add ldg.
37 * aarch64-asm-2.c: Regenerated.
38 * aarch64-dis-2.c: Regenerated.
39 * aarch64-opc-2.c: Regenerated.
41 2018-11-12 Sudakshina Das <sudi.das@arm.com>
43 * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
44 for AARCH64_OPND_QLF_imm_tag.
45 (operand_general_constraint_met_p): Add case for
46 AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
47 (aarch64_print_operand): Likewise.
48 * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
49 (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
50 for both offset and pre/post indexed versions.
51 (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
52 * aarch64-asm-2.c: Regenerated.
53 * aarch64-dis-2.c: Regenerated.
54 * aarch64-opc-2.c: Regenerated.
56 2018-11-12 Sudakshina Das <sudi.das@arm.com>
58 * aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp.
59 * aarch64-asm-2.c: Regenerated.
60 * aarch64-dis-2.c: Regenerated.
61 * aarch64-opc-2.c: Regenerated.
63 2018-11-12 Sudakshina Das <sudi.das@arm.com>
65 * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
66 (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
67 * aarch64-opc.c (fields): Add entry for imm4_3.
68 (operand_general_constraint_met_p): Add cases for
69 AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
70 (aarch64_print_operand): Likewise.
71 * aarch64-tbl.h (QL_ADDG): New.
72 (aarch64_opcode_table): Add addg, subg, irg and gmi.
73 (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
74 * aarch64-asm.c (aarch64_ins_imm): Add case for
75 operand_need_shift_by_four.
76 * aarch64-asm-2.c: Regenerated.
77 * aarch64-dis-2.c: Regenerated.
78 * aarch64-opc-2.c: Regenerated.
80 2018-11-12 Sudakshina Das <sudi.das@arm.com>
82 * aarch64-tbl.h (aarch64_feature_memtag): New.
83 (MEMTAG, MEMTAG_INSN): New.
85 2018-11-06 Sudakshina Das <sudi.das@arm.com>
87 * arm-dis.c (select_arm_features): Update bfd_mach_arm_8
88 with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML.
90 2018-11-06 Alan Modra <amodra@gmail.com>
92 * ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls),
93 (insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0),
94 (insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16),
95 (insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd):
96 Don't return zero on error, insert mask bits instead.
97 (insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete.
98 (insert_sh6, extract_sh6): Delete dead code.
99 (insert_sprbat, insert_sprg): Use unsigned comparisions.
100 (powerpc_operands <OIMM>): Set shift count rather than using
102 <SE_SDH, SE_SDW>: Likewise. Don't use insert/extract functions.
104 2018-11-06 Jan Beulich <jbeulich@suse.com>
106 * i386-dis-evex.h (evex_table): Use K suffix instead of %LW for
107 vpbroadcast{d,q} with GPR operand.
109 2018-11-06 Jan Beulich <jbeulich@suse.com>
111 * i386-dis.c (EVEX_W_0F6E_P_2, EVEX_W_0F7E_P_2): Delete.
112 * i386-dis-evex.h (evex_table): Move vmov[dq} with GPR operand
113 cases up one level in the hierarchy.
115 2018-11-06 Jan Beulich <jbeulich@suse.com>
117 * i386-dis.c (MOD_VEX_W_0_0F92_P_3_LEN_0,
118 MOD_VEX_W_1_0F92_P_3_LEN_0): Fold into MOD_VEX_0F92_P_3_LEN_0.
119 (MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0): Fold
120 into MOD_VEX_0F93_P_3_LEN_0.
121 (vex_len_table, vex_w_table, mod_table): Move kmov[dq} with GPR
122 operand cases up one level in the hierarchy.
124 2018-11-06 Jan Beulich <jbeulich@suse.com>
126 * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2,
127 VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2,
128 EVEX_W_0F3A22_P_2): Delete.
129 (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w}
130 entries up one level in the hierarchy.
131 (OP_E_memory): Handle dq_mode when determining Disp8 shift
133 * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q}
134 entries up one level in the hierarchy.
135 * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to
136 VexWIG for AVX flavors.
137 * i386-tbl.h: Re-generate.
139 2018-11-06 Jan Beulich <jbeulich@suse.com>
141 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
142 vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
143 vcvtusi2ss, kmovd): Drop VexW=1.
144 * i386-tbl.h: Re-generate.
146 2018-11-06 Jan Beulich <jbeulich@suse.com>
148 * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
149 EVex512, EVexLIG, EVexDYN): New.
150 (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
151 insns): Use Vex128 instead of Vex=3 (aka VexLIG).
152 (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
153 of EVex=4 (aka EVexLIG).
154 * i386-tbl.h: Re-generate.
156 2018-11-06 Jan Beulich <jbeulich@suse.com>
158 * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
159 (vpmaxub): Re-order attributes on AVX512BW flavor.
160 * i386-tbl.h: Re-generate.
162 2018-11-06 Jan Beulich <jbeulich@suse.com>
164 * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
165 vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
166 Vex=1 on AVX / AVX2 flavors.
167 (vpmaxub): Re-order attributes on AVX512BW flavor.
168 * i386-tbl.h: Re-generate.
170 2018-11-06 Jan Beulich <jbeulich@suse.com>
172 * i386-opc.tbl (VexW0, VexW1): New.
173 (vphadd*, vphsub*): Use VexW0 on XOP variants.
174 * i386-tbl.h: Re-generate.
176 2018-10-22 John Darrington <john@darrington.wattle.id.au>
178 * s12z-dis.c (decode_possible_symbol): Add fallback case.
179 (rel_15_7): Likewise.
181 2018-10-19 Tamar Christina <tamar.christina@arm.com>
183 * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
184 (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
185 (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
187 2018-10-16 Matthew Malcomson <matthew.malcomson@arm.com>
189 * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
190 corresponding to AARCH64_OPND_QLF_S_4B qualifier.
192 2018-10-10 Jan Beulich <jbeulich@suse.com>
194 * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
196 * i386-opc.h (Size16, Size32, Size64): Delete.
198 (SIZE16, SIZE32, SIZE64): Define.
199 (struct i386_opcode_modifier): Drop size16, size32, and size64.
201 * i386-opc.tbl (Size16, Size32, Size64): Define.
202 * i386-tbl.h: Re-generate.
204 2018-10-09 Sudakshina Das <sudi.das@arm.com>
206 * aarch64-opc.c (operand_general_constraint_met_p): Add
207 SSBS in the check for one-bit immediate.
208 (aarch64_sys_regs): New entry for SSBS.
209 (aarch64_sys_reg_supported_p): New check for above.
210 (aarch64_pstatefields): New entry for SSBS.
211 (aarch64_pstatefield_supported_p): New check for above.
213 2018-10-09 Sudakshina Das <sudi.das@arm.com>
215 * aarch64-opc.c (aarch64_sys_regs): New entries for
216 scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
217 (aarch64_sys_reg_supported_p): New checks for above.
219 2018-10-09 Sudakshina Das <sudi.das@arm.com>
221 * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
222 (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
223 with the hint immediate.
224 * aarch64-opc.c (aarch64_hint_options): New entries for
225 c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
226 (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
227 while checking for HINT_OPD_F_NOPRINT flag.
228 * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
230 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
231 (aarch64_opcode_table): Add entry for BTI.
232 (AARCH64_OPERANDS): Add new description for BTI targets.
233 * aarch64-asm-2.c: Regenerate.
234 * aarch64-dis-2.c: Regenerate.
235 * aarch64-opc-2.c: Regenerate.
237 2018-10-09 Sudakshina Das <sudi.das@arm.com>
239 * aarch64-opc.c (aarch64_sys_regs): New entries for
241 (aarch64_sys_reg_supported_p): New check for above.
243 2018-10-09 Sudakshina Das <sudi.das@arm.com>
245 * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
246 (aarch64_sys_ins_reg_supported_p): New check for above.
248 2018-10-09 Sudakshina Das <sudi.das@arm.com>
250 * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
251 AARCH64_OPND_SYSREG_SR.
252 * aarch64-opc.c (aarch64_print_operand): Likewise.
253 (aarch64_sys_regs_sr): Define table.
254 (aarch64_sys_ins_reg_supported_p): Check for RCTX with
255 AARCH64_FEATURE_PREDRES.
256 * aarch64-tbl.h (aarch64_feature_predres): New.
257 (PREDRES, PREDRES_INSN): New.
258 (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
259 (AARCH64_OPERANDS): Add new description for SYSREG_SR.
260 * aarch64-asm-2.c: Regenerate.
261 * aarch64-dis-2.c: Regenerate.
262 * aarch64-opc-2.c: Regenerate.
264 2018-10-09 Sudakshina Das <sudi.das@arm.com>
266 * aarch64-tbl.h (aarch64_feature_sb): New.
268 (aarch64_opcode_table): Add entry for sb.
269 * aarch64-asm-2.c: Regenerate.
270 * aarch64-dis-2.c: Regenerate.
271 * aarch64-opc-2.c: Regenerate.
273 2018-10-09 Sudakshina Das <sudi.das@arm.com>
275 * aarch64-tbl.h (aarch64_feature_flagmanip): New.
276 (aarch64_feature_frintts): New.
277 (FLAGMANIP, FRINTTS): New.
278 (aarch64_opcode_table): Add entries for xaflag, axflag
279 and frint[32,64][x,z] instructions.
280 * aarch64-asm-2.c: Regenerate.
281 * aarch64-dis-2.c: Regenerate.
282 * aarch64-opc-2.c: Regenerate.
284 2018-10-09 Sudakshina Das <sudi.das@arm.com>
286 * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
287 (ARMV8_5, V8_5_INSN): New.
289 2018-10-08 Tamar Christina <tamar.christina@arm.com>
291 * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
293 2018-10-05 H.J. Lu <hongjiu.lu@intel.com>
295 * i386-dis.c (rm_table): Add enclv.
296 * i386-opc.tbl: Add enclv.
297 * i386-tbl.h: Regenerated.
299 2018-10-05 Sudakshina Das <sudi.das@arm.com>
301 * arm-dis.c (arm_opcodes): Add sb.
302 (thumb32_opcodes): Likewise.
304 2018-10-05 Richard Henderson <rth@twiddle.net>
305 Stafford Horne <shorne@gmail.com>
307 * or1k-desc.c: Regenerate.
308 * or1k-desc.h: Regenerate.
309 * or1k-opc.c: Regenerate.
310 * or1k-opc.h: Regenerate.
311 * or1k-opinst.c: Regenerate.
313 2018-10-05 Richard Henderson <rth@twiddle.net>
315 * or1k-asm.c: Regenerated.
316 * or1k-desc.c: Regenerated.
317 * or1k-desc.h: Regenerated.
318 * or1k-dis.c: Regenerated.
319 * or1k-ibld.c: Regenerated.
320 * or1k-opc.c: Regenerated.
321 * or1k-opc.h: Regenerated.
322 * or1k-opinst.c: Regenerated.
324 2018-10-05 Richard Henderson <rth@twiddle.net>
326 * or1k-asm.c: Regenerate.
328 2018-10-03 Tamar Christina <tamar.christina@arm.com>
330 * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
331 * aarch64-dis.c (print_operands): Refactor to take notes.
332 (print_verifier_notes): New.
333 (print_aarch64_insn): Apply constraint verifier.
334 (print_insn_aarch64_word): Update call to print_aarch64_insn.
335 * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
337 2018-10-03 Tamar Christina <tamar.christina@arm.com>
339 * aarch64-opc.c (init_insn_block): New.
340 (verify_constraints, aarch64_is_destructive_by_operands): New.
341 * aarch64-opc.h (verify_constraints): New.
343 2018-10-03 Tamar Christina <tamar.christina@arm.com>
345 * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
346 * aarch64-opc.c (verify_ldpsw): Update arguments.
348 2018-10-03 Tamar Christina <tamar.christina@arm.com>
350 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
351 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
353 2018-10-03 Tamar Christina <tamar.christina@arm.com>
355 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
356 * aarch64-dis.c (insn_sequence): New.
358 2018-10-03 Tamar Christina <tamar.christina@arm.com>
360 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
361 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
362 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
363 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
366 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
368 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
370 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
371 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
372 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
373 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
374 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
375 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
376 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
378 2018-10-02 Palmer Dabbelt <palmer@sifive.com>
380 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
382 2018-09-23 Sandra Loosemore <sandra@codesourcery.com>
384 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
385 are used when extracting signed fields and converting them to
386 potentially 64-bit types.
388 2018-09-21 Simon Marchi <simon.marchi@ericsson.com>
390 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
391 * Makefile.in: Re-generate.
392 * aclocal.m4: Re-generate.
393 * configure: Re-generate.
394 * configure.ac: Remove check for -Wno-missing-field-initializers.
395 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
396 (csky_v2_opcodes): Likewise.
398 2018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
400 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
402 2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
404 * nds32-asm.c (operand_fields): Remove the unused fields.
405 (nds32_opcodes): Remove the unused instructions.
406 * nds32-dis.c (nds32_ex9_info): Removed.
407 (nds32_parse_opcode): Updated.
408 (print_insn_nds32): Likewise.
409 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
410 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
411 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
412 build_opcode_hash_table): New functions.
413 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
414 nds32_opcode_table): New.
415 (hw_ktabs): Declare it to a pointer rather than an array.
416 (build_hash_table): Removed.
417 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
418 SYN_ROPT and upadte HW_GPR and HW_INT.
419 * nds32-dis.c (keywords): Remove const.
420 (match_field): New function.
421 (nds32_parse_opcode): Updated.
422 * disassemble.c (disassemble_init_for_target):
423 Add disassemble_init_nds32.
424 * nds32-dis.c (eum map_type): New.
425 (nds32_private_data): Likewise.
426 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
427 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
428 (print_insn_nds32): Updated.
429 * nds32-asm.c (parse_aext_reg): Add new parameter.
430 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
433 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
434 (operand_fields): Add new fields.
435 (nds32_opcodes): Add new instructions.
436 (keyword_aridxi_mx): New keyword.
437 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
439 (ALU2_1, ALU2_2, ALU2_3): New macros.
440 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
442 2018-09-17 Kito Cheng <kito@andestech.com>
444 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
446 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
449 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
450 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
451 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
452 (EVEX_LEN_0F7E_P_1): Likewise.
453 (EVEX_LEN_0F7E_P_2): Likewise.
454 (EVEX_LEN_0FD6_P_2): Likewise.
455 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
456 (EVEX_LEN_TABLE): Likewise.
457 (EVEX_LEN_0F6E_P_2): New enum.
458 (EVEX_LEN_0F7E_P_1): Likewise.
459 (EVEX_LEN_0F7E_P_2): Likewise.
460 (EVEX_LEN_0FD6_P_2): Likewise.
461 (evex_len_table): New.
462 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
463 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
464 * i386-tbl.h: Regenerated.
466 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
469 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
470 VEX_LEN_0F7E_P_2 entries.
471 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
472 * i386-tbl.h: Regenerated.
474 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
476 * i386-dis.c (VZERO_Fixup): Removed.
478 (VEX_LEN_0F10_P_1): Likewise.
479 (VEX_LEN_0F10_P_3): Likewise.
480 (VEX_LEN_0F11_P_1): Likewise.
481 (VEX_LEN_0F11_P_3): Likewise.
482 (VEX_LEN_0F2E_P_0): Likewise.
483 (VEX_LEN_0F2E_P_2): Likewise.
484 (VEX_LEN_0F2F_P_0): Likewise.
485 (VEX_LEN_0F2F_P_2): Likewise.
486 (VEX_LEN_0F51_P_1): Likewise.
487 (VEX_LEN_0F51_P_3): Likewise.
488 (VEX_LEN_0F52_P_1): Likewise.
489 (VEX_LEN_0F53_P_1): Likewise.
490 (VEX_LEN_0F58_P_1): Likewise.
491 (VEX_LEN_0F58_P_3): Likewise.
492 (VEX_LEN_0F59_P_1): Likewise.
493 (VEX_LEN_0F59_P_3): Likewise.
494 (VEX_LEN_0F5A_P_1): Likewise.
495 (VEX_LEN_0F5A_P_3): Likewise.
496 (VEX_LEN_0F5C_P_1): Likewise.
497 (VEX_LEN_0F5C_P_3): Likewise.
498 (VEX_LEN_0F5D_P_1): Likewise.
499 (VEX_LEN_0F5D_P_3): Likewise.
500 (VEX_LEN_0F5E_P_1): Likewise.
501 (VEX_LEN_0F5E_P_3): Likewise.
502 (VEX_LEN_0F5F_P_1): Likewise.
503 (VEX_LEN_0F5F_P_3): Likewise.
504 (VEX_LEN_0FC2_P_1): Likewise.
505 (VEX_LEN_0FC2_P_3): Likewise.
506 (VEX_LEN_0F3A0A_P_2): Likewise.
507 (VEX_LEN_0F3A0B_P_2): Likewise.
508 (VEX_W_0F10_P_0): Likewise.
509 (VEX_W_0F10_P_1): Likewise.
510 (VEX_W_0F10_P_2): Likewise.
511 (VEX_W_0F10_P_3): Likewise.
512 (VEX_W_0F11_P_0): Likewise.
513 (VEX_W_0F11_P_1): Likewise.
514 (VEX_W_0F11_P_2): Likewise.
515 (VEX_W_0F11_P_3): Likewise.
516 (VEX_W_0F12_P_0_M_0): Likewise.
517 (VEX_W_0F12_P_0_M_1): Likewise.
518 (VEX_W_0F12_P_1): Likewise.
519 (VEX_W_0F12_P_2): Likewise.
520 (VEX_W_0F12_P_3): Likewise.
521 (VEX_W_0F13_M_0): Likewise.
522 (VEX_W_0F14): Likewise.
523 (VEX_W_0F15): Likewise.
524 (VEX_W_0F16_P_0_M_0): Likewise.
525 (VEX_W_0F16_P_0_M_1): Likewise.
526 (VEX_W_0F16_P_1): Likewise.
527 (VEX_W_0F16_P_2): Likewise.
528 (VEX_W_0F17_M_0): Likewise.
529 (VEX_W_0F28): Likewise.
530 (VEX_W_0F29): Likewise.
531 (VEX_W_0F2B_M_0): Likewise.
532 (VEX_W_0F2E_P_0): Likewise.
533 (VEX_W_0F2E_P_2): Likewise.
534 (VEX_W_0F2F_P_0): Likewise.
535 (VEX_W_0F2F_P_2): Likewise.
536 (VEX_W_0F50_M_0): Likewise.
537 (VEX_W_0F51_P_0): Likewise.
538 (VEX_W_0F51_P_1): Likewise.
539 (VEX_W_0F51_P_2): Likewise.
540 (VEX_W_0F51_P_3): Likewise.
541 (VEX_W_0F52_P_0): Likewise.
542 (VEX_W_0F52_P_1): Likewise.
543 (VEX_W_0F53_P_0): Likewise.
544 (VEX_W_0F53_P_1): Likewise.
545 (VEX_W_0F58_P_0): Likewise.
546 (VEX_W_0F58_P_1): Likewise.
547 (VEX_W_0F58_P_2): Likewise.
548 (VEX_W_0F58_P_3): Likewise.
549 (VEX_W_0F59_P_0): Likewise.
550 (VEX_W_0F59_P_1): Likewise.
551 (VEX_W_0F59_P_2): Likewise.
552 (VEX_W_0F59_P_3): Likewise.
553 (VEX_W_0F5A_P_0): Likewise.
554 (VEX_W_0F5A_P_1): Likewise.
555 (VEX_W_0F5A_P_3): Likewise.
556 (VEX_W_0F5B_P_0): Likewise.
557 (VEX_W_0F5B_P_1): Likewise.
558 (VEX_W_0F5B_P_2): Likewise.
559 (VEX_W_0F5C_P_0): Likewise.
560 (VEX_W_0F5C_P_1): Likewise.
561 (VEX_W_0F5C_P_2): Likewise.
562 (VEX_W_0F5C_P_3): Likewise.
563 (VEX_W_0F5D_P_0): Likewise.
564 (VEX_W_0F5D_P_1): Likewise.
565 (VEX_W_0F5D_P_2): Likewise.
566 (VEX_W_0F5D_P_3): Likewise.
567 (VEX_W_0F5E_P_0): Likewise.
568 (VEX_W_0F5E_P_1): Likewise.
569 (VEX_W_0F5E_P_2): Likewise.
570 (VEX_W_0F5E_P_3): Likewise.
571 (VEX_W_0F5F_P_0): Likewise.
572 (VEX_W_0F5F_P_1): Likewise.
573 (VEX_W_0F5F_P_2): Likewise.
574 (VEX_W_0F5F_P_3): Likewise.
575 (VEX_W_0F60_P_2): Likewise.
576 (VEX_W_0F61_P_2): Likewise.
577 (VEX_W_0F62_P_2): Likewise.
578 (VEX_W_0F63_P_2): Likewise.
579 (VEX_W_0F64_P_2): Likewise.
580 (VEX_W_0F65_P_2): Likewise.
581 (VEX_W_0F66_P_2): Likewise.
582 (VEX_W_0F67_P_2): Likewise.
583 (VEX_W_0F68_P_2): Likewise.
584 (VEX_W_0F69_P_2): Likewise.
585 (VEX_W_0F6A_P_2): Likewise.
586 (VEX_W_0F6B_P_2): Likewise.
587 (VEX_W_0F6C_P_2): Likewise.
588 (VEX_W_0F6D_P_2): Likewise.
589 (VEX_W_0F6F_P_1): Likewise.
590 (VEX_W_0F6F_P_2): Likewise.
591 (VEX_W_0F70_P_1): Likewise.
592 (VEX_W_0F70_P_2): Likewise.
593 (VEX_W_0F70_P_3): Likewise.
594 (VEX_W_0F71_R_2_P_2): Likewise.
595 (VEX_W_0F71_R_4_P_2): Likewise.
596 (VEX_W_0F71_R_6_P_2): Likewise.
597 (VEX_W_0F72_R_2_P_2): Likewise.
598 (VEX_W_0F72_R_4_P_2): Likewise.
599 (VEX_W_0F72_R_6_P_2): Likewise.
600 (VEX_W_0F73_R_2_P_2): Likewise.
601 (VEX_W_0F73_R_3_P_2): Likewise.
602 (VEX_W_0F73_R_6_P_2): Likewise.
603 (VEX_W_0F73_R_7_P_2): Likewise.
604 (VEX_W_0F74_P_2): Likewise.
605 (VEX_W_0F75_P_2): Likewise.
606 (VEX_W_0F76_P_2): Likewise.
607 (VEX_W_0F77_P_0): Likewise.
608 (VEX_W_0F7C_P_2): Likewise.
609 (VEX_W_0F7C_P_3): Likewise.
610 (VEX_W_0F7D_P_2): Likewise.
611 (VEX_W_0F7D_P_3): Likewise.
612 (VEX_W_0F7E_P_1): Likewise.
613 (VEX_W_0F7F_P_1): Likewise.
614 (VEX_W_0F7F_P_2): Likewise.
615 (VEX_W_0FAE_R_2_M_0): Likewise.
616 (VEX_W_0FAE_R_3_M_0): Likewise.
617 (VEX_W_0FC2_P_0): Likewise.
618 (VEX_W_0FC2_P_1): Likewise.
619 (VEX_W_0FC2_P_2): Likewise.
620 (VEX_W_0FC2_P_3): Likewise.
621 (VEX_W_0FD0_P_2): Likewise.
622 (VEX_W_0FD0_P_3): Likewise.
623 (VEX_W_0FD1_P_2): Likewise.
624 (VEX_W_0FD2_P_2): Likewise.
625 (VEX_W_0FD3_P_2): Likewise.
626 (VEX_W_0FD4_P_2): Likewise.
627 (VEX_W_0FD5_P_2): Likewise.
628 (VEX_W_0FD6_P_2): Likewise.
629 (VEX_W_0FD7_P_2_M_1): Likewise.
630 (VEX_W_0FD8_P_2): Likewise.
631 (VEX_W_0FD9_P_2): Likewise.
632 (VEX_W_0FDA_P_2): Likewise.
633 (VEX_W_0FDB_P_2): Likewise.
634 (VEX_W_0FDC_P_2): Likewise.
635 (VEX_W_0FDD_P_2): Likewise.
636 (VEX_W_0FDE_P_2): Likewise.
637 (VEX_W_0FDF_P_2): Likewise.
638 (VEX_W_0FE0_P_2): Likewise.
639 (VEX_W_0FE1_P_2): Likewise.
640 (VEX_W_0FE2_P_2): Likewise.
641 (VEX_W_0FE3_P_2): Likewise.
642 (VEX_W_0FE4_P_2): Likewise.
643 (VEX_W_0FE5_P_2): Likewise.
644 (VEX_W_0FE6_P_1): Likewise.
645 (VEX_W_0FE6_P_2): Likewise.
646 (VEX_W_0FE6_P_3): Likewise.
647 (VEX_W_0FE7_P_2_M_0): Likewise.
648 (VEX_W_0FE8_P_2): Likewise.
649 (VEX_W_0FE9_P_2): Likewise.
650 (VEX_W_0FEA_P_2): Likewise.
651 (VEX_W_0FEB_P_2): Likewise.
652 (VEX_W_0FEC_P_2): Likewise.
653 (VEX_W_0FED_P_2): Likewise.
654 (VEX_W_0FEE_P_2): Likewise.
655 (VEX_W_0FEF_P_2): Likewise.
656 (VEX_W_0FF0_P_3_M_0): Likewise.
657 (VEX_W_0FF1_P_2): Likewise.
658 (VEX_W_0FF2_P_2): Likewise.
659 (VEX_W_0FF3_P_2): Likewise.
660 (VEX_W_0FF4_P_2): Likewise.
661 (VEX_W_0FF5_P_2): Likewise.
662 (VEX_W_0FF6_P_2): Likewise.
663 (VEX_W_0FF7_P_2): Likewise.
664 (VEX_W_0FF8_P_2): Likewise.
665 (VEX_W_0FF9_P_2): Likewise.
666 (VEX_W_0FFA_P_2): Likewise.
667 (VEX_W_0FFB_P_2): Likewise.
668 (VEX_W_0FFC_P_2): Likewise.
669 (VEX_W_0FFD_P_2): Likewise.
670 (VEX_W_0FFE_P_2): Likewise.
671 (VEX_W_0F3800_P_2): Likewise.
672 (VEX_W_0F3801_P_2): Likewise.
673 (VEX_W_0F3802_P_2): Likewise.
674 (VEX_W_0F3803_P_2): Likewise.
675 (VEX_W_0F3804_P_2): Likewise.
676 (VEX_W_0F3805_P_2): Likewise.
677 (VEX_W_0F3806_P_2): Likewise.
678 (VEX_W_0F3807_P_2): Likewise.
679 (VEX_W_0F3808_P_2): Likewise.
680 (VEX_W_0F3809_P_2): Likewise.
681 (VEX_W_0F380A_P_2): Likewise.
682 (VEX_W_0F380B_P_2): Likewise.
683 (VEX_W_0F3817_P_2): Likewise.
684 (VEX_W_0F381C_P_2): Likewise.
685 (VEX_W_0F381D_P_2): Likewise.
686 (VEX_W_0F381E_P_2): Likewise.
687 (VEX_W_0F3820_P_2): Likewise.
688 (VEX_W_0F3821_P_2): Likewise.
689 (VEX_W_0F3822_P_2): Likewise.
690 (VEX_W_0F3823_P_2): Likewise.
691 (VEX_W_0F3824_P_2): Likewise.
692 (VEX_W_0F3825_P_2): Likewise.
693 (VEX_W_0F3828_P_2): Likewise.
694 (VEX_W_0F3829_P_2): Likewise.
695 (VEX_W_0F382A_P_2_M_0): Likewise.
696 (VEX_W_0F382B_P_2): Likewise.
697 (VEX_W_0F3830_P_2): Likewise.
698 (VEX_W_0F3831_P_2): Likewise.
699 (VEX_W_0F3832_P_2): Likewise.
700 (VEX_W_0F3833_P_2): Likewise.
701 (VEX_W_0F3834_P_2): Likewise.
702 (VEX_W_0F3835_P_2): Likewise.
703 (VEX_W_0F3837_P_2): Likewise.
704 (VEX_W_0F3838_P_2): Likewise.
705 (VEX_W_0F3839_P_2): Likewise.
706 (VEX_W_0F383A_P_2): Likewise.
707 (VEX_W_0F383B_P_2): Likewise.
708 (VEX_W_0F383C_P_2): Likewise.
709 (VEX_W_0F383D_P_2): Likewise.
710 (VEX_W_0F383E_P_2): Likewise.
711 (VEX_W_0F383F_P_2): Likewise.
712 (VEX_W_0F3840_P_2): Likewise.
713 (VEX_W_0F3841_P_2): Likewise.
714 (VEX_W_0F38DB_P_2): Likewise.
715 (VEX_W_0F3A08_P_2): Likewise.
716 (VEX_W_0F3A09_P_2): Likewise.
717 (VEX_W_0F3A0A_P_2): Likewise.
718 (VEX_W_0F3A0B_P_2): Likewise.
719 (VEX_W_0F3A0C_P_2): Likewise.
720 (VEX_W_0F3A0D_P_2): Likewise.
721 (VEX_W_0F3A0E_P_2): Likewise.
722 (VEX_W_0F3A0F_P_2): Likewise.
723 (VEX_W_0F3A21_P_2): Likewise.
724 (VEX_W_0F3A40_P_2): Likewise.
725 (VEX_W_0F3A41_P_2): Likewise.
726 (VEX_W_0F3A42_P_2): Likewise.
727 (VEX_W_0F3A62_P_2): Likewise.
728 (VEX_W_0F3A63_P_2): Likewise.
729 (VEX_W_0F3ADF_P_2): Likewise.
730 (VEX_LEN_0F77_P_0): New.
731 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
732 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
733 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
734 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
735 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
736 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
737 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
738 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
739 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
740 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
741 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
742 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
743 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
744 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
745 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
746 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
747 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
748 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
749 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
750 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
751 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
752 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
753 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
754 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
755 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
756 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
757 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
758 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
759 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
760 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
761 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
762 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
763 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
764 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
765 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
766 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
767 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
768 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
769 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
770 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
771 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
772 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
773 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
774 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
775 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
776 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
777 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
778 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
779 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
780 (vex_table): Update VEX 0F28 and 0F29 entries.
781 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
782 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
783 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
784 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
785 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
786 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
787 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
788 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
789 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
790 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
791 VEX_LEN_0F3A0B_P_2 entries.
792 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
793 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
794 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
795 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
796 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
797 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
798 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
799 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
800 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
801 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
802 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
803 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
804 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
805 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
806 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
807 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
808 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
809 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
810 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
811 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
812 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
813 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
814 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
815 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
816 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
817 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
818 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
819 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
820 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
821 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
822 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
823 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
824 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
825 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
826 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
827 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
828 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
829 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
830 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
831 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
832 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
833 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
834 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
835 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
836 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
837 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
838 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
839 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
840 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
841 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
842 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
843 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
844 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
845 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
846 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
847 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
848 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
849 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
850 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
851 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
852 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
853 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
854 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
855 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
856 VEX_W_0F3ADF_P_2 entries.
857 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
858 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
859 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
861 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
863 * i386-opc.tbl (VexWIG): New.
864 Replace VexW=3 with VexWIG.
866 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
868 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
869 * i386-tbl.h: Regenerated.
871 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
874 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
875 VEX_LEN_0FD6_P_2 entries.
876 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
877 * i386-tbl.h: Regenerated.
879 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
882 * i386-opc.h (VEXWIG): New.
883 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
884 * i386-tbl.h: Regenerated.
886 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
889 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
890 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
891 * i386-dis.c (EXxEVexR64): New.
892 (evex_rounding_64_mode): Likewise.
893 (OP_Rounding): Handle evex_rounding_64_mode.
895 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
898 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
899 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
900 * i386-dis.c (Edqa): New.
901 (dqa_mode): Likewise.
902 (intel_operand_size): Handle dqa_mode as m_mode.
903 (OP_E_register): Handle dqa_mode as dq_mode.
904 (OP_E_memory): Set shift for dqa_mode based on address_mode.
906 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
908 * i386-dis.c (OP_E_memory): Reformat.
910 2018-09-14 Jan Beulich <jbeulich@suse.com>
912 * i386-opc.tbl (crc32): Fold byte and word forms.
913 * i386-tbl.h: Re-generate.
915 2018-09-13 H.J. Lu <hongjiu.lu@intel.com>
917 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
918 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
919 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
920 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
921 * i386-tbl.h: Regenerated.
923 2018-09-13 Jan Beulich <jbeulich@suse.com>
925 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
927 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
928 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
929 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
930 * i386-tbl.h: Re-generate.
932 2018-09-13 Jan Beulich <jbeulich@suse.com>
934 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
936 * i386-tbl.h: Re-generate.
938 2018-09-13 Jan Beulich <jbeulich@suse.com>
940 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
942 * i386-tbl.h: Re-generate.
944 2018-09-13 Jan Beulich <jbeulich@suse.com>
946 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
948 * i386-tbl.h: Re-generate.
950 2018-09-13 Jan Beulich <jbeulich@suse.com>
952 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
954 * i386-tbl.h: Re-generate.
956 2018-09-13 Jan Beulich <jbeulich@suse.com>
958 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
960 * i386-tbl.h: Re-generate.
962 2018-09-13 Jan Beulich <jbeulich@suse.com>
964 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
966 * i386-tbl.h: Re-generate.
968 2018-09-13 Jan Beulich <jbeulich@suse.com>
970 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
971 * i386-tbl.h: Re-generate.
973 2018-09-13 Jan Beulich <jbeulich@suse.com>
975 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
976 * i386-tbl.h: Re-generate.
978 2018-09-13 Jan Beulich <jbeulich@suse.com>
980 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
982 * i386-tbl.h: Re-generate.
984 2018-09-13 Jan Beulich <jbeulich@suse.com>
986 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
988 * i386-tbl.h: Re-generate.
990 2018-09-13 Jan Beulich <jbeulich@suse.com>
992 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
993 * i386-tbl.h: Re-generate.
995 2018-09-13 Jan Beulich <jbeulich@suse.com>
997 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
998 * i386-tbl.h: Re-generate.
1000 2018-09-13 Jan Beulich <jbeulich@suse.com>
1002 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
1003 * i386-tbl.h: Re-generate.
1005 2018-09-13 Jan Beulich <jbeulich@suse.com>
1007 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
1009 * i386-tbl.h: Re-generate.
1011 2018-09-13 Jan Beulich <jbeulich@suse.com>
1013 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
1015 * i386-tbl.h: Re-generate.
1017 2018-09-13 Jan Beulich <jbeulich@suse.com>
1019 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
1021 * i386-tbl.h: Re-generate.
1023 2018-09-13 Jan Beulich <jbeulich@suse.com>
1025 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
1026 * i386-tbl.h: Re-generate.
1028 2018-09-13 Jan Beulich <jbeulich@suse.com>
1030 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
1031 * i386-tbl.h: Re-generate.
1033 2018-09-13 Jan Beulich <jbeulich@suse.com>
1035 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
1036 * i386-tbl.h: Re-generate.
1038 2018-09-13 Jan Beulich <jbeulich@suse.com>
1040 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
1041 (vpbroadcastw, rdpid): Drop NoRex64.
1042 * i386-tbl.h: Re-generate.
1044 2018-09-13 Jan Beulich <jbeulich@suse.com>
1046 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
1047 store templates, adding D.
1048 * i386-tbl.h: Re-generate.
1050 2018-09-13 Jan Beulich <jbeulich@suse.com>
1052 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
1053 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
1054 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
1055 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
1056 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
1057 Fold load and store templates where possible, adding D. Drop
1058 IgnoreSize where it was pointlessly present. Drop redundant
1060 * i386-tbl.h: Re-generate.
1062 2018-09-13 Jan Beulich <jbeulich@suse.com>
1064 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
1065 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
1066 (intel_operand_size): Handle v_bndmk_mode.
1067 (OP_E_memory): Likewise. Produce (bad) when also riprel.
1069 2018-09-08 John Darrington <john@darrington.wattle.id.au>
1071 * disassemble.c (ARCH_s12z): Define if ARCH_all.
1073 2018-08-31 Kito Cheng <kito@andestech.com>
1075 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
1076 compressed floating point instructions.
1078 2018-08-30 Kito Cheng <kito@andestech.com>
1080 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
1081 riscv_opcode.xlen_requirement.
1082 * riscv-opc.c (riscv_opcodes): Update for struct change.
1084 2018-08-29 Martin Aberg <maberg@gaisler.com>
1086 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
1087 psr (PWRPSR) instruction.
1089 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1091 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
1093 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1095 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
1097 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1099 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
1100 loongson3a as an alias of gs464 for compatibility.
1101 * mips-opc.c (mips_opcodes): Change Comments.
1103 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1105 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
1107 (print_mips_disassembler_options): Document -M loongson-ext.
1108 * mips-opc.c (LEXT2): New macro.
1109 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
1111 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1113 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
1115 (parse_mips_ase_option): Handle -M loongson-ext option.
1116 (print_mips_disassembler_options): Document -M loongson-ext.
1117 * mips-opc.c (IL3A): Delete.
1118 * mips-opc.c (LEXT): New macro.
1119 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
1122 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1124 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
1126 (parse_mips_ase_option): Handle -M loongson-cam option.
1127 (print_mips_disassembler_options): Document -M loongson-cam.
1128 * mips-opc.c (LCAM): New macro.
1129 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
1132 2018-08-21 Alan Modra <amodra@gmail.com>
1134 * ppc-dis.c (operand_value_powerpc): Init "invalid".
1135 (skip_optional_operands): Count optional operands, and update
1136 ppc_optional_operand_value call.
1137 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
1138 (extract_vlensi): Likewise.
1139 (extract_fxm): Return default value for missing optional operand.
1140 (extract_ls, extract_raq, extract_tbr): Likewise.
1141 (insert_sxl, extract_sxl): New functions.
1142 (insert_esync, extract_esync): Remove Power9 handling and simplify.
1143 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
1144 flag and extra entry.
1145 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
1148 2018-08-20 Alan Modra <amodra@gmail.com>
1150 * sh-opc.h (MASK): Simplify.
1152 2018-08-18 John Darrington <john@darrington.wattle.id.au>
1154 * s12z-dis.c (bm_decode): Deal with cases where the mode is
1155 BM_RESERVED0 or BM_RESERVED1
1156 (bm_rel_decode, bm_n_bytes): Ditto.
1158 2018-08-18 John Darrington <john@darrington.wattle.id.au>
1162 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
1164 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1165 address with the addr32 prefix and without base nor index
1168 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
1170 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1171 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1172 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1173 (cpu_flags): Add CpuCMOV and CpuFXSR.
1174 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1175 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
1176 * i386-init.h: Regenerated.
1177 * i386-tbl.h: Likewise.
1179 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
1181 * arc-regs.h: Update auxiliary registers.
1183 2018-08-06 Jan Beulich <jbeulich@suse.com>
1185 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1186 (RegIP, RegIZ): Define.
1187 * i386-reg.tbl: Adjust comments.
1188 (rip): Use Qword instead of BaseIndex. Use RegIP.
1189 (eip): Use Dword instead of BaseIndex. Use RegIP.
1190 (riz): Add Qword. Use RegIZ.
1191 (eiz): Add Dword. Use RegIZ.
1192 * i386-tbl.h: Re-generate.
1194 2018-08-03 Jan Beulich <jbeulich@suse.com>
1196 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1197 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1198 vpmovzxdq, vpmovzxwd): Remove NoRex64.
1199 * i386-tbl.h: Re-generate.
1201 2018-08-03 Jan Beulich <jbeulich@suse.com>
1203 * i386-gen.c (operand_types): Remove Mem field.
1204 * i386-opc.h (union i386_operand_type): Remove mem field.
1205 * i386-init.h, i386-tbl.h: Re-generate.
1207 2018-08-01 Alan Modra <amodra@gmail.com>
1209 * po/POTFILES.in: Regenerate.
1211 2018-07-31 Nick Clifton <nickc@redhat.com>
1213 * po/sv.po: Updated Swedish translation.
1215 2018-07-31 Jan Beulich <jbeulich@suse.com>
1217 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1218 * i386-init.h, i386-tbl.h: Re-generate.
1220 2018-07-31 Jan Beulich <jbeulich@suse.com>
1222 * i386-opc.h (ZEROING_MASKING) Rename to ...
1223 (DYNAMIC_MASKING): ... this. Adjust comment.
1224 * i386-opc.tbl (MaskingMorZ): Define.
1225 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1226 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1227 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1228 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1229 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1230 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1231 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1232 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1233 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1235 2018-07-31 Jan Beulich <jbeulich@suse.com>
1237 * i386-opc.tbl: Use element rather than vector size for AVX512*
1238 scatter/gather insns.
1239 * i386-tbl.h: Re-generate.
1241 2018-07-31 Jan Beulich <jbeulich@suse.com>
1243 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1244 (cpu_flags): Drop CpuVREX.
1245 * i386-opc.h (CpuVREX): Delete.
1246 (union i386_cpu_flags): Remove cpuvrex.
1247 * i386-init.h, i386-tbl.h: Re-generate.
1249 2018-07-30 Jim Wilson <jimw@sifive.com>
1251 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1253 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1255 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
1257 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1258 * Makefile.in: Regenerated.
1259 * configure.ac: Add C-SKY.
1260 * configure: Regenerated.
1261 * csky-dis.c: New file.
1262 * csky-opc.h: New file.
1263 * disassemble.c (ARCH_csky): Define.
1264 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1265 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1267 2018-07-27 Alan Modra <amodra@gmail.com>
1269 * ppc-opc.c (insert_sprbat): Correct function parameter and
1271 (extract_sprbat): Likewise, variable too.
1273 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
1274 Alan Modra <amodra@gmail.com>
1276 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1277 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1278 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1279 support disjointed BAT.
1280 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
1281 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1282 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1284 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
1285 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1287 * i386-gen.c (adjust_broadcast_modifier): New function.
1288 (process_i386_opcode_modifier): Add an argument for operands.
1289 Adjust the Broadcast value based on operands.
1290 (output_i386_opcode): Pass operand_types to
1291 process_i386_opcode_modifier.
1292 (process_i386_opcodes): Pass NULL as operands to
1293 process_i386_opcode_modifier.
1294 * i386-opc.h (BYTE_BROADCAST): New.
1295 (WORD_BROADCAST): Likewise.
1296 (DWORD_BROADCAST): Likewise.
1297 (QWORD_BROADCAST): Likewise.
1298 (i386_opcode_modifier): Expand broadcast to 3 bits.
1299 * i386-tbl.h: Regenerated.
1301 2018-07-24 Alan Modra <amodra@gmail.com>
1304 * or1k-desc.h: Regenerate.
1306 2018-07-24 Jan Beulich <jbeulich@suse.com>
1308 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1309 vcvtusi2ss, and vcvtusi2sd.
1310 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1311 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1312 * i386-tbl.h: Re-generate.
1314 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1316 * arc-opc.c (extract_w6): Fix extending the sign.
1318 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1320 * arc-tbl.h (vewt): Allow it for ARC EM family.
1322 2018-07-23 Alan Modra <amodra@gmail.com>
1325 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1326 opcode variants for mtspr/mfspr encodings.
1328 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
1329 Maciej W. Rozycki <macro@mips.com>
1331 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1332 loongson3a descriptors.
1333 (parse_mips_ase_option): Handle -M loongson-mmi option.
1334 (print_mips_disassembler_options): Document -M loongson-mmi.
1335 * mips-opc.c (LMMI): New macro.
1336 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1339 2018-07-19 Jan Beulich <jbeulich@suse.com>
1341 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1342 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1343 IgnoreSize and [XYZ]MMword where applicable.
1344 * i386-tbl.h: Re-generate.
1346 2018-07-19 Jan Beulich <jbeulich@suse.com>
1348 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1349 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1350 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1351 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1352 * i386-tbl.h: Re-generate.
1354 2018-07-19 Jan Beulich <jbeulich@suse.com>
1356 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1357 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1358 VPCLMULQDQ templates into their respective AVX512VL counterparts
1359 where possible, using Disp8ShiftVL and CheckRegSize instead of
1360 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1361 * i386-tbl.h: Re-generate.
1363 2018-07-19 Jan Beulich <jbeulich@suse.com>
1365 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1366 AVX512VL counterparts where possible, using Disp8ShiftVL and
1367 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1368 IgnoreSize) as appropriate.
1369 * i386-tbl.h: Re-generate.
1371 2018-07-19 Jan Beulich <jbeulich@suse.com>
1373 * i386-opc.tbl: Fold AVX512BW templates into their respective
1374 AVX512VL counterparts where possible, using Disp8ShiftVL and
1375 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1376 IgnoreSize) as appropriate.
1377 * i386-tbl.h: Re-generate.
1379 2018-07-19 Jan Beulich <jbeulich@suse.com>
1381 * i386-opc.tbl: Fold AVX512CD templates into their respective
1382 AVX512VL counterparts where possible, using Disp8ShiftVL and
1383 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1384 IgnoreSize) as appropriate.
1385 * i386-tbl.h: Re-generate.
1387 2018-07-19 Jan Beulich <jbeulich@suse.com>
1389 * i386-opc.h (DISP8_SHIFT_VL): New.
1390 * i386-opc.tbl (Disp8ShiftVL): Define.
1391 (various): Fold AVX512VL templates into their respective
1392 AVX512F counterparts where possible, using Disp8ShiftVL and
1393 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1394 IgnoreSize) as appropriate.
1395 * i386-tbl.h: Re-generate.
1397 2018-07-19 Jan Beulich <jbeulich@suse.com>
1399 * Makefile.am: Change dependencies and rule for
1400 $(srcdir)/i386-init.h.
1401 * Makefile.in: Re-generate.
1402 * i386-gen.c (process_i386_opcodes): New local variable
1403 "marker". Drop opening of input file. Recognize marker and line
1405 * i386-opc.tbl (OPCODE_I386_H): Define.
1406 (i386-opc.h): Include it.
1409 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1412 * i386-opc.h (Byte): Update comments.
1418 (Xmmword): Likewise.
1419 (Ymmword): Likewise.
1420 (Zmmword): Likewise.
1421 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1423 * i386-tbl.h: Regenerated.
1425 2018-07-12 Sudakshina Das <sudi.das@arm.com>
1427 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1428 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1429 * aarch64-asm-2.c: Regenerate.
1430 * aarch64-dis-2.c: Regenerate.
1431 * aarch64-opc-2.c: Regenerate.
1433 2018-07-12 Tamar Christina <tamar.christina@arm.com>
1436 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1437 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1438 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1439 sqdmulh, sqrdmulh): Use Em16.
1441 2018-07-11 Sudakshina Das <sudi.das@arm.com>
1443 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1444 csdb together with them.
1445 (thumb32_opcodes): Likewise.
1447 2018-07-11 Jan Beulich <jbeulich@suse.com>
1449 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1450 requiring 32-bit registers as operands 2 and 3. Improve
1452 (mwait, mwaitx): Fold templates. Improve comments.
1453 OPERAND_TYPE_INOUTPORTREG.
1454 * i386-tbl.h: Re-generate.
1456 2018-07-11 Jan Beulich <jbeulich@suse.com>
1458 * i386-gen.c (operand_type_init): Remove
1459 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1460 OPERAND_TYPE_INOUTPORTREG.
1461 * i386-init.h: Re-generate.
1463 2018-07-11 Jan Beulich <jbeulich@suse.com>
1465 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1466 (wrssq, wrussq): Add Qword.
1467 * i386-tbl.h: Re-generate.
1469 2018-07-11 Jan Beulich <jbeulich@suse.com>
1471 * i386-opc.h: Rename OTMax to OTNum.
1472 (OTNumOfUints): Adjust calculation.
1473 (OTUnused): Directly alias to OTNum.
1475 2018-07-09 Maciej W. Rozycki <macro@mips.com>
1477 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1479 (lea_reg_xys): Likewise.
1480 (print_insn_loop_primitive): Rename `reg' local variable to
1483 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1486 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1488 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1491 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1492 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1494 2018-07-02 Maciej W. Rozycki <macro@mips.com>
1497 * mips-dis.c (mips_option_arg_t): New enumeration.
1498 (mips_options): New variable.
1499 (disassembler_options_mips): New function.
1500 (print_mips_disassembler_options): Reimplement in terms of
1501 `disassembler_options_mips'.
1502 * arm-dis.c (disassembler_options_arm): Adapt to using the
1503 `disasm_options_and_args_t' structure.
1504 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1505 * s390-dis.c (disassembler_options_s390): Likewise.
1507 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1509 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1511 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1512 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1513 * testsuite/ld-arm/tls-longplt.d: Likewise.
1515 2018-06-29 Tamar Christina <tamar.christina@arm.com>
1518 * aarch64-asm-2.c: Regenerate.
1519 * aarch64-dis-2.c: Likewise.
1520 * aarch64-opc-2.c: Likewise.
1521 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1522 * aarch64-opc.c (operand_general_constraint_met_p,
1523 aarch64_print_operand): Likewise.
1524 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1525 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1527 (AARCH64_OPERANDS): Add Em2.
1529 2018-06-26 Nick Clifton <nickc@redhat.com>
1531 * po/uk.po: Updated Ukranian translation.
1532 * po/de.po: Updated German translation.
1533 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1535 2018-06-26 Nick Clifton <nickc@redhat.com>
1537 * nfp-dis.c: Fix spelling mistake.
1539 2018-06-24 Nick Clifton <nickc@redhat.com>
1541 * configure: Regenerate.
1542 * po/opcodes.pot: Regenerate.
1544 2018-06-24 Nick Clifton <nickc@redhat.com>
1546 2.31 branch created.
1548 2018-06-19 Tamar Christina <tamar.christina@arm.com>
1550 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1551 * aarch64-asm-2.c: Regenerate.
1552 * aarch64-dis-2.c: Likewise.
1554 2018-06-21 Maciej W. Rozycki <macro@mips.com>
1556 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1557 `-M ginv' option description.
1559 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1562 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1565 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1567 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1568 * configure.ac: Remove AC_PREREQ.
1569 * Makefile.in: Re-generate.
1570 * aclocal.m4: Re-generate.
1571 * configure: Re-generate.
1573 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1575 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1576 mips64r6 descriptors.
1577 (parse_mips_ase_option): Handle -Mginv option.
1578 (print_mips_disassembler_options): Document -Mginv.
1579 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1581 (mips_opcodes): Define ginvi and ginvt.
1583 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1584 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1586 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1587 * mips-opc.c (CRC, CRC64): New macros.
1588 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1589 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1592 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1595 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1596 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1598 2018-06-06 Alan Modra <amodra@gmail.com>
1600 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1601 setjmp. Move init for some other vars later too.
1603 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1605 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1606 (dis_private): Add new fields for property section tracking.
1607 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1608 (xtensa_instruction_fits): New functions.
1609 (fetch_data): Bump minimal fetch size to 4.
1610 (print_insn_xtensa): Make struct dis_private static.
1611 Load and prepare property table on section change.
1612 Don't disassemble literals. Don't disassemble instructions that
1613 cross property table boundaries.
1615 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1617 * configure: Regenerated.
1619 2018-06-01 Jan Beulich <jbeulich@suse.com>
1621 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1622 * i386-tbl.h: Re-generate.
1624 2018-06-01 Jan Beulich <jbeulich@suse.com>
1626 * i386-opc.tbl (sldt, str): Add NoRex64.
1627 * i386-tbl.h: Re-generate.
1629 2018-06-01 Jan Beulich <jbeulich@suse.com>
1631 * i386-opc.tbl (invpcid): Add Oword.
1632 * i386-tbl.h: Re-generate.
1634 2018-06-01 Alan Modra <amodra@gmail.com>
1636 * sysdep.h (_bfd_error_handler): Don't declare.
1637 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1638 * rl78-decode.opc: Likewise.
1639 * msp430-decode.c: Regenerate.
1640 * rl78-decode.c: Regenerate.
1642 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1644 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1645 * i386-init.h : Regenerated.
1647 2018-05-25 Alan Modra <amodra@gmail.com>
1649 * Makefile.in: Regenerate.
1650 * po/POTFILES.in: Regenerate.
1652 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1654 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1655 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1656 (insert_bab, extract_bab, insert_btab, extract_btab,
1657 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1658 (BAT, BBA VBA RBS XB6S): Delete macros.
1659 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1660 (BB, BD, RBX, XC6): Update for new macros.
1661 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1662 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1663 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1664 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1666 2018-05-18 John Darrington <john@darrington.wattle.id.au>
1668 * Makefile.am: Add support for s12z architecture.
1669 * configure.ac: Likewise.
1670 * disassemble.c: Likewise.
1671 * disassemble.h: Likewise.
1672 * Makefile.in: Regenerate.
1673 * configure: Regenerate.
1674 * s12z-dis.c: New file.
1677 2018-05-18 Alan Modra <amodra@gmail.com>
1679 * nfp-dis.c: Don't #include libbfd.h.
1680 (init_nfp3200_priv): Use bfd_get_section_contents.
1681 (nit_nfp6000_mecsr_sec): Likewise.
1683 2018-05-17 Nick Clifton <nickc@redhat.com>
1685 * po/zh_CN.po: Updated simplified Chinese translation.
1687 2018-05-16 Tamar Christina <tamar.christina@arm.com>
1690 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1691 * aarch64-dis-2.c: Regenerate.
1693 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1696 * aarch64-asm.c (opintl.h): Include.
1697 (aarch64_ins_sysreg): Enforce read/write constraints.
1698 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1699 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1700 (F_REG_READ, F_REG_WRITE): New.
1701 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1702 AARCH64_OPND_SYSREG.
1703 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1704 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1705 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1706 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1707 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1708 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1709 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1710 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1711 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1712 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1713 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1714 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1715 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1716 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1717 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1718 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1719 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1721 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1724 * aarch64-dis.c (no_notes: New.
1725 (parse_aarch64_dis_option): Support notes.
1726 (aarch64_decode_insn, print_operands): Likewise.
1727 (print_aarch64_disassembler_options): Document notes.
1728 * aarch64-opc.c (aarch64_print_operand): Support notes.
1730 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1733 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1734 and take error struct.
1735 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1736 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1737 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1738 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1739 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1740 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1741 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1742 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1743 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1744 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1745 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1746 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1747 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1748 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1749 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1750 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1751 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1752 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1753 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1754 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1755 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1756 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1757 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1758 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1759 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1760 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1761 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1762 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1763 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1764 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1765 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1766 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1767 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1768 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1769 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1770 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1771 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1772 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1773 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1774 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1775 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1776 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1777 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1778 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1779 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1780 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1781 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1782 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1783 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1784 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1785 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1786 (determine_disassembling_preference, aarch64_decode_insn,
1787 print_insn_aarch64_word, print_insn_data): Take errors struct.
1788 (print_insn_aarch64): Use errors.
1789 * aarch64-asm-2.c: Regenerate.
1790 * aarch64-dis-2.c: Regenerate.
1791 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1792 boolean in aarch64_insert_operan.
1793 (print_operand_extractor): Likewise.
1794 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1796 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
1798 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1800 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1802 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1804 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1806 * cr16-opc.c (cr16_instruction): Comment typo fix.
1807 * hppa-dis.c (print_insn_hppa): Likewise.
1809 2018-05-08 Jim Wilson <jimw@sifive.com>
1811 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1812 (match_c_slli64, match_srxi_as_c_srxi): New.
1813 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1814 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1815 <c.slli, c.srli, c.srai>: Use match_s_slli.
1816 <c.slli64, c.srli64, c.srai64>: New.
1818 2018-05-08 Alan Modra <amodra@gmail.com>
1820 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1821 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1822 partition opcode space for index lookup.
1824 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1826 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1827 <insn_length>: ...with this. Update usage.
1828 Remove duplicate call to *info->memory_error_func.
1830 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1831 H.J. Lu <hongjiu.lu@intel.com>
1833 * i386-dis.c (Gva): New.
1834 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1835 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1836 (prefix_table): New instructions (see prefix above).
1837 (mod_table): New instructions (see prefix above).
1838 (OP_G): Handle va_mode.
1839 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1840 CPU_MOVDIR64B_FLAGS.
1841 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1842 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1843 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1844 * i386-opc.tbl: Add movidir{i,64b}.
1845 * i386-init.h: Regenerated.
1846 * i386-tbl.h: Likewise.
1848 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1850 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1852 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1853 (AddrPrefixOpReg): This.
1854 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1855 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1857 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1859 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1860 (vle_num_opcodes): Likewise.
1861 (spe2_num_opcodes): Likewise.
1862 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1863 initialization loop.
1864 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1865 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1868 2018-05-01 Tamar Christina <tamar.christina@arm.com>
1870 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1872 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
1874 Makefile.am: Added nfp-dis.c.
1875 configure.ac: Added bfd_nfp_arch.
1876 disassemble.h: Added print_insn_nfp prototype.
1877 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1878 nfp-dis.c: New, for NFP support.
1879 po/POTFILES.in: Added nfp-dis.c to the list.
1880 Makefile.in: Regenerate.
1881 configure: Regenerate.
1883 2018-04-26 Jan Beulich <jbeulich@suse.com>
1885 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1886 templates into their base ones.
1887 * i386-tlb.h: Re-generate.
1889 2018-04-26 Jan Beulich <jbeulich@suse.com>
1891 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1892 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1893 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1894 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1895 * i386-init.h: Re-generate.
1897 2018-04-26 Jan Beulich <jbeulich@suse.com>
1899 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1900 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1901 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1902 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1904 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1906 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1908 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1909 cpuregzmm, and cpuregmask.
1910 * i386-init.h: Re-generate.
1911 * i386-tbl.h: Re-generate.
1913 2018-04-26 Jan Beulich <jbeulich@suse.com>
1915 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1916 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1917 * i386-init.h: Re-generate.
1919 2018-04-26 Jan Beulich <jbeulich@suse.com>
1921 * i386-gen.c (VexImmExt): Delete.
1922 * i386-opc.h (VexImmExt, veximmext): Delete.
1923 * i386-opc.tbl: Drop all VexImmExt uses.
1924 * i386-tlb.h: Re-generate.
1926 2018-04-25 Jan Beulich <jbeulich@suse.com>
1928 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1929 register-only forms.
1930 * i386-tlb.h: Re-generate.
1932 2018-04-25 Tamar Christina <tamar.christina@arm.com>
1934 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1936 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1938 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1940 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1941 (cpu_flags): Add CpuCLDEMOTE.
1942 * i386-init.h: Regenerate.
1943 * i386-opc.h (enum): Add CpuCLDEMOTE,
1944 (i386_cpu_flags): Add cpucldemote.
1945 * i386-opc.tbl: Add cldemote.
1946 * i386-tbl.h: Regenerate.
1948 2018-04-16 Alan Modra <amodra@gmail.com>
1950 * Makefile.am: Remove sh5 and sh64 support.
1951 * configure.ac: Likewise.
1952 * disassemble.c: Likewise.
1953 * disassemble.h: Likewise.
1954 * sh-dis.c: Likewise.
1955 * sh64-dis.c: Delete.
1956 * sh64-opc.c: Delete.
1957 * sh64-opc.h: Delete.
1958 * Makefile.in: Regenerate.
1959 * configure: Regenerate.
1960 * po/POTFILES.in: Regenerate.
1962 2018-04-16 Alan Modra <amodra@gmail.com>
1964 * Makefile.am: Remove w65 support.
1965 * configure.ac: Likewise.
1966 * disassemble.c: Likewise.
1967 * disassemble.h: Likewise.
1968 * w65-dis.c: Delete.
1969 * w65-opc.h: Delete.
1970 * Makefile.in: Regenerate.
1971 * configure: Regenerate.
1972 * po/POTFILES.in: Regenerate.
1974 2018-04-16 Alan Modra <amodra@gmail.com>
1976 * configure.ac: Remove we32k support.
1977 * configure: Regenerate.
1979 2018-04-16 Alan Modra <amodra@gmail.com>
1981 * Makefile.am: Remove m88k support.
1982 * configure.ac: Likewise.
1983 * disassemble.c: Likewise.
1984 * disassemble.h: Likewise.
1985 * m88k-dis.c: Delete.
1986 * Makefile.in: Regenerate.
1987 * configure: Regenerate.
1988 * po/POTFILES.in: Regenerate.
1990 2018-04-16 Alan Modra <amodra@gmail.com>
1992 * Makefile.am: Remove i370 support.
1993 * configure.ac: Likewise.
1994 * disassemble.c: Likewise.
1995 * disassemble.h: Likewise.
1996 * i370-dis.c: Delete.
1997 * i370-opc.c: Delete.
1998 * Makefile.in: Regenerate.
1999 * configure: Regenerate.
2000 * po/POTFILES.in: Regenerate.
2002 2018-04-16 Alan Modra <amodra@gmail.com>
2004 * Makefile.am: Remove h8500 support.
2005 * configure.ac: Likewise.
2006 * disassemble.c: Likewise.
2007 * disassemble.h: Likewise.
2008 * h8500-dis.c: Delete.
2009 * h8500-opc.h: Delete.
2010 * Makefile.in: Regenerate.
2011 * configure: Regenerate.
2012 * po/POTFILES.in: Regenerate.
2014 2018-04-16 Alan Modra <amodra@gmail.com>
2016 * configure.ac: Remove tahoe support.
2017 * configure: Regenerate.
2019 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
2021 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
2023 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
2025 * i386-tbl.h: Regenerated.
2027 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2029 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
2030 PREFIX_MOD_1_0FAE_REG_6.
2032 (OP_E_register): Use va_mode.
2033 * i386-dis-evex.h (prefix_table):
2034 New instructions (see prefixes above).
2035 * i386-gen.c (cpu_flag_init): Add WAITPKG.
2036 (cpu_flags): Likewise.
2037 * i386-opc.h (enum): Likewise.
2038 (i386_cpu_flags): Likewise.
2039 * i386-opc.tbl: Add umonitor, umwait, tpause.
2040 * i386-init.h: Regenerate.
2041 * i386-tbl.h: Likewise.
2043 2018-04-11 Alan Modra <amodra@gmail.com>
2045 * opcodes/i860-dis.c: Delete.
2046 * opcodes/i960-dis.c: Delete.
2047 * Makefile.am: Remove i860 and i960 support.
2048 * configure.ac: Likewise.
2049 * disassemble.c: Likewise.
2050 * disassemble.h: Likewise.
2051 * Makefile.in: Regenerate.
2052 * configure: Regenerate.
2053 * po/POTFILES.in: Regenerate.
2055 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
2058 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
2060 (print_insn): Clear vex instead of vex.evex.
2062 2018-04-04 Nick Clifton <nickc@redhat.com>
2064 * po/es.po: Updated Spanish translation.
2066 2018-03-28 Jan Beulich <jbeulich@suse.com>
2068 * i386-gen.c (opcode_modifiers): Delete VecESize.
2069 * i386-opc.h (VecESize): Delete.
2070 (struct i386_opcode_modifier): Delete vecesize.
2071 * i386-opc.tbl: Drop VecESize.
2072 * i386-tlb.h: Re-generate.
2074 2018-03-28 Jan Beulich <jbeulich@suse.com>
2076 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
2077 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
2078 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
2079 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
2080 * i386-tlb.h: Re-generate.
2082 2018-03-28 Jan Beulich <jbeulich@suse.com>
2084 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
2086 * i386-tlb.h: Re-generate.
2088 2018-03-28 Jan Beulich <jbeulich@suse.com>
2090 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
2091 (vex_len_table): Drop Y for vcvt*2si.
2092 (putop): Replace plain 'Y' handling by abort().
2094 2018-03-28 Nick Clifton <nickc@redhat.com>
2097 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
2098 instructions with only a base address register.
2099 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
2100 handle AARHC64_OPND_SVE_ADDR_R.
2101 (aarch64_print_operand): Likewise.
2102 * aarch64-asm-2.c: Regenerate.
2103 * aarch64_dis-2.c: Regenerate.
2104 * aarch64-opc-2.c: Regenerate.
2106 2018-03-22 Jan Beulich <jbeulich@suse.com>
2108 * i386-opc.tbl: Drop VecESize from register only insn forms and
2109 memory forms not allowing broadcast.
2110 * i386-tlb.h: Re-generate.
2112 2018-03-22 Jan Beulich <jbeulich@suse.com>
2114 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
2115 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
2116 sha256*): Drop Disp<N>.
2118 2018-03-22 Jan Beulich <jbeulich@suse.com>
2120 * i386-dis.c (EbndS, bnd_swap_mode): New.
2121 (prefix_table): Use EbndS.
2122 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
2123 * i386-opc.tbl (bndmov): Move misplaced Load.
2124 * i386-tlb.h: Re-generate.
2126 2018-03-22 Jan Beulich <jbeulich@suse.com>
2128 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
2129 templates allowing memory operands and folded ones for register
2131 * i386-tlb.h: Re-generate.
2133 2018-03-22 Jan Beulich <jbeulich@suse.com>
2135 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
2136 256-bit templates. Drop redundant leftover Disp<N>.
2137 * i386-tlb.h: Re-generate.
2139 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
2141 * riscv-opc.c (riscv_insn_types): New.
2143 2018-03-13 Nick Clifton <nickc@redhat.com>
2145 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2147 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2149 * i386-opc.tbl: Add Optimize to clr.
2150 * i386-tbl.h: Regenerated.
2152 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2154 * i386-gen.c (opcode_modifiers): Remove OldGcc.
2155 * i386-opc.h (OldGcc): Removed.
2156 (i386_opcode_modifier): Remove oldgcc.
2157 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
2158 instructions for old (<= 2.8.1) versions of gcc.
2159 * i386-tbl.h: Regenerated.
2161 2018-03-08 Jan Beulich <jbeulich@suse.com>
2163 * i386-opc.h (EVEXDYN): New.
2164 * i386-opc.tbl: Fold various AVX512VL templates.
2165 * i386-tlb.h: Re-generate.
2167 2018-03-08 Jan Beulich <jbeulich@suse.com>
2169 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2170 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2171 vpexpandd, vpexpandq): Fold AFX512VF templates.
2172 * i386-tlb.h: Re-generate.
2174 2018-03-08 Jan Beulich <jbeulich@suse.com>
2176 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2177 Fold 128- and 256-bit VEX-encoded templates.
2178 * i386-tlb.h: Re-generate.
2180 2018-03-08 Jan Beulich <jbeulich@suse.com>
2182 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2183 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2184 vpexpandd, vpexpandq): Fold AVX512F templates.
2185 * i386-tlb.h: Re-generate.
2187 2018-03-08 Jan Beulich <jbeulich@suse.com>
2189 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2190 64-bit templates. Drop Disp<N>.
2191 * i386-tlb.h: Re-generate.
2193 2018-03-08 Jan Beulich <jbeulich@suse.com>
2195 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2196 and 256-bit templates.
2197 * i386-tlb.h: Re-generate.
2199 2018-03-08 Jan Beulich <jbeulich@suse.com>
2201 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2202 * i386-tlb.h: Re-generate.
2204 2018-03-08 Jan Beulich <jbeulich@suse.com>
2206 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2208 * i386-tlb.h: Re-generate.
2210 2018-03-08 Jan Beulich <jbeulich@suse.com>
2212 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2213 * i386-tlb.h: Re-generate.
2215 2018-03-08 Jan Beulich <jbeulich@suse.com>
2217 * i386-gen.c (opcode_modifiers): Delete FloatD.
2218 * i386-opc.h (FloatD): Delete.
2219 (struct i386_opcode_modifier): Delete floatd.
2220 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2222 * i386-tlb.h: Re-generate.
2224 2018-03-08 Jan Beulich <jbeulich@suse.com>
2226 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2228 2018-03-08 Jan Beulich <jbeulich@suse.com>
2230 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2231 * i386-tlb.h: Re-generate.
2233 2018-03-08 Jan Beulich <jbeulich@suse.com>
2235 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2237 * i386-tlb.h: Re-generate.
2239 2018-03-07 Alan Modra <amodra@gmail.com>
2241 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2243 * disassemble.h (print_insn_rs6000): Delete.
2244 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2245 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2246 (print_insn_rs6000): Delete.
2248 2018-03-03 Alan Modra <amodra@gmail.com>
2250 * sysdep.h (opcodes_error_handler): Define.
2251 (_bfd_error_handler): Declare.
2252 * Makefile.am: Remove stray #.
2253 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
2255 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2256 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2257 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2258 opcodes_error_handler to print errors. Standardize error messages.
2259 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2260 and include opintl.h.
2261 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2262 * i386-gen.c: Standardize error messages.
2263 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2264 * Makefile.in: Regenerate.
2265 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2266 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2267 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2268 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2269 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2270 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2271 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2272 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2273 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2274 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2275 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2276 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2277 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2279 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
2281 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2282 vpsub[bwdq] instructions.
2283 * i386-tbl.h: Regenerated.
2285 2018-03-01 Alan Modra <amodra@gmail.com>
2287 * configure.ac (ALL_LINGUAS): Sort.
2288 * configure: Regenerate.
2290 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
2292 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2293 macro by assignements.
2295 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
2298 * i386-gen.c (opcode_modifiers): Add Optimize.
2299 * i386-opc.h (Optimize): New enum.
2300 (i386_opcode_modifier): Add optimize.
2301 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2302 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2303 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2304 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2305 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2307 * i386-tbl.h: Regenerated.
2309 2018-02-26 Alan Modra <amodra@gmail.com>
2311 * crx-dis.c (getregliststring): Allocate a large enough buffer
2312 to silence false positive gcc8 warning.
2314 2018-02-22 Shea Levy <shea@shealevy.com>
2316 * disassemble.c (ARCH_riscv): Define if ARCH_all.
2318 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
2320 * i386-opc.tbl: Add {rex},
2321 * i386-tbl.h: Regenerated.
2323 2018-02-20 Maciej W. Rozycki <macro@mips.com>
2325 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2326 (mips16_opcodes): Replace `M' with `m' for "restore".
2328 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
2330 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2332 2018-02-13 Maciej W. Rozycki <macro@mips.com>
2334 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2335 variable to `function_index'.
2337 2018-02-13 Nick Clifton <nickc@redhat.com>
2340 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2341 about truncation of printing.
2343 2018-02-12 Henry Wong <henry@stuffedcow.net>
2345 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2347 2018-02-05 Nick Clifton <nickc@redhat.com>
2349 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2351 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2353 * i386-dis.c (enum): Add pconfig.
2354 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2355 (cpu_flags): Add CpuPCONFIG.
2356 * i386-opc.h (enum): Add CpuPCONFIG.
2357 (i386_cpu_flags): Add cpupconfig.
2358 * i386-opc.tbl: Add PCONFIG instruction.
2359 * i386-init.h: Regenerate.
2360 * i386-tbl.h: Likewise.
2362 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2364 * i386-dis.c (enum): Add PREFIX_0F09.
2365 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2366 (cpu_flags): Add CpuWBNOINVD.
2367 * i386-opc.h (enum): Add CpuWBNOINVD.
2368 (i386_cpu_flags): Add cpuwbnoinvd.
2369 * i386-opc.tbl: Add WBNOINVD instruction.
2370 * i386-init.h: Regenerate.
2371 * i386-tbl.h: Likewise.
2373 2018-01-17 Jim Wilson <jimw@sifive.com>
2375 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2377 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2379 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2380 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2381 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2382 (cpu_flags): Add CpuIBT, CpuSHSTK.
2383 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2384 (i386_cpu_flags): Add cpuibt, cpushstk.
2385 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2386 * i386-init.h: Regenerate.
2387 * i386-tbl.h: Likewise.
2389 2018-01-16 Nick Clifton <nickc@redhat.com>
2391 * po/pt_BR.po: Updated Brazilian Portugese translation.
2392 * po/de.po: Updated German translation.
2394 2018-01-15 Jim Wilson <jimw@sifive.com>
2396 * riscv-opc.c (match_c_nop): New.
2397 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2399 2018-01-15 Nick Clifton <nickc@redhat.com>
2401 * po/uk.po: Updated Ukranian translation.
2403 2018-01-13 Nick Clifton <nickc@redhat.com>
2405 * po/opcodes.pot: Regenerated.
2407 2018-01-13 Nick Clifton <nickc@redhat.com>
2409 * configure: Regenerate.
2411 2018-01-13 Nick Clifton <nickc@redhat.com>
2413 2.30 branch created.
2415 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2417 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2418 * i386-tbl.h: Regenerate.
2420 2018-01-10 Jan Beulich <jbeulich@suse.com>
2422 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2423 * i386-tbl.h: Re-generate.
2425 2018-01-10 Jan Beulich <jbeulich@suse.com>
2427 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2428 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2429 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2430 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2431 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2432 Disp8MemShift of AVX512VL forms.
2433 * i386-tbl.h: Re-generate.
2435 2018-01-09 Jim Wilson <jimw@sifive.com>
2437 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2438 then the hi_addr value is zero.
2440 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2442 * arm-dis.c (arm_opcodes): Add csdb.
2443 (thumb32_opcodes): Add csdb.
2445 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2447 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2448 * aarch64-asm-2.c: Regenerate.
2449 * aarch64-dis-2.c: Regenerate.
2450 * aarch64-opc-2.c: Regenerate.
2452 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2455 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2456 Remove AVX512 vmovd with 64-bit operands.
2457 * i386-tbl.h: Regenerated.
2459 2018-01-05 Jim Wilson <jimw@sifive.com>
2461 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2464 2018-01-03 Alan Modra <amodra@gmail.com>
2466 Update year range in copyright notice of all files.
2468 2018-01-02 Jan Beulich <jbeulich@suse.com>
2470 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2471 and OPERAND_TYPE_REGZMM entries.
2473 For older changes see ChangeLog-2017
2475 Copyright (C) 2018 Free Software Foundation, Inc.
2477 Copying and distribution of this file, with or without modification,
2478 are permitted in any medium without royalty provided the copyright
2479 notice and this notice are preserved.
2485 version-control: never