opcodes/ChangeLog

   1 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
   2
   3         * disassemble.c Include "safe-ctype.h".
   4         (disassemble_init_for_target): Handle s390 init.
   5         (remove_whitespace_and_extra_commas): New function.
   6         (disassembler_options_cmp): Likewise.
   7         * arm-dis.c: Include "libiberty.h".
   8         (NUM_ELEM): Delete.
   9         (regnames): Use long disassembler style names.
  10         Add force-thumb and no-force-thumb options.
  11         (NUM_ARM_REGNAMES): Rename from this...
  12         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
  13         (get_arm_regname_num_options): Delete.
  14         (set_arm_regname_option): Likewise.
  15         (get_arm_regnames): Likewise.
  16         (parse_disassembler_options): Likewise.
  17         (parse_arm_disassembler_option): Rename from this...
  18         (parse_arm_disassembler_options): ...to this.  Make static.
  19         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
  20         (print_insn): Use parse_arm_disassembler_options.
  21         (disassembler_options_arm): New function.
  22         (print_arm_disassembler_options): Handle updated regnames.
  23         * ppc-dis.c: Include "libiberty.h".
  24         (ppc_opts): Add "32" and "64" entries.
  25         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
  26         (powerpc_init_dialect): Add break to switch statement.
  27         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
  28         (disassembler_options_powerpc): New function.
  29         (print_ppc_disassembler_options): Use ARRAY_SIZE.
  30         Remove printing of "32" and "64".
  31         * s390-dis.c: Include "libiberty.h".
  32         (init_flag): Remove unneeded variable.
  33         (struct s390_options_t): New structure type.
  34         (options): New structure.
  35         (init_disasm): Rename from this...
  36         (disassemble_init_s390): ...to this.  Add initializations for
  37         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
  38         (print_insn_s390): Delete call to init_disasm.
  39         (disassembler_options_s390): New function.
  40         (print_s390_disassembler_options): Print using information from
  41         struct 'options'.
  42         * po/opcodes.pot: Regenerate.
  43
  44 2017-02-28  Jan Beulich  <jbeulich@suse.com>
  45
  46         * i386-dis.c (PCMPESTR_Fixup): New.
  47         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
  48         (prefix_table): Use PCMPESTR_Fixup.
  49         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
  50         PCMPESTR_Fixup.
  51         (vex_w_table): Delete VPCMPESTR{I,M} entries.
  52         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
  53         Split 64-bit and non-64-bit variants.
  54         * opcodes/i386-tbl.h: Re-generate.
  55
  56 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
  57
  58         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
  59         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
  60         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
  61         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
  62         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
  63         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
  64         (OP_SVE_V_HSD): New macros.
  65         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
  66         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
  67         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
  68         (aarch64_opcode_table): Add new SVE instructions.
  69         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
  70         for rotation operands.  Add new SVE operands.
  71         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
  72         (ins_sve_quad_index): Likewise.
  73         (ins_imm_rotate): Split into...
  74         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
  75         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
  76         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
  77         functions.
  78         (aarch64_ins_sve_addr_ri_s4): New function.
  79         (aarch64_ins_sve_quad_index): Likewise.
  80         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
  81         * aarch64-asm-2.c: Regenerate.
  82         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
  83         (ext_sve_quad_index): Likewise.
  84         (ext_imm_rotate): Split into...
  85         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
  86         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
  87         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
  88         functions.
  89         (aarch64_ext_sve_addr_ri_s4): New function.
  90         (aarch64_ext_sve_quad_index): Likewise.
  91         (aarch64_ext_sve_index): Allow quad indices.
  92         (do_misc_decoding): Likewise.
  93         * aarch64-dis-2.c: Regenerate.
  94         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
  95         aarch64_field_kinds.
  96         (OPD_F_OD_MASK): Widen by one bit.
  97         (OPD_F_NO_ZR): Bump accordingly.
  98         (get_operand_field_width): New function.
  99         * aarch64-opc.c (fields): Add new SVE fields.
 100         (operand_general_constraint_met_p): Handle new SVE operands.
 101         (aarch64_print_operand): Likewise.
 102         * aarch64-opc-2.c: Regenerate.
 103
 104 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 105
 106         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 107         (aarch64_feature_compnum): ...this.
 108         (SIMD_V8_3): Replace with...
 109         (COMPNUM): ...this.
 110         (CNUM_INSN): New macro.
 111         (aarch64_opcode_table): Use it for the complex number instructions.
 112
 113 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 114
 115         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 116
 117 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 118
 119         Add support for associating SPARC ASIs with an architecture level.
 120         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 121         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 122         decoding of SPARC ASIs.
 123
 124 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 125
 126         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 127         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 128
 129 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 130
 131         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 132         1 (instead of to itself). Correct typo.
 133
 134 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 135
 136         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 137         pseudoinstructions.
 138
 139 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 140
 141         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 142         (aarch64_sys_reg_supported_p): Handle them.
 143
 144 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 145
 146         * arc-opc.c (UIMM6_20R): Define.
 147         (SIMM12_20): Use above.
 148         (SIMM12_20R): Define.
 149         (SIMM3_5_S): Use above.
 150         (UIMM7_A32_11R_S): Define.
 151         (UIMM7_9_S): Use above.
 152         (UIMM3_13R_S): Define.
 153         (SIMM11_A32_7_S): Use above.
 154         (SIMM9_8R): Define.
 155         (UIMM10_A32_8_S): Use above.
 156         (UIMM8_8R_S): Define.
 157         (W6): Use above.
 158         (arc_relax_opcodes): Use all above defines.
 159
 160 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 161
 162         * arc-regs.h: Distinguish some of the registers different on
 163         ARC700 and HS38 cpus.
 164
 165 2017-02-14  Alan Modra  <amodra@gmail.com>
 166
 167         PR 21118
 168         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 169         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 170
 171 2017-02-11  Stafford Horne  <shorne@gmail.com>
 172             Alan Modra  <amodra@gmail.com>
 173
 174         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 175         Use insn_bytes_value and insn_int_value directly instead.  Don't
 176         free allocated memory until function exit.
 177
 178 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 179
 180         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 181
 182 2017-02-03  Nick Clifton  <nickc@redhat.com>
 183
 184         PR 21096
 185         * aarch64-opc.c (print_register_list): Ensure that the register
 186         list index will fir into the tb buffer.
 187         (print_register_offset_address): Likewise.
 188         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 189
 190 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 191
 192         PR 21056
 193         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 194         instructions when the previous fetch packet ends with a 32-bit
 195         instruction.
 196
 197 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 198
 199         * pru-opc.c: Remove vague reference to a future GDB port.
 200
 201 2017-01-20  Nick Clifton  <nickc@redhat.com>
 202
 203         * po/ga.po: Updated Irish translation.
 204
 205 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 206
 207         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 208
 209 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 210
 211         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 212         if FETCH_DATA returns 0.
 213         (m68k_scan_mask): Likewise.
 214         (print_insn_m68k): Update code to handle -1 return value.
 215
 216 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 217
 218         * m68k-dis.c (enum print_insn_arg_error): New.
 219         (NEXTBYTE): Replace -3 with
 220         PRINT_INSN_ARG_MEMORY_ERROR.
 221         (NEXTULONG): Likewise.
 222         (NEXTSINGLE): Likewise.
 223         (NEXTDOUBLE): Likewise.
 224         (NEXTDOUBLE): Likewise.
 225         (NEXTPACKED): Likewise.
 226         (FETCH_ARG): Likewise.
 227         (FETCH_DATA): Update comments.
 228         (print_insn_arg): Update comments. Replace magic numbers with
 229         enum.
 230         (match_insn_m68k): Likewise.
 231
 232 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 233
 234         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 235         * i386-dis-evex.h (evex_table): Updated.
 236         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 237         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 238         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 239         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 240         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 241         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 242         * i386-init.h: Regenerate.
 243         * i386-tbl.h: Ditto.
 244
 245 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 246
 247         * msp430-dis.c (msp430_singleoperand): Return -1 if
 248         msp430dis_opcode_signed returns false.
 249         (msp430_doubleoperand): Likewise.
 250         (msp430_branchinstr): Return -1 if
 251         msp430dis_opcode_unsigned returns false.
 252         (msp430x_calla_instr): Likewise.
 253         (print_insn_msp430): Likewise.
 254
 255 2017-01-05  Nick Clifton  <nickc@redhat.com>
 256
 257         PR 20946
 258         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 259         could not be matched.
 260         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 261         NULL.
 262
 263 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 264
 265         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 266         (aarch64_opcode_table): Use RCPC_INSN.
 267
 268 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 269
 270         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 271         extension.
 272         * riscv-opcodes/all-opcodes: Likewise.
 273
 274 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 275
 276         * riscv-dis.c (print_insn_args): Add fall through comment.
 277
 278 2017-01-03  Nick Clifton  <nickc@redhat.com>
 279
 280         * po/sr.po: New Serbian translation.
 281         * configure.ac (ALL_LINGUAS): Add sr.
 282         * configure: Regenerate.
 283
 284 2017-01-02  Alan Modra  <amodra@gmail.com>
 285
 286         * epiphany-desc.h: Regenerate.
 287         * epiphany-opc.h: Regenerate.
 288         * fr30-desc.h: Regenerate.
 289         * fr30-opc.h: Regenerate.
 290         * frv-desc.h: Regenerate.
 291         * frv-opc.h: Regenerate.
 292         * ip2k-desc.h: Regenerate.
 293         * ip2k-opc.h: Regenerate.
 294         * iq2000-desc.h: Regenerate.
 295         * iq2000-opc.h: Regenerate.
 296         * lm32-desc.h: Regenerate.
 297         * lm32-opc.h: Regenerate.
 298         * m32c-desc.h: Regenerate.
 299         * m32c-opc.h: Regenerate.
 300         * m32r-desc.h: Regenerate.
 301         * m32r-opc.h: Regenerate.
 302         * mep-desc.h: Regenerate.
 303         * mep-opc.h: Regenerate.
 304         * mt-desc.h: Regenerate.
 305         * mt-opc.h: Regenerate.
 306         * or1k-desc.h: Regenerate.
 307         * or1k-opc.h: Regenerate.
 308         * xc16x-desc.h: Regenerate.
 309         * xc16x-opc.h: Regenerate.
 310         * xstormy16-desc.h: Regenerate.
 311         * xstormy16-opc.h: Regenerate.
 312
 313 2017-01-02  Alan Modra  <amodra@gmail.com>
 314
 315         Update year range in copyright notice of all files.
 316
 317 For older changes see ChangeLog-2016
 318 \f
 319 Copyright (C) 2017 Free Software Foundation, Inc.
 320
 321 Copying and distribution of this file, with or without modification,
 322 are permitted in any medium without royalty provided the copyright
 323 notice and this notice are preserved.
 324
 325 Local Variables:
 326 mode: change-log
 327 left-margin: 8
 328 fill-column: 74
 329 version-control: never
 330 End: