opcodes/ChangeLog

   1 2020-03-06  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
   4         template.
   5         * i386-tbl.h: Re-generate.
   6
   7 2020-03-04  Jan Beulich  <jbeulich@suse.com>
   8
   9         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
  10         (prefix_table): Move vmmcall here. Add vmgexit.
  11         (rm_table): Replace vmmcall entry by prefix_table[] escape.
  12         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
  13         (cpu_flags): Add CpuSEV_ES entry.
  14         * i386-opc.h (CpuSEV_ES): New.
  15         (union i386_cpu_flags): Add cpusev_es field.
  16         * i386-opc.tbl (vmgexit): New.
  17         * i386-init.h, i386-tbl.h: Re-generate.
  18
  19 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
  20
  21         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
  22         with MnemonicSize.
  23         * i386-opc.h (IGNORESIZE): New.
  24         (DEFAULTSIZE): Likewise.
  25         (IgnoreSize): Removed.
  26         (DefaultSize): Likewise.
  27         (MnemonicSize): New.
  28         (i386_opcode_modifier): Replace ignoresize/defaultsize with
  29         mnemonicsize.
  30         * i386-opc.tbl (IgnoreSize): New.
  31         (DefaultSize): Likewise.
  32         * i386-tbl.h: Regenerated.
  33
  34 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
  35
  36         PR 25627
  37         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
  38         instructions.
  39
  40 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
  41
  42         PR gas/25622
  43         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
  44         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
  45         * i386-tbl.h: Regenerated.
  46
  47 2020-02-26  Alan Modra  <amodra@gmail.com>
  48
  49         * aarch64-asm.c: Indent labels correctly.
  50         * aarch64-dis.c: Likewise.
  51         * aarch64-gen.c: Likewise.
  52         * aarch64-opc.c: Likewise.
  53         * alpha-dis.c: Likewise.
  54         * i386-dis.c: Likewise.
  55         * nds32-asm.c: Likewise.
  56         * nfp-dis.c: Likewise.
  57         * visium-dis.c: Likewise.
  58
  59 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
  60
  61         * arc-regs.h (int_vector_base): Make it available for all ARC
  62         CPUs.
  63
  64 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
  65
  66         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
  67         changed.
  68
  69 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
  70
  71         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
  72         c.mv/c.li if rs1 is zero.
  73
  74 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
  75
  76         * i386-gen.c (cpu_flag_init): Replace CpuABM with
  77         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
  78         CPU_POPCNT_FLAGS.
  79         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
  80         * i386-opc.h (CpuABM): Removed.
  81         (CpuPOPCNT): New.
  82         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
  83         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
  84         popcnt.  Remove CpuABM from lzcnt.
  85         * i386-init.h: Regenerated.
  86         * i386-tbl.h: Likewise.
  87
  88 2020-02-17  Jan Beulich  <jbeulich@suse.com>
  89
  90         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
  91         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
  92         VexW1 instead of open-coding them.
  93         * i386-tbl.h: Re-generate.
  94
  95 2020-02-17  Jan Beulich  <jbeulich@suse.com>
  96
  97         * i386-opc.tbl (AddrPrefixOpReg): Define.
  98         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
  99         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 100         templates. Drop NoRex64.
 101         * i386-tbl.h: Re-generate.
 102
 103 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 104
 105         PR gas/6518
 106         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 107         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 108         into Intel syntax instance (with Unpsecified) and AT&T one
 109         (without).
 110         (vcvtneps2bf16): Likewise, along with folding the two so far
 111         separate ones.
 112         * i386-tbl.h: Re-generate.
 113
 114 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 115
 116         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 117         CPU_ANY_SSE4A_FLAGS.
 118
 119 2020-02-17  Alan Modra  <amodra@gmail.com>
 120
 121         * i386-gen.c (cpu_flag_init): Correct last change.
 122
 123 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 124
 125         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 126         CPU_ANY_SSE4_FLAGS.
 127
 128 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 129
 130         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 131         (movzx): Likewise.
 132
 133 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 134
 135         PR gas/25438
 136         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 137         destination for Cpu64-only variant.
 138         (movzx): Fold patterns.
 139         * i386-tbl.h: Re-generate.
 140
 141 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 142
 143         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 144         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 145         CPU_ANY_SSE4_FLAGS entry.
 146         * i386-init.h: Re-generate.
 147
 148 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 149
 150         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 151         with Unspecified, making the present one AT&T syntax only.
 152         * i386-tbl.h: Re-generate.
 153
 154 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 155
 156         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 157         * i386-tbl.h: Re-generate.
 158
 159 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 160
 161         PR gas/24546
 162         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 163         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 164         Amd64 and Intel64 templates.
 165         (call, jmp): Likewise for far indirect variants. Dro
 166         Unspecified.
 167         * i386-tbl.h: Re-generate.
 168
 169 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 170
 171         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 172         * i386-opc.h (ShortForm): Delete.
 173         (struct i386_opcode_modifier): Remove shortform field.
 174         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 175         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 176         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 177         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 178         Drop ShortForm.
 179         * i386-tbl.h: Re-generate.
 180
 181 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 182
 183         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 184         fucompi): Drop ShortForm from operand-less templates.
 185         * i386-tbl.h: Re-generate.
 186
 187 2020-02-11  Alan Modra  <amodra@gmail.com>
 188
 189         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 190         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 191         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 192         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 193         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 194
 195 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 196
 197         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 198         (cde_opcodes): Add VCX* instructions.
 199
 200 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 201             Matthew Malcomson  <matthew.malcomson@arm.com>
 202
 203         * arm-dis.c (struct cdeopcode32): New.
 204         (CDE_OPCODE): New macro.
 205         (cde_opcodes): New disassembly table.
 206         (regnames): New option to table.
 207         (cde_coprocs): New global variable.
 208         (print_insn_cde): New
 209         (print_insn_thumb32): Use print_insn_cde.
 210         (parse_arm_disassembler_options): Parse coprocN args.
 211
 212 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 213
 214         PR gas/25516
 215         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 216         with ISA64.
 217         * i386-opc.h (AMD64): Removed.
 218         (Intel64): Likewose.
 219         (AMD64): New.
 220         (INTEL64): Likewise.
 221         (INTEL64ONLY): Likewise.
 222         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 223         * i386-opc.tbl (Amd64): New.
 224         (Intel64): Likewise.
 225         (Intel64Only): Likewise.
 226         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 227         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 228         * i386-tbl.h: Regenerated.
 229
 230 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 231
 232         PR 25469
 233         * z80-dis.c: Add support for GBZ80 opcodes.
 234
 235 2020-02-04  Alan Modra  <amodra@gmail.com>
 236
 237         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 238
 239 2020-02-03  Alan Modra  <amodra@gmail.com>
 240
 241         * m32c-ibld.c: Regenerate.
 242
 243 2020-02-01  Alan Modra  <amodra@gmail.com>
 244
 245         * frv-ibld.c: Regenerate.
 246
 247 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 248
 249         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 250         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 251         (OP_E_memory): Replace xmm_mdq_mode case label by
 252         vex_scalar_w_dq_mode one.
 253         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 254
 255 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 256
 257         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 258         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 259         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 260         (intel_operand_size): Drop vex_w_dq_mode case label.
 261
 262 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 263
 264         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 265         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 266
 267 2020-01-30  Alan Modra  <amodra@gmail.com>
 268
 269         * m32c-ibld.c: Regenerate.
 270
 271 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 272
 273         * bpf-opc.c: Regenerate.
 274
 275 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 276
 277         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 278         (dis386): Use them to replace C2/C3 table entries.
 279         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 280         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 281         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 282         * i386-tbl.h: Re-generate.
 283
 284 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 285
 286         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 287         forms.
 288         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 289         DefaultSize.
 290         * i386-tbl.h: Re-generate.
 291
 292 2020-01-30  Alan Modra  <amodra@gmail.com>
 293
 294         * tic4x-dis.c (tic4x_dp): Make unsigned.
 295
 296 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 297             Jan Beulich  <jbeulich@suse.com>
 298
 299         PR binutils/25445
 300         * i386-dis.c (MOVSXD_Fixup): New function.
 301         (movsxd_mode): New enum.
 302         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 303         (intel_operand_size): Handle movsxd_mode.
 304         (OP_E_register): Likewise.
 305         (OP_G): Likewise.
 306         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 307         register on movsxd.  Add movsxd with 16-bit destination register
 308         for AMD64 and Intel64 ISAs.
 309         * i386-tbl.h: Regenerated.
 310
 311 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 312
 313         PR 25403
 314         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 315         * aarch64-asm-2.c: Regenerate
 316         * aarch64-dis-2.c: Likewise.
 317         * aarch64-opc-2.c: Likewise.
 318
 319 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 320
 321         * i386-opc.tbl (sysret): Drop DefaultSize.
 322         * i386-tbl.h: Re-generate.
 323
 324 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 325
 326         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 327         Dword.
 328         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 329         * i386-tbl.h: Re-generate.
 330
 331 2020-01-20  Nick Clifton  <nickc@redhat.com>
 332
 333         * po/de.po: Updated German translation.
 334         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 335         * po/uk.po: Updated Ukranian translation.
 336
 337 2020-01-20  Alan Modra  <amodra@gmail.com>
 338
 339         * hppa-dis.c (fput_const): Remove useless cast.
 340
 341 2020-01-20  Alan Modra  <amodra@gmail.com>
 342
 343         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 344
 345 2020-01-18  Nick Clifton  <nickc@redhat.com>
 346
 347         * configure: Regenerate.
 348         * po/opcodes.pot: Regenerate.
 349
 350 2020-01-18  Nick Clifton  <nickc@redhat.com>
 351
 352         Binutils 2.34 branch created.
 353
 354 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 355
 356         * opintl.h: Fix spelling error (seperate).
 357
 358 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 359
 360         * i386-opc.tbl: Add {vex} pseudo prefix.
 361         * i386-tbl.h: Regenerated.
 362
 363 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 364
 365         PR 25376
 366         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 367         (neon_opcodes): Likewise.
 368         (select_arm_features): Make sure we enable MVE bits when selecting
 369         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 370         any architecture.
 371
 372 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 373
 374         * i386-opc.tbl: Drop stale comment from XOP section.
 375
 376 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 377
 378         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 379         (extractps): Add VexWIG to SSE2AVX forms.
 380         * i386-tbl.h: Re-generate.
 381
 382 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 383
 384         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 385         Size64 from and use VexW1 on SSE2AVX forms.
 386         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 387         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 388         * i386-tbl.h: Re-generate.
 389
 390 2020-01-15  Alan Modra  <amodra@gmail.com>
 391
 392         * tic4x-dis.c (tic4x_version): Make unsigned long.
 393         (optab, optab_special, registernames): New file scope vars.
 394         (tic4x_print_register): Set up registernames rather than
 395         malloc'd registertable.
 396         (tic4x_disassemble): Delete optable and optable_special.  Use
 397         optab and optab_special instead.  Throw away old optab,
 398         optab_special and registernames when info->mach changes.
 399
 400 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 401
 402         PR 25377
 403         * z80-dis.c (suffix): Use .db instruction to generate double
 404         prefix.
 405
 406 2020-01-14  Alan Modra  <amodra@gmail.com>
 407
 408         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 409         values to unsigned before shifting.
 410
 411 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 412
 413         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 414         flow instructions.
 415         (print_insn_thumb16, print_insn_thumb32): Likewise.
 416         (print_insn): Initialize the insn info.
 417         * i386-dis.c (print_insn): Initialize the insn info fields, and
 418         detect jumps.
 419
 420 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 421
 422         * arc-opc.c (C_NE): Make it required.
 423
 424 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 425
 426         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 427         reserved register name.
 428
 429 2020-01-13  Alan Modra  <amodra@gmail.com>
 430
 431         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 432         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 433
 434 2020-01-13  Alan Modra  <amodra@gmail.com>
 435
 436         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 437         result of wasm_read_leb128 in a uint64_t and check that bits
 438         are not lost when copying to other locals.  Use uint32_t for
 439         most locals.  Use PRId64 when printing int64_t.
 440
 441 2020-01-13  Alan Modra  <amodra@gmail.com>
 442
 443         * score-dis.c: Formatting.
 444         * score7-dis.c: Formatting.
 445
 446 2020-01-13  Alan Modra  <amodra@gmail.com>
 447
 448         * score-dis.c (print_insn_score48): Use unsigned variables for
 449         unsigned values.  Don't left shift negative values.
 450         (print_insn_score32): Likewise.
 451         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 452
 453 2020-01-13  Alan Modra  <amodra@gmail.com>
 454
 455         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 456
 457 2020-01-13  Alan Modra  <amodra@gmail.com>
 458
 459         * fr30-ibld.c: Regenerate.
 460
 461 2020-01-13  Alan Modra  <amodra@gmail.com>
 462
 463         * xgate-dis.c (print_insn): Don't left shift signed value.
 464         (ripBits): Formatting, use 1u.
 465
 466 2020-01-10  Alan Modra  <amodra@gmail.com>
 467
 468         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 469         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 470
 471 2020-01-10  Alan Modra  <amodra@gmail.com>
 472
 473         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 474         and XRREG value earlier to avoid a shift with negative exponent.
 475         * m10200-dis.c (disassemble): Similarly.
 476
 477 2020-01-09  Nick Clifton  <nickc@redhat.com>
 478
 479         PR 25224
 480         * z80-dis.c (ld_ii_ii): Use correct cast.
 481
 482 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 483
 484         PR 25224
 485         * z80-dis.c (ld_ii_ii): Use character constant when checking
 486         opcode byte value.
 487
 488 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 489
 490         * i386-dis.c (SEP_Fixup): New.
 491         (SEP): Define.
 492         (dis386_twobyte): Use it for sysenter/sysexit.
 493         (enum x86_64_isa): Change amd64 enumerator to value 1.
 494         (OP_J): Compare isa64 against intel64 instead of amd64.
 495         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 496         forms.
 497         * i386-tbl.h: Re-generate.
 498
 499 2020-01-08  Alan Modra  <amodra@gmail.com>
 500
 501         * z8k-dis.c: Include libiberty.h
 502         (instr_data_s): Make max_fetched unsigned.
 503         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 504         Don't exceed byte_info bounds.
 505         (output_instr): Make num_bytes unsigned.
 506         (unpack_instr): Likewise for nibl_count and loop.
 507         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 508         idx unsigned.
 509         * z8k-opc.h: Regenerate.
 510
 511 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 512
 513         * arc-tbl.h (llock): Use 'LLOCK' as class.
 514         (llockd): Likewise.
 515         (scond): Use 'SCOND' as class.
 516         (scondd): Likewise.
 517         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 518         (scondd): Likewise.
 519
 520 2020-01-06  Alan Modra  <amodra@gmail.com>
 521
 522         * m32c-ibld.c: Regenerate.
 523
 524 2020-01-06  Alan Modra  <amodra@gmail.com>
 525
 526         PR 25344
 527         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 528         Peek at next byte to prevent recursion on repeated prefix bytes.
 529         Ensure uninitialised "mybuf" is not accessed.
 530         (print_insn_z80): Don't zero n_fetch and n_used here,..
 531         (print_insn_z80_buf): ..do it here instead.
 532
 533 2020-01-04  Alan Modra  <amodra@gmail.com>
 534
 535         * m32r-ibld.c: Regenerate.
 536
 537 2020-01-04  Alan Modra  <amodra@gmail.com>
 538
 539         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 540
 541 2020-01-04  Alan Modra  <amodra@gmail.com>
 542
 543         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 544
 545 2020-01-04  Alan Modra  <amodra@gmail.com>
 546
 547         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 548
 549 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 550
 551         * aarch64-tbl.h (aarch64_opcode_table): Use
 552         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 553
 554 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 555
 556         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 557         forms of SUDOT and USDOT.
 558
 559 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 560
 561         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 562         uzip{1,2}.
 563         * opcodes/aarch64-dis-2.c: Re-generate.
 564
 565 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 566
 567         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 568         FMMLA encoding.
 569         * opcodes/aarch64-dis-2.c: Re-generate.
 570
 571 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 572
 573         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 574
 575 2020-01-01  Alan Modra  <amodra@gmail.com>
 576
 577         Update year range in copyright notice of all files.
 578
 579 For older changes see ChangeLog-2019
 580 \f
 581 Copyright (C) 2020 Free Software Foundation, Inc.
 582
 583 Copying and distribution of this file, with or without modification,
 584 are permitted in any medium without royalty provided the copyright
 585 notice and this notice are preserved.
 586
 587 Local Variables:
 588 mode: change-log
 589 left-margin: 8
 590 fill-column: 74
 591 version-control: never
 592 End: