opcodes/ChangeLog

   1 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
   2             Faraz Shahbazker  <fshahbazker@wavecomp.com>
   3
   4         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
   5
   6 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
   7
   8         * s12z-opc.h: Add extern "C" bracketing to help
   9         users who wish to use this interface in c++ code.
  10
  11 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
  12
  13         * s12z-opc.c (bm_decode): Handle bit map operations with the
  14         "reserved0" mode.
  15
  16 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  17
  18         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
  19         specifier.  Add entries for VLDR and VSTR of system registers.
  20         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
  21         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
  22         of %J and %K format specifier.
  23
  24 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  25
  26         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
  27         Add new entries for VSCCLRM instruction.
  28         (print_insn_coprocessor): Handle new %C format control code.
  29
  30 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  31
  32         * arm-dis.c (enum isa): New enum.
  33         (struct sopcode32): New structure.
  34         (coprocessor_opcodes): change type of entries to struct sopcode32 and
  35         set isa field of all current entries to ANY.
  36         (print_insn_coprocessor): Change type of insn to struct sopcode32.
  37         Only match an entry if its isa field allows the current mode.
  38
  39 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  40
  41         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
  42         CLRM.
  43         (print_insn_thumb32): Add logic to print %n CLRM register list.
  44
  45 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  46
  47         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
  48         and %Q patterns.
  49
  50 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  51
  52         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
  53         (print_insn_thumb32): Edit the switch case for %Z.
  54
  55 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  56
  57         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
  58
  59 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  60
  61         * arm-dis.c (thumb32_opcodes): New instruction bfl.
  62
  63 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  64
  65         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
  66
  67 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  68
  69         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
  70         Arm register with r13 and r15 unpredictable.
  71         (thumb32_opcodes): New instructions for bfx and bflx.
  72
  73 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  74
  75         * arm-dis.c (thumb32_opcodes): New instructions for bf.
  76
  77 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  78
  79         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
  80
  81 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  82
  83         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
  84
  85 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  86
  87         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
  88
  89 2019-04-12  John Darrington <john@darrington.wattle.id.au>
  90
  91         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
  92         "optr". ("operator" is a reserved word in c++).
  93
  94 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
  95
  96         * aarch64-opc.c (aarch64_print_operand): Add case for
  97         AARCH64_OPND_Rt_SP.
  98         (verify_constraints): Likewise.
  99         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 100         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 101         to accept Rt|SP as first operand.
 102         (AARCH64_OPERANDS): Add new Rt_SP.
 103         * aarch64-asm-2.c: Regenerated.
 104         * aarch64-dis-2.c: Regenerated.
 105         * aarch64-opc-2.c: Regenerated.
 106
 107 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 108
 109         * aarch64-asm-2.c: Regenerated.
 110         * aarch64-dis-2.c: Likewise.
 111         * aarch64-opc-2.c: Likewise.
 112         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 113
 114 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 115
 116         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 117
 118 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 119
 120         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 121         * i386-init.h: Regenerated.
 122
 123 2019-04-07  Alan Modra  <amodra@gmail.com>
 124
 125         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 126         op_separator to control printing of spaces, comma and parens
 127         rather than need_comma, need_paren and spaces vars.
 128
 129 2019-04-07  Alan Modra  <amodra@gmail.com>
 130
 131         PR 24421
 132         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 133         (print_insn_neon, print_insn_arm): Likewise.
 134
 135 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 136
 137         * i386-dis-evex.h (evex_table): Updated to support BF16
 138         instructions.
 139         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 140         and EVEX_W_0F3872_P_3.
 141         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 142         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 143         * i386-opc.h (enum): Add CpuAVX512_BF16.
 144         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 145         * i386-opc.tbl: Add AVX512 BF16 instructions.
 146         * i386-init.h: Regenerated.
 147         * i386-tbl.h: Likewise.
 148
 149 2019-04-05  Alan Modra  <amodra@gmail.com>
 150
 151         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 152         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 153         to favour printing of "-" branch hint when using the "y" bit.
 154         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 155
 156 2019-04-05  Alan Modra  <amodra@gmail.com>
 157
 158         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 159         opcode until first operand is output.
 160
 161 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 162
 163         PR gas/24349
 164         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 165         (valid_bo_post_v2): Add support for 'at' branch hints.
 166         (insert_bo): Only error on branch on ctr.
 167         (get_bo_hint_mask): New function.
 168         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 169         for inserting 'at' branch hints.
 170         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 171         for extracting 'at' branch hints.
 172         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 173         (BOE): Delete operand.
 174         (BOM, BOP): New operands.
 175         (RM): Update value.
 176         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 177         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 178         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 179         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 180         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 181         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 182         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 183         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 184         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 185         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 186         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 187         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 188         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 189         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 190         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 191         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 192         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 193         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 194         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 195         bttarl+>: New extended mnemonics.
 196
 197 2019-03-28  Alan Modra  <amodra@gmail.com>
 198
 199         PR 24390
 200         * ppc-opc.c (BTF): Define.
 201         (powerpc_opcodes): Use for mtfsb*.
 202         * ppc-dis.c (print_insn_powerpc): Print fields with both
 203         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 204
 205 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 206
 207         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 208         (mapping_symbol_for_insn): Implement new algorithm.
 209         (print_insn): Remove duplicate code.
 210
 211 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 212
 213         * aarch64-dis.c (print_insn_aarch64):
 214         Implement override.
 215
 216 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 217
 218         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 219         order.
 220
 221 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 222
 223         * aarch64-dis.c (last_stop_offset): New.
 224         (print_insn_aarch64): Use stop_offset.
 225
 226 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 227
 228         PR gas/24359
 229         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 230         CPU_ANY_AVX2_FLAGS.
 231         * i386-init.h: Regenerated.
 232
 233 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 234
 235         PR gas/24348
 236         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 237         vmovdqu16, vmovdqu32 and vmovdqu64.
 238         * i386-tbl.h: Regenerated.
 239
 240 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 241
 242         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 243         from vstrszb, vstrszh, and vstrszf.
 244
 245 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 246
 247         * s390-opc.txt: Add instruction descriptions.
 248
 249 2019-02-08  Jim Wilson  <jimw@sifive.com>
 250
 251         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 252         <bne>: Likewise.
 253
 254 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 255
 256         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 257
 258 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 259
 260         PR binutils/23212
 261         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 262         * aarch64-opc.c (verify_elem_sd): New.
 263         (fields): Add FLD_sz entr.
 264         * aarch64-tbl.h (_SIMD_INSN): New.
 265         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 266         fmulx scalar and vector by element isns.
 267
 268 2019-02-07  Nick Clifton  <nickc@redhat.com>
 269
 270         * po/sv.po: Updated Swedish translation.
 271
 272 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 273
 274         * s390-mkopc.c (main): Accept arch13 as cpu string.
 275         * s390-opc.c: Add new instruction formats and instruction opcode
 276         masks.
 277         * s390-opc.txt: Add new arch13 instructions.
 278
 279 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 280
 281         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 282         (aarch64_opcode): Change encoding for stg, stzg
 283         st2g and st2zg.
 284         * aarch64-asm-2.c: Regenerated.
 285         * aarch64-dis-2.c: Regenerated.
 286         * aarch64-opc-2.c: Regenerated.
 287
 288 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 289
 290         * aarch64-asm-2.c: Regenerated.
 291         * aarch64-dis-2.c: Likewise.
 292         * aarch64-opc-2.c: Likewise.
 293         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 294
 295 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 296             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 297
 298         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 299         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 300         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 301         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 302         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 303         case for ldstgv_indexed.
 304         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 305         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 306         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 307         * aarch64-asm-2.c: Regenerated.
 308         * aarch64-dis-2.c: Regenerated.
 309         * aarch64-opc-2.c: Regenerated.
 310
 311 2019-01-23  Nick Clifton  <nickc@redhat.com>
 312
 313         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 314
 315 2019-01-21  Nick Clifton  <nickc@redhat.com>
 316
 317         * po/de.po: Updated German translation.
 318         * po/uk.po: Updated Ukranian translation.
 319
 320 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 321         * mips-dis.c (mips_arch_choices): Fix typo in
 322         gs464, gs464e and gs264e descriptors.
 323
 324 2019-01-19  Nick Clifton  <nickc@redhat.com>
 325
 326         * configure: Regenerate.
 327         * po/opcodes.pot: Regenerate.
 328
 329 2018-06-24  Nick Clifton  <nickc@redhat.com>
 330
 331         2.32 branch created.
 332
 333 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 334
 335         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 336         if it is null.
 337         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 338         zero.
 339
 340 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 341
 342         * configure: Regenerate.
 343
 344 2019-01-07  Alan Modra  <amodra@gmail.com>
 345
 346         * configure: Regenerate.
 347         * po/POTFILES.in: Regenerate.
 348
 349 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 350
 351         * s12z-opc.c: New file.
 352         * s12z-opc.h: New file.
 353         * s12z-dis.c: Removed all code not directly related to display
 354         of instructions.  Used the interface provided by the new files
 355         instead.
 356         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 357         * Makefile.in: Regenerate.
 358         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 359         * configure: Regenerate.
 360
 361 2019-01-01  Alan Modra  <amodra@gmail.com>
 362
 363         Update year range in copyright notice of all files.
 364
 365 For older changes see ChangeLog-2018
 366 \f
 367 Copyright (C) 2019 Free Software Foundation, Inc.
 368
 369 Copying and distribution of this file, with or without modification,
 370 are permitted in any medium without royalty provided the copyright
 371 notice and this notice are preserved.
 372
 373 Local Variables:
 374 mode: change-log
 375 left-margin: 8
 376 fill-column: 74
 377 version-control: never
 378 End: