1 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
3 * i386-gen.c (cpu_flag_init): Replace CpuABM with
4 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
6 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
7 * i386-opc.h (CpuABM): Removed.
9 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
10 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
11 popcnt. Remove CpuABM from lzcnt.
12 * i386-init.h: Regenerated.
13 * i386-tbl.h: Likewise.
15 2020-02-17 Jan Beulich <jbeulich@suse.com>
17 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
18 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
19 VexW1 instead of open-coding them.
20 * i386-tbl.h: Re-generate.
22 2020-02-17 Jan Beulich <jbeulich@suse.com>
24 * i386-opc.tbl (AddrPrefixOpReg): Define.
25 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
26 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
27 templates. Drop NoRex64.
28 * i386-tbl.h: Re-generate.
30 2020-02-17 Jan Beulich <jbeulich@suse.com>
33 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
34 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
35 into Intel syntax instance (with Unpsecified) and AT&T one
37 (vcvtneps2bf16): Likewise, along with folding the two so far
39 * i386-tbl.h: Re-generate.
41 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
43 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
46 2020-02-17 Alan Modra <amodra@gmail.com>
48 * i386-gen.c (cpu_flag_init): Correct last change.
50 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
52 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
55 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
57 * i386-opc.tbl (movsx): Remove Intel syntax comments.
60 2020-02-14 Jan Beulich <jbeulich@suse.com>
63 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
64 destination for Cpu64-only variant.
65 (movzx): Fold patterns.
66 * i386-tbl.h: Re-generate.
68 2020-02-13 Jan Beulich <jbeulich@suse.com>
70 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
71 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
72 CPU_ANY_SSE4_FLAGS entry.
73 * i386-init.h: Re-generate.
75 2020-02-12 Jan Beulich <jbeulich@suse.com>
77 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
78 with Unspecified, making the present one AT&T syntax only.
79 * i386-tbl.h: Re-generate.
81 2020-02-12 Jan Beulich <jbeulich@suse.com>
83 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
84 * i386-tbl.h: Re-generate.
86 2020-02-12 Jan Beulich <jbeulich@suse.com>
89 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
90 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
91 Amd64 and Intel64 templates.
92 (call, jmp): Likewise for far indirect variants. Dro
94 * i386-tbl.h: Re-generate.
96 2020-02-11 Jan Beulich <jbeulich@suse.com>
98 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
99 * i386-opc.h (ShortForm): Delete.
100 (struct i386_opcode_modifier): Remove shortform field.
101 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
102 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
103 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
104 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
106 * i386-tbl.h: Re-generate.
108 2020-02-11 Jan Beulich <jbeulich@suse.com>
110 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
111 fucompi): Drop ShortForm from operand-less templates.
112 * i386-tbl.h: Re-generate.
114 2020-02-11 Alan Modra <amodra@gmail.com>
116 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
117 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
118 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
119 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
120 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
122 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
124 * arm-dis.c (print_insn_cde): Define 'V' parse character.
125 (cde_opcodes): Add VCX* instructions.
127 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
128 Matthew Malcomson <matthew.malcomson@arm.com>
130 * arm-dis.c (struct cdeopcode32): New.
131 (CDE_OPCODE): New macro.
132 (cde_opcodes): New disassembly table.
133 (regnames): New option to table.
134 (cde_coprocs): New global variable.
135 (print_insn_cde): New
136 (print_insn_thumb32): Use print_insn_cde.
137 (parse_arm_disassembler_options): Parse coprocN args.
139 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
142 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
144 * i386-opc.h (AMD64): Removed.
148 (INTEL64ONLY): Likewise.
149 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
150 * i386-opc.tbl (Amd64): New.
152 (Intel64Only): Likewise.
153 Replace AMD64 with Amd64. Update sysenter/sysenter with
154 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
155 * i386-tbl.h: Regenerated.
157 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
160 * z80-dis.c: Add support for GBZ80 opcodes.
162 2020-02-04 Alan Modra <amodra@gmail.com>
164 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
166 2020-02-03 Alan Modra <amodra@gmail.com>
168 * m32c-ibld.c: Regenerate.
170 2020-02-01 Alan Modra <amodra@gmail.com>
172 * frv-ibld.c: Regenerate.
174 2020-01-31 Jan Beulich <jbeulich@suse.com>
176 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
177 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
178 (OP_E_memory): Replace xmm_mdq_mode case label by
179 vex_scalar_w_dq_mode one.
180 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
182 2020-01-31 Jan Beulich <jbeulich@suse.com>
184 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
185 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
186 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
187 (intel_operand_size): Drop vex_w_dq_mode case label.
189 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
191 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
192 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
194 2020-01-30 Alan Modra <amodra@gmail.com>
196 * m32c-ibld.c: Regenerate.
198 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
200 * bpf-opc.c: Regenerate.
202 2020-01-30 Jan Beulich <jbeulich@suse.com>
204 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
205 (dis386): Use them to replace C2/C3 table entries.
206 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
207 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
208 ones. Use Size64 instead of DefaultSize on Intel64 ones.
209 * i386-tbl.h: Re-generate.
211 2020-01-30 Jan Beulich <jbeulich@suse.com>
213 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
215 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
217 * i386-tbl.h: Re-generate.
219 2020-01-30 Alan Modra <amodra@gmail.com>
221 * tic4x-dis.c (tic4x_dp): Make unsigned.
223 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
224 Jan Beulich <jbeulich@suse.com>
227 * i386-dis.c (MOVSXD_Fixup): New function.
228 (movsxd_mode): New enum.
229 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
230 (intel_operand_size): Handle movsxd_mode.
231 (OP_E_register): Likewise.
233 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
234 register on movsxd. Add movsxd with 16-bit destination register
235 for AMD64 and Intel64 ISAs.
236 * i386-tbl.h: Regenerated.
238 2020-01-27 Tamar Christina <tamar.christina@arm.com>
241 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
242 * aarch64-asm-2.c: Regenerate
243 * aarch64-dis-2.c: Likewise.
244 * aarch64-opc-2.c: Likewise.
246 2020-01-21 Jan Beulich <jbeulich@suse.com>
248 * i386-opc.tbl (sysret): Drop DefaultSize.
249 * i386-tbl.h: Re-generate.
251 2020-01-21 Jan Beulich <jbeulich@suse.com>
253 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
255 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
256 * i386-tbl.h: Re-generate.
258 2020-01-20 Nick Clifton <nickc@redhat.com>
260 * po/de.po: Updated German translation.
261 * po/pt_BR.po: Updated Brazilian Portuguese translation.
262 * po/uk.po: Updated Ukranian translation.
264 2020-01-20 Alan Modra <amodra@gmail.com>
266 * hppa-dis.c (fput_const): Remove useless cast.
268 2020-01-20 Alan Modra <amodra@gmail.com>
270 * arm-dis.c (print_insn_arm): Wrap 'T' value.
272 2020-01-18 Nick Clifton <nickc@redhat.com>
274 * configure: Regenerate.
275 * po/opcodes.pot: Regenerate.
277 2020-01-18 Nick Clifton <nickc@redhat.com>
279 Binutils 2.34 branch created.
281 2020-01-17 Christian Biesinger <cbiesinger@google.com>
283 * opintl.h: Fix spelling error (seperate).
285 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
287 * i386-opc.tbl: Add {vex} pseudo prefix.
288 * i386-tbl.h: Regenerated.
290 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
293 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
294 (neon_opcodes): Likewise.
295 (select_arm_features): Make sure we enable MVE bits when selecting
296 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
299 2020-01-16 Jan Beulich <jbeulich@suse.com>
301 * i386-opc.tbl: Drop stale comment from XOP section.
303 2020-01-16 Jan Beulich <jbeulich@suse.com>
305 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
306 (extractps): Add VexWIG to SSE2AVX forms.
307 * i386-tbl.h: Re-generate.
309 2020-01-16 Jan Beulich <jbeulich@suse.com>
311 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
312 Size64 from and use VexW1 on SSE2AVX forms.
313 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
314 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
315 * i386-tbl.h: Re-generate.
317 2020-01-15 Alan Modra <amodra@gmail.com>
319 * tic4x-dis.c (tic4x_version): Make unsigned long.
320 (optab, optab_special, registernames): New file scope vars.
321 (tic4x_print_register): Set up registernames rather than
322 malloc'd registertable.
323 (tic4x_disassemble): Delete optable and optable_special. Use
324 optab and optab_special instead. Throw away old optab,
325 optab_special and registernames when info->mach changes.
327 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
330 * z80-dis.c (suffix): Use .db instruction to generate double
333 2020-01-14 Alan Modra <amodra@gmail.com>
335 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
336 values to unsigned before shifting.
338 2020-01-13 Thomas Troeger <tstroege@gmx.de>
340 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
342 (print_insn_thumb16, print_insn_thumb32): Likewise.
343 (print_insn): Initialize the insn info.
344 * i386-dis.c (print_insn): Initialize the insn info fields, and
347 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
349 * arc-opc.c (C_NE): Make it required.
351 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
353 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
354 reserved register name.
356 2020-01-13 Alan Modra <amodra@gmail.com>
358 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
359 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
361 2020-01-13 Alan Modra <amodra@gmail.com>
363 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
364 result of wasm_read_leb128 in a uint64_t and check that bits
365 are not lost when copying to other locals. Use uint32_t for
366 most locals. Use PRId64 when printing int64_t.
368 2020-01-13 Alan Modra <amodra@gmail.com>
370 * score-dis.c: Formatting.
371 * score7-dis.c: Formatting.
373 2020-01-13 Alan Modra <amodra@gmail.com>
375 * score-dis.c (print_insn_score48): Use unsigned variables for
376 unsigned values. Don't left shift negative values.
377 (print_insn_score32): Likewise.
378 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
380 2020-01-13 Alan Modra <amodra@gmail.com>
382 * tic4x-dis.c (tic4x_print_register): Remove dead code.
384 2020-01-13 Alan Modra <amodra@gmail.com>
386 * fr30-ibld.c: Regenerate.
388 2020-01-13 Alan Modra <amodra@gmail.com>
390 * xgate-dis.c (print_insn): Don't left shift signed value.
391 (ripBits): Formatting, use 1u.
393 2020-01-10 Alan Modra <amodra@gmail.com>
395 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
396 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
398 2020-01-10 Alan Modra <amodra@gmail.com>
400 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
401 and XRREG value earlier to avoid a shift with negative exponent.
402 * m10200-dis.c (disassemble): Similarly.
404 2020-01-09 Nick Clifton <nickc@redhat.com>
407 * z80-dis.c (ld_ii_ii): Use correct cast.
409 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
412 * z80-dis.c (ld_ii_ii): Use character constant when checking
415 2020-01-09 Jan Beulich <jbeulich@suse.com>
417 * i386-dis.c (SEP_Fixup): New.
419 (dis386_twobyte): Use it for sysenter/sysexit.
420 (enum x86_64_isa): Change amd64 enumerator to value 1.
421 (OP_J): Compare isa64 against intel64 instead of amd64.
422 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
424 * i386-tbl.h: Re-generate.
426 2020-01-08 Alan Modra <amodra@gmail.com>
428 * z8k-dis.c: Include libiberty.h
429 (instr_data_s): Make max_fetched unsigned.
430 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
431 Don't exceed byte_info bounds.
432 (output_instr): Make num_bytes unsigned.
433 (unpack_instr): Likewise for nibl_count and loop.
434 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
436 * z8k-opc.h: Regenerate.
438 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
440 * arc-tbl.h (llock): Use 'LLOCK' as class.
442 (scond): Use 'SCOND' as class.
444 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
447 2020-01-06 Alan Modra <amodra@gmail.com>
449 * m32c-ibld.c: Regenerate.
451 2020-01-06 Alan Modra <amodra@gmail.com>
454 * z80-dis.c (suffix): Don't use a local struct buffer copy.
455 Peek at next byte to prevent recursion on repeated prefix bytes.
456 Ensure uninitialised "mybuf" is not accessed.
457 (print_insn_z80): Don't zero n_fetch and n_used here,..
458 (print_insn_z80_buf): ..do it here instead.
460 2020-01-04 Alan Modra <amodra@gmail.com>
462 * m32r-ibld.c: Regenerate.
464 2020-01-04 Alan Modra <amodra@gmail.com>
466 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
468 2020-01-04 Alan Modra <amodra@gmail.com>
470 * crx-dis.c (match_opcode): Avoid shift left of signed value.
472 2020-01-04 Alan Modra <amodra@gmail.com>
474 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
476 2020-01-03 Jan Beulich <jbeulich@suse.com>
478 * aarch64-tbl.h (aarch64_opcode_table): Use
479 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
481 2020-01-03 Jan Beulich <jbeulich@suse.com>
483 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
484 forms of SUDOT and USDOT.
486 2020-01-03 Jan Beulich <jbeulich@suse.com>
488 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
490 * opcodes/aarch64-dis-2.c: Re-generate.
492 2020-01-03 Jan Beulich <jbeulich@suse.com>
494 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
496 * opcodes/aarch64-dis-2.c: Re-generate.
498 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
500 * z80-dis.c: Add support for eZ80 and Z80 instructions.
502 2020-01-01 Alan Modra <amodra@gmail.com>
504 Update year range in copyright notice of all files.
506 For older changes see ChangeLog-2019
508 Copyright (C) 2020 Free Software Foundation, Inc.
510 Copying and distribution of this file, with or without modification,
511 are permitted in any medium without royalty provided the copyright
512 notice and this notice are preserved.
518 version-control: never