1 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
3 * mips16-opc.c (decode_mips16_operand): Replace `0' and `4'
4 operand codes with `.' and `F' respectively.
5 (mips16_opcodes): Likewise.
7 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
9 * mips-dis.c (print_insn_mips16): Disallow EXTEND prefix
10 matching for INSN2_SHORT_ONLY opcode table entries.
11 * mips16-opc.c (SH): New macro.
12 (mips16_opcodes): Set SH in `pinfo2' for non-extensible
13 instruction entries: "nop", "addu", "and", "break", "cmp",
14 "daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu",
15 "drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv",
16 "dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j",
17 "jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg",
18 "not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu",
19 "srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb",
20 "seh", "sew", "zeb", "zeh", "zew" and "extend".
22 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
24 * mips16-opc.c (decode_mips16_operand) <'6'>: Remove extended
27 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
29 * mips16-opc.c (mips16_opcodes): Set NODS in `pinfo' for
32 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
34 * mips-dis.c (set_default_mips_dis_options): Use
35 HAVE_BFD_MIPS_ELF_GET_ABIFLAGS rather than BFD64 to guard the
36 call to `bfd_mips_elf_get_abiflags'.
37 * configure.ac: Check for `bfd_mips_elf_get_abiflags' in BFD.
38 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add `libbfd.la'.
39 * aclocal.m4: Regenerate.
40 * configure: Regenerate.
41 * config.in: Regenerate.
42 * Makefile.in: Regenerate.
44 2016-12-23 Tristan Gingold <gingold@adacore.com>
46 * configure: Regenerate.
48 2016-12-23 Tristan Gingold <gingold@adacore.com>
50 * po/opcodes.pot: Regenerate.
52 2016-12-21 Andrew Waterman <andrew@sifive.com>
54 * riscv-opc.c (riscv_opcodes): Reorder jal and call entries.
56 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
58 * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than
59 ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry.
60 (print_insn_mips16): Check opcode entries for validity against
61 the ISA level and ASE set selected.
63 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
65 * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
66 `insn' together, with `extend' as the high-order 16 bits.
67 (match_kind): New enum.
68 (print_insn_mips16): Rework for 32-bit instruction matching.
69 Do not dump EXTEND prefixes here.
70 * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
71 Recode `match' and `mask' fields as 32-bit in absolute "jal" and
74 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
76 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
77 than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu"
80 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
82 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
83 than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
86 2016-12-20 Andrew Waterman <andrew@sifive.com>
88 * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to
91 2016-12-20 Andrew Waterman <andrew@sifive.com>
93 * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as
96 2016-12-20 Andrew Waterman <andrew@sifive.com>
98 * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
101 2016-12-20 Andrew Waterman <andrew@sifive.com>
103 * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
104 XLEN when none is provided.
106 2016-12-20 Andrew Waterman <andrew@sifive.com>
108 * riscv-opc.c: Formatting fixes.
110 2016-12-20 Alan Modra <amodra@gmail.com>
112 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
113 * Makefile.in: Regenerate.
114 * po/POTFILES.in: Regenerate.
116 2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
118 * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
119 Only examine ELF file structures here.
121 2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
123 * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
124 `bfd_mips_elf_get_abiflags' here.
126 2016-12-16 Nick Clifton <nickc@redhat.com>
128 * arm-dis.c (print_insn_thumb32): Fix compile time warning
129 computing value_in_comment.
131 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
133 * mips-dis.c (mips_convert_abiflags_ases): New function.
134 (set_default_mips_dis_options): Also infer ASE flags from ELF
137 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
139 * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
140 header flag interpretation code.
142 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
144 * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
145 `pinfo2' with SP-relative "sd" entries.
147 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
149 * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
152 2016-12-13 Renlin Li <renlin.li@arm.com>
154 * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
156 (operand_general_constraint_met_p): Remove case for CP_REG.
157 (aarch64_print_operand): Print CRn, CRm operand using imm field.
158 * aarch64-tbl.h (QL_SYS): Use CR qualifier.
160 (aarch64_opcode_table): Change CRn, CRm operand class and type.
161 * aarch64-opc-2.c : Regenerate.
162 * aarch64-asm-2.c : Likewise.
163 * aarch64-dis-2.c : Likewise.
165 2016-12-12 Yao Qi <yao.qi@linaro.org>
167 * rx-dis.c: Include <setjmp.h>
168 (struct private): New.
169 (rx_get_byte): Check return value of read_memory_func, and
170 call memory_error_func and OPCODES_SIGLONGJMP on error.
171 (print_insn_rx): Call OPCODES_SIGSETJMP.
173 2016-12-12 Yao Qi <yao.qi@linaro.org>
175 * rl78-dis.c: Include <setjmp.h>.
176 (struct private): New.
177 (rl78_get_byte): Check return value of read_memory_func, and
178 call memory_error_func and OPCODES_SIGLONGJMP on error.
179 (print_insn_rl78_common): Call OPCODES_SIGJMP.
181 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
183 * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
185 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
187 * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
190 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
192 * mips-dis.c (print_insn_mips16): Use a tab rather than a space
193 to separate `extend' and its uninterpreted argument output.
194 Separate hexadecimal halves of undecoded extended instructions
197 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
199 * mips-dis.c (print_mips16_insn_arg): Remove extraneous
200 indentation space across.
202 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
204 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
205 adjustment for PC-relative operations following MIPS16e compact
206 jumps or undefined RR/J(AL)R(C) encodings.
208 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
210 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
211 variable to `reglane_index'.
213 2016-12-08 Luis Machado <lgustavo@codesourcery.com>
215 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
217 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
219 * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
221 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
223 * mips16-opc.c (mips16_opcodes): Update comment naming structure
226 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
228 * mips-dis.c (print_mips_disassembler_options): Reformat output.
230 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
232 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
233 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
235 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
237 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
239 2016-12-01 Nick Clifton <nickc@redhat.com>
242 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
245 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
247 * arc-opc.c (insert_ra_chk): New function.
248 (insert_rb_chk): Likewise.
249 (insert_rad): Update text error message.
250 (insert_rcd): Likewise.
251 (insert_rhv2): Likewise.
252 (insert_r0): Likewise.
253 (insert_r1): Likewise.
254 (insert_r2): Likewise.
255 (insert_r3): Likewise.
256 (insert_sp): Likewise.
257 (insert_gp): Likewise.
258 (insert_pcl): Likewise.
259 (insert_blink): Likewise.
260 (insert_ilink1): Likewise.
261 (insert_ilink2): Likewise.
262 (insert_ras): Likewise.
263 (insert_rbs): Likewise.
264 (insert_rcs): Likewise.
265 (insert_simm3s): Likewise.
266 (insert_rrange): Likewise.
267 (insert_fpel): Likewise.
268 (insert_blinkel): Likewise.
269 (insert_pcel): Likewise.
270 (insert_nps_3bit_dst): Likewise.
271 (insert_nps_3bit_dst_short): Likewise.
272 (insert_nps_3bit_src2_short): Likewise.
273 (insert_nps_bitop_size_2b): Likewise.
274 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
279 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
280 * arc-tbl.h (div, divu): All instructions are DIVREM class.
281 Change first insn argument to check for LP_COUNT usage.
283 (ld, ldd): All instructions are LOAD class. Change first insn
284 argument to check for LP_COUNT usage.
285 (st, std): All instructions are STORE class.
286 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
287 Change first insn argument to check for LP_COUNT usage.
288 (mov): All instructions are MOVE class. Change first insn
289 argument to check for LP_COUNT usage.
291 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
293 * arc-dis.c (is_compatible_p): Remove function.
294 (skip_this_opcode): Don't add any decoding class to decode list.
296 (find_format_from_table): Go through all opcodes, and warn if we
297 use a guessed mnemonic.
299 2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
300 Amit Pawar <amit.pawar@amd.com>
303 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
306 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
308 * configure: Regenerate.
310 2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
312 * sparc-opc.c (HWS_V8): Definition moved from
313 gas/config/tc-sparc.c.
323 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
326 2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
328 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
331 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
333 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
334 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
335 (aarch64_opcode_table): Add fcmla and fcadd.
336 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
337 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
338 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
339 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
340 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
341 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
342 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
343 (operand_general_constraint_met_p): Rotate and index range check.
344 (aarch64_print_operand): Handle rotate operand.
345 * aarch64-asm-2.c: Regenerate.
346 * aarch64-dis-2.c: Likewise.
347 * aarch64-opc-2.c: Likewise.
349 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
351 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
352 * aarch64-asm-2.c: Regenerate.
353 * aarch64-dis-2.c: Regenerate.
354 * aarch64-opc-2.c: Regenerate.
356 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
358 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
359 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
360 * aarch64-asm-2.c: Regenerate.
361 * aarch64-dis-2.c: Regenerate.
362 * aarch64-opc-2.c: Regenerate.
364 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
366 * aarch64-tbl.h (QL_X1NIL): New.
367 (arch64_opcode_table): Add ldraa, ldrab.
368 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
369 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
370 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
371 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
372 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
373 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
374 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
375 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
376 (aarch64_print_operand): Likewise.
377 * aarch64-asm-2.c: Regenerate.
378 * aarch64-dis-2.c: Regenerate.
379 * aarch64-opc-2.c: Regenerate.
381 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
383 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
384 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
385 * aarch64-asm-2.c: Regenerate.
386 * aarch64-dis-2.c: Regenerate.
387 * aarch64-opc-2.c: Regenerate.
389 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
391 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
392 (AARCH64_OPERANDS): Add Rm_SP.
393 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
394 * aarch64-asm-2.c: Regenerate.
395 * aarch64-dis-2.c: Regenerate.
396 * aarch64-opc-2.c: Regenerate.
398 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
400 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
401 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
402 autdzb, xpaci, xpacd.
403 * aarch64-asm-2.c: Regenerate.
404 * aarch64-dis-2.c: Regenerate.
405 * aarch64-opc-2.c: Regenerate.
407 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
409 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
410 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
411 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
412 (aarch64_sys_reg_supported_p): Add feature test for new registers.
414 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
416 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
417 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
418 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
420 * aarch64-asm-2.c: Regenerate.
421 * aarch64-dis-2.c: Regenerate.
423 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
425 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
427 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
430 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
431 * i386-dis.c (EdqwS): Removed.
432 (dqw_swap_mode): Likewise.
433 (intel_operand_size): Don't check dqw_swap_mode.
434 (OP_E_register): Likewise.
435 (OP_E_memory): Likewise.
438 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
439 * i386-tbl.h: Regerated.
441 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
443 * i386-opc.tbl: Merge AVX512F vmovq.
444 * i386-tbl.h: Regerated.
446 2016-11-08 H.J. Lu <hongjiu.lu@intel.com>
449 * i386-dis.c (THREE_BYTE_0F7A): Removed.
450 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
451 (three_byte_table): Remove THREE_BYTE_0F7A.
453 2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
456 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
457 (FGRPd9_4): Replace 1 with 2.
458 (FGRPd9_5): Replace 2 with 3.
459 (FGRPd9_6): Replace 3 with 4.
460 (FGRPd9_7): Replace 4 with 5.
461 (FGRPda_5): Replace 5 with 6.
462 (FGRPdb_4): Replace 6 with 7.
463 (FGRPde_3): Replace 7 with 8.
464 (FGRPdf_4): Replace 8 with 9.
465 (fgrps): Add an entry for Bad_Opcode.
467 2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
469 * arc-opc.c (arc_flag_operands): Add F_DI14.
470 (arc_flag_classes): Add C_DI14.
471 * arc-nps400-tbl.h: Add new exc instructions.
473 2016-11-03 Graham Markall <graham.markall@embecosm.com>
475 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
477 * arc-nps-400-tbl.h: Add dcmac instruction.
478 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
479 (insert_nps_rbdouble_64): Added.
480 (extract_nps_rbdouble_64): Added.
481 (insert_nps_proto_size): Added.
482 (extract_nps_proto_size): Added.
484 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
486 * arc-dis.c (struct arc_operand_iterator): Remove all fields
487 relating to long instruction processing, add new limm field.
488 (OPCODE): Rename to...
489 (OPCODE_32BIT_INSN): ...this.
491 (skip_this_opcode): Handle different instruction lengths, update
493 (special_flag_p): Update parameter type.
494 (find_format_from_table): Update for more instruction lengths.
495 (find_format_long_instructions): Delete.
496 (find_format): Update for more instruction lengths.
497 (arc_insn_length): Likewise.
498 (extract_operand_value): Update for more instruction lengths.
499 (operand_iterator_next): Remove code relating to long
501 (arc_opcode_to_insn_type): New function.
502 (print_insn_arc):Update for more instructions lengths.
503 * arc-ext.c (extInstruction_t): Change argument type.
504 * arc-ext.h (extInstruction_t): Change argument type.
505 * arc-fxi.h: Change type unsigned to unsigned long long
506 extensively throughout.
507 * arc-nps400-tbl.h: Add long instructions taken from
508 arc_long_opcodes table in arc-opc.c.
509 * arc-opc.c: Update parameter types on insert/extract handlers.
510 (arc_long_opcodes): Delete.
511 (arc_num_long_opcodes): Delete.
512 (arc_opcode_len): Update for more instruction lengths.
514 2016-11-03 Graham Markall <graham.markall@embecosm.com>
516 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
518 2016-11-03 Graham Markall <graham.markall@embecosm.com>
520 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
522 (find_format_long_instructions): Likewise.
523 * arc-opc.c (arc_opcode_len): New function.
525 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
527 * arc-nps400-tbl.h: Fix some instruction masks.
529 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
531 * i386-dis.c (REG_82): Removed.
532 (X86_64_82_REG_0): Likewise.
533 (X86_64_82_REG_1): Likewise.
534 (X86_64_82_REG_2): Likewise.
535 (X86_64_82_REG_3): Likewise.
536 (X86_64_82_REG_4): Likewise.
537 (X86_64_82_REG_5): Likewise.
538 (X86_64_82_REG_6): Likewise.
539 (X86_64_82_REG_7): Likewise.
541 (dis386): Use X86_64_82 instead of REG_82.
542 (reg_table): Remove REG_82.
543 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
544 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
545 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
548 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
551 * i386-dis.c (REG_82): New.
552 (X86_64_82_REG_0): Likewise.
553 (X86_64_82_REG_1): Likewise.
554 (X86_64_82_REG_2): Likewise.
555 (X86_64_82_REG_3): Likewise.
556 (X86_64_82_REG_4): Likewise.
557 (X86_64_82_REG_5): Likewise.
558 (X86_64_82_REG_6): Likewise.
559 (X86_64_82_REG_7): Likewise.
560 (dis386): Use REG_82.
561 (reg_table): Add REG_82.
562 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
563 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
564 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
566 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
568 * i386-dis.c (REG_82): Renamed to ...
571 (reg_table): Likewise.
573 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
575 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
576 * i386-dis-evex.h (evex_table): Updated.
577 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
578 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
579 (cpu_flags): Add CpuAVX512_4VNNIW.
580 * i386-opc.h (enum): (AVX512_4VNNIW): New.
581 (i386_cpu_flags): Add cpuavx512_4vnniw.
582 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
583 * i386-init.h: Regenerate.
586 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
588 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
589 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
590 * i386-dis-evex.h (evex_table): Updated.
591 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
592 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
593 (cpu_flags): Add CpuAVX512_4FMAPS.
594 (opcode_modifiers): Add ImplicitQuadGroup modifier.
595 * i386-opc.h (AVX512_4FMAP): New.
596 (i386_cpu_flags): Add cpuavx512_4fmaps.
597 (ImplicitQuadGroup): New.
598 (i386_opcode_modifier): Add implicitquadgroup.
599 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
600 * i386-init.h: Regenerate.
603 2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
604 Andrew Waterman <andrew@sifive.com>
606 Add support for RISC-V architecture.
607 * configure.ac: Add entry for bfd_riscv_arch.
608 * configure: Regenerate.
609 * disassemble.c (disassembler): Add support for riscv.
610 (disassembler_usage): Likewise.
611 * riscv-dis.c: New file.
612 * riscv-opc.c: New file.
614 2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
616 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
617 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
618 (rm_table): Update the RM_0FAE_REG_7 entry.
619 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
620 (cpu_flags): Remove CpuPCOMMIT.
621 * i386-opc.h (CpuPCOMMIT): Removed.
622 (i386_cpu_flags): Remove cpupcommit.
623 * i386-opc.tbl: Remove pcommit.
624 * i386-init.h: Regenerated.
625 * i386-tbl.h: Likewise.
627 2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
630 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
631 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
632 32-bit mode. Don't check vex.register_specifier in 32-bit
634 (OP_VEX): Check for invalid mask registers.
636 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
639 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
642 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
645 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
647 2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
649 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
650 local variable to `index_regno'.
652 2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
654 * arc-tbl.h: Removed any "inv.+" instructions from the table.
656 2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
658 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
661 2016-10-11 Jiong Wang <jiong.wang@arm.com>
664 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
666 2016-10-07 Jiong Wang <jiong.wang@arm.com>
669 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
672 2016-10-07 Alan Modra <amodra@gmail.com>
674 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
676 2016-10-06 Alan Modra <amodra@gmail.com>
678 * aarch64-opc.c: Spell fall through comments consistently.
679 * i386-dis.c: Likewise.
680 * aarch64-dis.c: Add missing fall through comments.
681 * aarch64-opc.c: Likewise.
682 * arc-dis.c: Likewise.
683 * arm-dis.c: Likewise.
684 * i386-dis.c: Likewise.
685 * m68k-dis.c: Likewise.
686 * mep-asm.c: Likewise.
687 * ns32k-dis.c: Likewise.
688 * sh-dis.c: Likewise.
689 * tic4x-dis.c: Likewise.
690 * tic6x-dis.c: Likewise.
691 * vax-dis.c: Likewise.
693 2016-10-06 Alan Modra <amodra@gmail.com>
695 * arc-ext.c (create_map): Add missing break.
696 * msp430-decode.opc (encode_as): Likewise.
697 * msp430-decode.c: Regenerate.
699 2016-10-06 Alan Modra <amodra@gmail.com>
701 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
702 * crx-dis.c (print_insn_crx): Likewise.
704 2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
707 * i386-dis.c (putop): Don't assign alt twice.
709 2016-09-29 Jiong Wang <jiong.wang@arm.com>
712 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
714 2016-09-29 Alan Modra <amodra@gmail.com>
716 * ppc-opc.c (L): Make compulsory.
717 (LOPT): New, optional form of L.
718 (HTM_R): Define as LOPT.
720 (L32OPT): New, optional for 32-bit L.
721 (L2OPT): New, 2-bit L for dcbf.
724 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
725 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
727 <tlbiel, tlbie>: Use LOPT.
728 <wclr, wclrall>: Use L2.
730 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
732 * Makefile.in: Regenerate.
733 * configure: Likewise.
735 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
737 * arc-ext-tbl.h (EXTINSN2OPF): Define.
738 (EXTINSN2OP): Use EXTINSN2OPF.
739 (bspeekm, bspop, modapp): New extension instructions.
740 * arc-opc.c (F_DNZ_ND): Define.
745 * arc-tbl.h (dbnz): New instruction.
746 (prealloc): Allow it for ARC EM.
749 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
751 * aarch64-opc.c (print_immediate_offset_address): Print spaces
752 after commas in addresses.
753 (aarch64_print_operand): Likewise.
755 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
757 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
758 rather than "should be" or "expected to be" in error messages.
760 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
762 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
763 (print_mnemonic_name): ...here.
764 (print_comment): New function.
765 (print_aarch64_insn): Call it.
766 * aarch64-opc.c (aarch64_conds): Add SVE names.
767 (aarch64_print_operand): Print alternative condition names in
770 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
772 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
773 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
774 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
775 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
776 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
777 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
778 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
779 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
780 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
781 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
782 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
783 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
784 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
785 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
786 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
787 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
788 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
789 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
790 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
791 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
792 (OP_SVE_XWU, OP_SVE_XXU): New macros.
793 (aarch64_feature_sve): New variable.
795 (_SVE_INSN): Likewise.
796 (aarch64_opcode_table): Add SVE instructions.
797 * aarch64-opc.h (extract_fields): Declare.
798 * aarch64-opc-2.c: Regenerate.
799 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
800 * aarch64-asm-2.c: Regenerate.
801 * aarch64-dis.c (extract_fields): Make global.
802 (do_misc_decoding): Handle the new SVE aarch64_ops.
803 * aarch64-dis-2.c: Regenerate.
805 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
807 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
808 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
810 * aarch64-opc.c (fields): Add corresponding entries.
811 * aarch64-asm.c (aarch64_get_variant): New function.
812 (aarch64_encode_variant_using_iclass): Likewise.
813 (aarch64_opcode_encode): Call it.
814 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
815 (aarch64_opcode_decode): Call it.
817 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
819 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
820 and FP register operands.
821 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
822 (FLD_SVE_Vn): New aarch64_field_kinds.
823 * aarch64-opc.c (fields): Add corresponding entries.
824 (aarch64_print_operand): Handle the new SVE core and FP register
826 * aarch64-opc-2.c: Regenerate.
827 * aarch64-asm-2.c: Likewise.
828 * aarch64-dis-2.c: Likewise.
830 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
832 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
834 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
835 * aarch64-opc.c (fields): Add corresponding entry.
836 (operand_general_constraint_met_p): Handle the new SVE FP immediate
838 (aarch64_print_operand): Likewise.
839 * aarch64-opc-2.c: Regenerate.
840 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
841 (ins_sve_float_zero_one): New inserters.
842 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
843 (aarch64_ins_sve_float_half_two): Likewise.
844 (aarch64_ins_sve_float_zero_one): Likewise.
845 * aarch64-asm-2.c: Regenerate.
846 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
847 (ext_sve_float_zero_one): New extractors.
848 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
849 (aarch64_ext_sve_float_half_two): Likewise.
850 (aarch64_ext_sve_float_zero_one): Likewise.
851 * aarch64-dis-2.c: Regenerate.
853 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
855 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
856 integer immediate operands.
857 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
858 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
859 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
860 * aarch64-opc.c (fields): Add corresponding entries.
861 (operand_general_constraint_met_p): Handle the new SVE integer
863 (aarch64_print_operand): Likewise.
864 (aarch64_sve_dupm_mov_immediate_p): New function.
865 * aarch64-opc-2.c: Regenerate.
866 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
867 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
868 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
869 (aarch64_ins_limm): ...here.
870 (aarch64_ins_inv_limm): New function.
871 (aarch64_ins_sve_aimm): Likewise.
872 (aarch64_ins_sve_asimm): Likewise.
873 (aarch64_ins_sve_limm_mov): Likewise.
874 (aarch64_ins_sve_shlimm): Likewise.
875 (aarch64_ins_sve_shrimm): Likewise.
876 * aarch64-asm-2.c: Regenerate.
877 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
878 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
879 * aarch64-dis.c (decode_limm): New function, split out from...
880 (aarch64_ext_limm): ...here.
881 (aarch64_ext_inv_limm): New function.
882 (decode_sve_aimm): Likewise.
883 (aarch64_ext_sve_aimm): Likewise.
884 (aarch64_ext_sve_asimm): Likewise.
885 (aarch64_ext_sve_limm_mov): Likewise.
886 (aarch64_top_bit): Likewise.
887 (aarch64_ext_sve_shlimm): Likewise.
888 (aarch64_ext_sve_shrimm): Likewise.
889 * aarch64-dis-2.c: Regenerate.
891 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
893 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
895 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
896 the AARCH64_MOD_MUL_VL entry.
897 (value_aligned_p): Cope with non-power-of-two alignments.
898 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
899 (print_immediate_offset_address): Likewise.
900 (aarch64_print_operand): Likewise.
901 * aarch64-opc-2.c: Regenerate.
902 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
903 (ins_sve_addr_ri_s9xvl): New inserters.
904 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
905 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
906 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
907 * aarch64-asm-2.c: Regenerate.
908 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
909 (ext_sve_addr_ri_s9xvl): New extractors.
910 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
911 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
912 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
913 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
914 * aarch64-dis-2.c: Regenerate.
916 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
918 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
920 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
921 (FLD_SVE_xs_22): New aarch64_field_kinds.
922 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
923 (get_operand_specific_data): New function.
924 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
925 FLD_SVE_xs_14 and FLD_SVE_xs_22.
926 (operand_general_constraint_met_p): Handle the new SVE address
928 (sve_reg): New array.
929 (get_addr_sve_reg_name): New function.
930 (aarch64_print_operand): Handle the new SVE address operands.
931 * aarch64-opc-2.c: Regenerate.
932 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
933 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
934 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
935 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
936 (aarch64_ins_sve_addr_rr_lsl): Likewise.
937 (aarch64_ins_sve_addr_rz_xtw): Likewise.
938 (aarch64_ins_sve_addr_zi_u5): Likewise.
939 (aarch64_ins_sve_addr_zz): Likewise.
940 (aarch64_ins_sve_addr_zz_lsl): Likewise.
941 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
942 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
943 * aarch64-asm-2.c: Regenerate.
944 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
945 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
946 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
947 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
948 (aarch64_ext_sve_addr_ri_u6): Likewise.
949 (aarch64_ext_sve_addr_rr_lsl): Likewise.
950 (aarch64_ext_sve_addr_rz_xtw): Likewise.
951 (aarch64_ext_sve_addr_zi_u5): Likewise.
952 (aarch64_ext_sve_addr_zz): Likewise.
953 (aarch64_ext_sve_addr_zz_lsl): Likewise.
954 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
955 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
956 * aarch64-dis-2.c: Regenerate.
958 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
960 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
961 AARCH64_OPND_SVE_PATTERN_SCALED.
962 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
963 * aarch64-opc.c (fields): Add a corresponding entry.
964 (set_multiplier_out_of_range_error): New function.
965 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
966 (operand_general_constraint_met_p): Handle
967 AARCH64_OPND_SVE_PATTERN_SCALED.
968 (print_register_offset_address): Use PRIi64 to print the
970 (aarch64_print_operand): Likewise. Handle
971 AARCH64_OPND_SVE_PATTERN_SCALED.
972 * aarch64-opc-2.c: Regenerate.
973 * aarch64-asm.h (ins_sve_scale): New inserter.
974 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
975 * aarch64-asm-2.c: Regenerate.
976 * aarch64-dis.h (ext_sve_scale): New inserter.
977 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
978 * aarch64-dis-2.c: Regenerate.
980 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
982 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
983 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
984 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
985 (FLD_SVE_prfop): Likewise.
986 * aarch64-opc.c: Include libiberty.h.
987 (aarch64_sve_pattern_array): New variable.
988 (aarch64_sve_prfop_array): Likewise.
989 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
990 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
991 AARCH64_OPND_SVE_PRFOP.
992 * aarch64-asm-2.c: Regenerate.
993 * aarch64-dis-2.c: Likewise.
994 * aarch64-opc-2.c: Likewise.
996 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
998 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
999 AARCH64_OPND_QLF_P_[ZM].
1000 (aarch64_print_operand): Print /z and /m where appropriate.
1002 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1004 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
1005 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
1006 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
1007 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
1008 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
1009 * aarch64-opc.c (fields): Add corresponding entries here.
1010 (operand_general_constraint_met_p): Check that SVE register lists
1011 have the correct length. Check the ranges of SVE index registers.
1012 Check for cases where p8-p15 are used in 3-bit predicate fields.
1013 (aarch64_print_operand): Handle the new SVE operands.
1014 * aarch64-opc-2.c: Regenerate.
1015 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
1016 * aarch64-asm.c (aarch64_ins_sve_index): New function.
1017 (aarch64_ins_sve_reglist): Likewise.
1018 * aarch64-asm-2.c: Regenerate.
1019 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
1020 * aarch64-dis.c (aarch64_ext_sve_index): New function.
1021 (aarch64_ext_sve_reglist): Likewise.
1022 * aarch64-dis-2.c: Regenerate.
1024 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1026 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
1027 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
1028 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
1029 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
1032 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1034 * aarch64-opc.c (get_offset_int_reg_name): New function.
1035 (print_immediate_offset_address): Likewise.
1036 (print_register_offset_address): Take the base and offset
1037 registers as parameters.
1038 (aarch64_print_operand): Update caller accordingly. Use
1039 print_immediate_offset_address.
1041 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1043 * aarch64-opc.c (BANK): New macro.
1044 (R32, R64): Take a register number as argument
1045 (int_reg): Use BANK.
1047 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1049 * aarch64-opc.c (print_register_list): Add a prefix parameter.
1050 (aarch64_print_operand): Update accordingly.
1052 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1054 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
1056 * aarch64-asm.h (ins_fpimm): New inserter.
1057 * aarch64-asm.c (aarch64_ins_fpimm): New function.
1058 * aarch64-asm-2.c: Regenerate.
1059 * aarch64-dis.h (ext_fpimm): New extractor.
1060 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
1061 (aarch64_ext_fpimm): New function.
1062 * aarch64-dis-2.c: Regenerate.
1064 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1066 * aarch64-asm.c: Include libiberty.h.
1067 (insert_fields): New function.
1068 (aarch64_ins_imm): Use it.
1069 * aarch64-dis.c (extract_fields): New function.
1070 (aarch64_ext_imm): Use it.
1072 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1074 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
1075 with an esize parameter.
1076 (operand_general_constraint_met_p): Update accordingly.
1077 Fix misindented code.
1078 * aarch64-asm.c (aarch64_ins_limm): Update call to
1079 aarch64_logical_immediate_p.
1081 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1083 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
1085 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1087 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
1089 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
1091 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
1093 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
1095 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
1096 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
1097 xor3>: Delete mnemonics.
1098 <cp_abort>: Rename mnemonic from ...
1099 <cpabort>: ...to this.
1100 <setb>: Change to a X form instruction.
1101 <sync>: Change to 1 operand form.
1102 <copy>: Delete mnemonic.
1103 <copy_first>: Rename mnemonic from ...
1105 <paste, paste.>: Delete mnemonics.
1106 <paste_last>: Rename mnemonic from ...
1107 <paste.>: ...to this.
1109 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
1111 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
1113 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1115 * s390-mkopc.c (main): Support alternate arch strings.
1117 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
1119 * s390-opc.txt: Fix kmctr instruction type.
1121 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
1123 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
1124 * i386-init.h: Regenerated.
1126 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
1128 * opcodes/arc-dis.c (print_insn_arc): Changed.
1130 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
1132 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1135 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
1137 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
1138 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1139 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1141 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
1143 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1144 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1145 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1146 PREFIX_MOD_3_0FAE_REG_4.
1147 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1148 PREFIX_MOD_3_0FAE_REG_4.
1149 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1150 (cpu_flags): Add CpuPTWRITE.
1151 * i386-opc.h (CpuPTWRITE): New.
1152 (i386_cpu_flags): Add cpuptwrite.
1153 * i386-opc.tbl: Add ptwrite instruction.
1154 * i386-init.h: Regenerated.
1155 * i386-tbl.h: Likewise.
1157 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
1159 * arc-dis.h: Wrap around in extern "C".
1161 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1163 * aarch64-tbl.h (V8_2_INSN): New macro.
1164 (aarch64_opcode_table): Use it.
1166 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1168 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1169 CORE_INSN, __FP_INSN and SIMD_INSN.
1171 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1173 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1174 (aarch64_opcode_table): Update uses accordingly.
1176 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
1177 Kwok Cheung Yeung <kcy@codesourcery.com>
1180 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1181 'e_cmplwi' to 'e_cmpli' instead.
1182 (OPVUPRT, OPVUPRT_MASK): Define.
1183 (powerpc_opcodes): Add E200Z4 insns.
1184 (vle_opcodes): Add context save/restore insns.
1186 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
1188 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1189 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1192 2016-07-27 Graham Markall <graham.markall@embecosm.com>
1194 * arc-nps400-tbl.h: Change block comments to GNU format.
1195 * arc-dis.c: Add new globals addrtypenames,
1196 addrtypenames_max, and addtypeunknown.
1197 (get_addrtype): New function.
1198 (print_insn_arc): Print colons and address types when
1200 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1201 define insert and extract functions for all address types.
1202 (arc_operands): Add operands for colon and all address
1204 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1205 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1206 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1207 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1208 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1209 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1211 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
1213 * configure: Regenerated.
1215 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
1217 * arc-dis.c (skipclass): New structure.
1218 (decodelist): New variable.
1219 (is_compatible_p): New function.
1220 (new_element): Likewise.
1221 (skip_class_p): Likewise.
1222 (find_format_from_table): Use skip_class_p function.
1223 (find_format): Decode first the extension instructions.
1224 (print_insn_arc): Select either ARCEM or ARCHS based on elf
1226 (parse_option): New function.
1227 (parse_disassembler_options): Likewise.
1228 (print_arc_disassembler_options): Likewise.
1229 (print_insn_arc): Use parse_disassembler_options function. Proper
1230 select ARCv2 cpu variant.
1231 * disassemble.c (disassembler_usage): Add ARC disassembler
1234 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1236 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1237 annotation from the "nal" entry and reorder it beyond "bltzal".
1239 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1241 * sparc-opc.c (ldtxa): New macro.
1242 (sparc_opcodes): Use the macro defined above to add entries for
1243 the LDTXA instructions.
1244 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1247 2016-07-07 James Bowman <james.bowman@ftdichip.com>
1249 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1252 2016-07-01 Jan Beulich <jbeulich@suse.com>
1254 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1255 (movzb): Adjust to cover all permitted suffixes.
1257 * i386-tbl.h: Re-generate.
1259 2016-07-01 Jan Beulich <jbeulich@suse.com>
1261 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1262 (lgdt): Remove Tbyte from non-64-bit variant.
1263 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1264 xsaves64, xsavec64): Remove Disp16.
1265 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1266 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1268 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1269 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1270 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1272 * i386-tbl.h: Re-generate.
1274 2016-07-01 Jan Beulich <jbeulich@suse.com>
1276 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1277 * i386-tbl.h: Re-generate.
1279 2016-06-30 Yao Qi <yao.qi@linaro.org>
1281 * arm-dis.c (print_insn): Fix typo in comment.
1283 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1285 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1286 range of ldst_elemlist operands.
1287 (print_register_list): Use PRIi64 to print the index.
1288 (aarch64_print_operand): Likewise.
1290 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1292 * mcore-opc.h: Remove sentinal.
1293 * mcore-dis.c (print_insn_mcore): Adjust.
1295 2016-06-23 Graham Markall <graham.markall@embecosm.com>
1297 * arc-opc.c: Correct description of availability of NPS400
1300 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1302 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1303 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1304 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1305 xor3>: New mnemonics.
1306 <setb>: Change to a VX form instruction.
1307 (insert_sh6): Add support for rldixor.
1308 (extract_sh6): Likewise.
1310 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1312 * arc-ext.h: Wrap in extern C.
1314 2016-06-21 Graham Markall <graham.markall@embecosm.com>
1316 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1317 Use same method for determining instruction length on ARC700 and
1319 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1320 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1321 with the NPS400 subclass.
1322 * arc-opc.c: Likewise.
1324 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1326 * sparc-opc.c (rdasr): New macro.
1332 (sparc_opcodes): Use the macros above to fix and expand the
1333 definition of read/write instructions from/to
1334 asr/privileged/hyperprivileged instructions.
1335 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1336 %hva_mask_nz. Prefer softint_set and softint_clear over
1337 set_softint and clear_softint.
1338 (print_insn_sparc): Support %ver in Rd.
1340 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1342 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1343 architecture according to the hardware capabilities they require.
1345 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1347 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1348 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1349 bfd_mach_sparc_v9{c,d,e,v,m}.
1350 * sparc-opc.c (MASK_V9C): Define.
1351 (MASK_V9D): Likewise.
1352 (MASK_V9E): Likewise.
1353 (MASK_V9V): Likewise.
1354 (MASK_V9M): Likewise.
1355 (v6): Add MASK_V9{C,D,E,V,M}.
1356 (v6notlet): Likewise.
1360 (v9andleon): Likewise.
1368 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1370 2016-06-15 Nick Clifton <nickc@redhat.com>
1372 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1373 constants to match expected behaviour.
1374 (nds32_parse_opcode): Likewise. Also for whitespace.
1376 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1378 * arc-opc.c (extract_rhv1): Extract value from insn.
1380 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1382 * arc-nps400-tbl.h: Add ldbit instruction.
1383 * arc-opc.c: Add flag classes required for ldbit.
1385 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1387 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1388 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1389 support the above instructions.
1391 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1393 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1394 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1395 csma, cbba, zncv, and hofs.
1396 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1397 support the above instructions.
1399 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1401 * arc-nps400-tbl.h: Add andab and orab instructions.
1403 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1405 * arc-nps400-tbl.h: Add addl-like instructions.
1407 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1409 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1411 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1413 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1416 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1418 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1420 (init_disasm): Handle new command line option "insnlength".
1421 (print_s390_disassembler_options): Mention new option in help
1423 (print_insn_s390): Use the encoded insn length when dumping
1424 unknown instructions.
1426 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1428 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1429 to the address and set as symbol address for LDS/ STS immediate operands.
1431 2016-06-07 Alan Modra <amodra@gmail.com>
1433 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1434 cpu for "vle" to e500.
1435 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1436 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1437 (PPCNONE): Delete, substitute throughout.
1438 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1439 except for major opcode 4 and 31.
1440 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1442 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1444 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1445 ARM_EXT_RAS in relevant entries.
1447 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1450 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1453 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1456 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1457 (indir_v_mode): New.
1458 Add comments for '&'.
1459 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1460 (putop): Handle '&'.
1461 (intel_operand_size): Handle indir_v_mode.
1462 (OP_E_register): Likewise.
1463 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1464 64-bit indirect call/jmp for AMD64.
1465 * i386-tbl.h: Regenerated
1467 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1469 * arc-dis.c (struct arc_operand_iterator): New structure.
1470 (find_format_from_table): All the old content from find_format,
1471 with some minor adjustments, and parameter renaming.
1472 (find_format_long_instructions): New function.
1473 (find_format): Rewritten.
1474 (arc_insn_length): Add LSB parameter.
1475 (extract_operand_value): New function.
1476 (operand_iterator_next): New function.
1477 (print_insn_arc): Use new functions to find opcode, and iterator
1479 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1480 (extract_nps_3bit_dst_short): New function.
1481 (insert_nps_3bit_src2_short): New function.
1482 (extract_nps_3bit_src2_short): New function.
1483 (insert_nps_bitop1_size): New function.
1484 (extract_nps_bitop1_size): New function.
1485 (insert_nps_bitop2_size): New function.
1486 (extract_nps_bitop2_size): New function.
1487 (insert_nps_bitop_mod4_msb): New function.
1488 (extract_nps_bitop_mod4_msb): New function.
1489 (insert_nps_bitop_mod4_lsb): New function.
1490 (extract_nps_bitop_mod4_lsb): New function.
1491 (insert_nps_bitop_dst_pos3_pos4): New function.
1492 (extract_nps_bitop_dst_pos3_pos4): New function.
1493 (insert_nps_bitop_ins_ext): New function.
1494 (extract_nps_bitop_ins_ext): New function.
1495 (arc_operands): Add new operands.
1496 (arc_long_opcodes): New global array.
1497 (arc_num_long_opcodes): New global.
1498 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1500 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1502 * nds32-asm.h: Add extern "C".
1503 * sh-opc.h: Likewise.
1505 2016-06-01 Graham Markall <graham.markall@embecosm.com>
1507 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1508 0,b,limm to the rflt instruction.
1510 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1512 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1515 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1518 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1519 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1520 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1521 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1522 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1523 * i386-init.h: Regenerated.
1525 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1528 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1529 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1530 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1531 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1532 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1533 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1534 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1535 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1536 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1537 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1538 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1539 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1540 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1541 CpuRegMask for AVX512.
1542 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1544 (set_bitfield_from_cpu_flag_init): New function.
1545 (set_bitfield): Remove const on f. Call
1546 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1547 * i386-opc.h (CpuRegMMX): New.
1548 (CpuRegXMM): Likewise.
1549 (CpuRegYMM): Likewise.
1550 (CpuRegZMM): Likewise.
1551 (CpuRegMask): Likewise.
1552 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1554 * i386-init.h: Regenerated.
1555 * i386-tbl.h: Likewise.
1557 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1560 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1561 (opcode_modifiers): Add AMD64 and Intel64.
1562 (main): Properly verify CpuMax.
1563 * i386-opc.h (CpuAMD64): Removed.
1564 (CpuIntel64): Likewise.
1565 (CpuMax): Set to CpuNo64.
1566 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1568 (Intel64): Likewise.
1569 (i386_opcode_modifier): Add amd64 and intel64.
1570 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1572 * i386-init.h: Regenerated.
1573 * i386-tbl.h: Likewise.
1575 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1578 * i386-gen.c (main): Fail if CpuMax is incorrect.
1579 * i386-opc.h (CpuMax): Set to CpuIntel64.
1580 * i386-tbl.h: Regenerated.
1582 2016-05-27 Nick Clifton <nickc@redhat.com>
1585 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1586 (msp430dis_opcode_unsigned): New function.
1587 (msp430dis_opcode_signed): New function.
1588 (msp430_singleoperand): Use the new opcode reading functions.
1589 Only disassenmble bytes if they were successfully read.
1590 (msp430_doubleoperand): Likewise.
1591 (msp430_branchinstr): Likewise.
1592 (msp430x_callx_instr): Likewise.
1593 (print_insn_msp430): Check that it is safe to read bytes before
1594 attempting disassembly. Use the new opcode reading functions.
1596 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1598 * ppc-opc.c (CY): New define. Document it.
1599 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1601 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1603 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1604 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1605 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1606 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1608 * i386-init.h: Regenerated.
1610 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1613 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1614 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1615 * i386-init.h: Regenerated.
1617 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1619 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1620 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1621 * i386-init.h: Regenerated.
1623 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1625 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1627 (print_insn_arc): Set insn_type information.
1628 * arc-opc.c (C_CC): Add F_CLASS_COND.
1629 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1630 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1631 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1632 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1633 (brne, brne_s, jeq_s, jne_s): Likewise.
1635 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1637 * arc-tbl.h (neg): New instruction variant.
1639 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1641 * arc-dis.c (find_format, find_format, get_auxreg)
1642 (print_insn_arc): Changed.
1643 * arc-ext.h (INSERT_XOP): Likewise.
1645 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1647 * tic54x-dis.c (sprint_mmr): Adjust.
1648 * tic54x-opc.c: Likewise.
1650 2016-05-19 Alan Modra <amodra@gmail.com>
1652 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1654 2016-05-19 Alan Modra <amodra@gmail.com>
1656 * ppc-opc.c: Formatting.
1657 (NSISIGNOPT): Define.
1658 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1660 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1662 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1663 replacing references to `micromips_ase' throughout.
1664 (_print_insn_mips): Don't use file-level microMIPS annotation to
1665 determine the disassembly mode with the symbol table.
1667 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1669 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1671 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1673 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1675 * mips-opc.c (D34): New macro.
1676 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1678 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1680 * i386-dis.c (prefix_table): Add RDPID instruction.
1681 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1682 (cpu_flags): Add RDPID bitfield.
1683 * i386-opc.h (enum): Add RDPID element.
1684 (i386_cpu_flags): Add RDPID field.
1685 * i386-opc.tbl: Add RDPID instruction.
1686 * i386-init.h: Regenerate.
1687 * i386-tbl.h: Regenerate.
1689 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1691 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1692 branch type of a symbol.
1693 (print_insn): Likewise.
1695 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1697 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1698 Mainline Security Extensions instructions.
1699 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1700 Extensions instructions.
1701 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1703 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1706 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1708 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1710 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1712 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1713 (arcExtMap_genOpcode): Likewise.
1714 * arc-opc.c (arg_32bit_rc): Define new variable.
1715 (arg_32bit_u6): Likewise.
1716 (arg_32bit_limm): Likewise.
1718 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1720 * aarch64-gen.c (VERIFIER): Define.
1721 * aarch64-opc.c (VERIFIER): Define.
1722 (verify_ldpsw): Use static linkage.
1723 * aarch64-opc.h (verify_ldpsw): Remove.
1724 * aarch64-tbl.h: Use VERIFIER for verifiers.
1726 2016-04-28 Nick Clifton <nickc@redhat.com>
1729 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1730 * aarch64-opc.c (verify_ldpsw): New function.
1731 * aarch64-opc.h (verify_ldpsw): New prototype.
1732 * aarch64-tbl.h: Add initialiser for verifier field.
1733 (LDPSW): Set verifier to verify_ldpsw.
1735 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1739 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1740 smaller than address size.
1742 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1744 * alpha-dis.c: Regenerate.
1745 * crx-dis.c: Likewise.
1746 * disassemble.c: Likewise.
1747 * epiphany-opc.c: Likewise.
1748 * fr30-opc.c: Likewise.
1749 * frv-opc.c: Likewise.
1750 * ip2k-opc.c: Likewise.
1751 * iq2000-opc.c: Likewise.
1752 * lm32-opc.c: Likewise.
1753 * lm32-opinst.c: Likewise.
1754 * m32c-opc.c: Likewise.
1755 * m32r-opc.c: Likewise.
1756 * m32r-opinst.c: Likewise.
1757 * mep-opc.c: Likewise.
1758 * mt-opc.c: Likewise.
1759 * or1k-opc.c: Likewise.
1760 * or1k-opinst.c: Likewise.
1761 * tic80-opc.c: Likewise.
1762 * xc16x-opc.c: Likewise.
1763 * xstormy16-opc.c: Likewise.
1765 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1767 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1768 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1769 calcsd, and calcxd instructions.
1770 * arc-opc.c (insert_nps_bitop_size): Delete.
1771 (extract_nps_bitop_size): Delete.
1772 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1773 (extract_nps_qcmp_m3): Define.
1774 (extract_nps_qcmp_m2): Define.
1775 (extract_nps_qcmp_m1): Define.
1776 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1777 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1778 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1779 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1780 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1783 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1785 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1787 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1789 * Makefile.in: Regenerated with automake 1.11.6.
1790 * aclocal.m4: Likewise.
1792 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1794 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1796 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1797 (extract_nps_cmem_uimm16): New function.
1798 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1800 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1802 * arc-dis.c (arc_insn_length): New function.
1803 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1804 (find_format): Change insnLen parameter to unsigned.
1806 2016-04-13 Nick Clifton <nickc@redhat.com>
1809 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1810 the LD.B and LD.BU instructions.
1812 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1814 * arc-dis.c (find_format): Check for extension flags.
1815 (print_flags): New function.
1816 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1818 * arc-ext.c (arcExtMap_coreRegName): Use
1819 LAST_EXTENSION_CORE_REGISTER.
1820 (arcExtMap_coreReadWrite): Likewise.
1821 (dump_ARC_extmap): Update printing.
1822 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1823 (arc_aux_regs): Add cpu field.
1824 * arc-regs.h: Add cpu field, lower case name aux registers.
1826 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1828 * arc-tbl.h: Add rtsc, sleep with no arguments.
1830 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1832 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1834 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1835 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1836 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1837 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1838 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1839 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1840 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1841 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1842 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1843 (arc_opcode arc_opcodes): Null terminate the array.
1844 (arc_num_opcodes): Remove.
1845 * arc-ext.h (INSERT_XOP): Define.
1846 (extInstruction_t): Likewise.
1847 (arcExtMap_instName): Delete.
1848 (arcExtMap_insn): New function.
1849 (arcExtMap_genOpcode): Likewise.
1850 * arc-ext.c (ExtInstruction): Remove.
1851 (create_map): Zero initialize instruction fields.
1852 (arcExtMap_instName): Remove.
1853 (arcExtMap_insn): New function.
1854 (dump_ARC_extmap): More info while debuging.
1855 (arcExtMap_genOpcode): New function.
1856 * arc-dis.c (find_format): New function.
1857 (print_insn_arc): Use find_format.
1858 (arc_get_disassembler): Enable dump_ARC_extmap only when
1861 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1863 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1864 instruction bits out.
1866 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1868 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1869 * arc-opc.c (arc_flag_operands): Add new flags.
1870 (arc_flag_classes): Add new classes.
1872 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1874 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1876 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1878 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1879 encode1, rflt, crc16, and crc32 instructions.
1880 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1881 (arc_flag_classes): Add C_NPS_R.
1882 (insert_nps_bitop_size_2b): New function.
1883 (extract_nps_bitop_size_2b): Likewise.
1884 (insert_nps_bitop_uimm8): Likewise.
1885 (extract_nps_bitop_uimm8): Likewise.
1886 (arc_operands): Add new operand entries.
1888 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1890 * arc-regs.h: Add a new subclass field. Add double assist
1891 accumulator register values.
1892 * arc-tbl.h: Use DPA subclass to mark the double assist
1893 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1894 * arc-opc.c (RSP): Define instead of SP.
1895 (arc_aux_regs): Add the subclass field.
1897 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1899 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1901 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1903 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1906 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1908 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1909 issues. No functional changes.
1911 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1913 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1914 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1915 (RTT): Remove duplicate.
1916 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1917 (PCT_CONFIG*): Remove.
1918 (D1L, D1H, D2H, D2L): Define.
1920 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1922 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1924 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1926 * arc-tbl.h (invld07): Remove.
1927 * arc-ext-tbl.h: New file.
1928 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1929 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1931 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1933 Fix -Wstack-usage warnings.
1934 * aarch64-dis.c (print_operands): Substitute size.
1935 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1937 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1939 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1940 to get a proper diagnostic when an invalid ASR register is used.
1942 2016-03-22 Nick Clifton <nickc@redhat.com>
1944 * configure: Regenerate.
1946 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1948 * arc-nps400-tbl.h: New file.
1949 * arc-opc.c: Add top level comment.
1950 (insert_nps_3bit_dst): New function.
1951 (extract_nps_3bit_dst): New function.
1952 (insert_nps_3bit_src2): New function.
1953 (extract_nps_3bit_src2): New function.
1954 (insert_nps_bitop_size): New function.
1955 (extract_nps_bitop_size): New function.
1956 (arc_flag_operands): Add nps400 entries.
1957 (arc_flag_classes): Add nps400 entries.
1958 (arc_operands): Add nps400 entries.
1959 (arc_opcodes): Add nps400 include.
1961 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1963 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1964 the new class enum values.
1966 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1968 * arc-dis.c (print_insn_arc): Handle nps400.
1970 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1972 * arc-opc.c (BASE): Delete.
1974 2016-03-18 Nick Clifton <nickc@redhat.com>
1977 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1978 of MOV insn that aliases an ORR insn.
1980 2016-03-16 Jiong Wang <jiong.wang@arm.com>
1982 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1984 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1986 * mcore-opc.h: Add const qualifiers.
1987 * microblaze-opc.h (struct op_code_struct): Likewise.
1988 * sh-opc.h: Likewise.
1989 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1990 (tic4x_print_op): Likewise.
1992 2016-03-02 Alan Modra <amodra@gmail.com>
1994 * or1k-desc.h: Regenerate.
1995 * fr30-ibld.c: Regenerate.
1996 * rl78-decode.c: Regenerate.
1998 2016-03-01 Nick Clifton <nickc@redhat.com>
2001 * rl78-dis.c (print_insn_rl78_common): Fix typo.
2003 2016-02-24 Renlin Li <renlin.li@arm.com>
2005 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
2006 (print_insn_coprocessor): Support fp16 instructions.
2008 2016-02-24 Renlin Li <renlin.li@arm.com>
2010 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
2011 vminnm, vrint(mpna).
2013 2016-02-24 Renlin Li <renlin.li@arm.com>
2015 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
2016 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
2018 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
2020 * i386-dis.c (print_insn): Parenthesize expression to prevent
2021 truncated addresses.
2024 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
2025 Janek van Oirschot <jvanoirs@synopsys.com>
2027 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
2030 2016-02-04 Nick Clifton <nickc@redhat.com>
2033 * msp430-dis.c (print_insn_msp430): Add a special case for
2034 decoding an RRC instruction with the ZC bit set in the extension
2037 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
2039 * cgen-ibld.in (insert_normal): Rework calculation of shift.
2040 * epiphany-ibld.c: Regenerate.
2041 * fr30-ibld.c: Regenerate.
2042 * frv-ibld.c: Regenerate.
2043 * ip2k-ibld.c: Regenerate.
2044 * iq2000-ibld.c: Regenerate.
2045 * lm32-ibld.c: Regenerate.
2046 * m32c-ibld.c: Regenerate.
2047 * m32r-ibld.c: Regenerate.
2048 * mep-ibld.c: Regenerate.
2049 * mt-ibld.c: Regenerate.
2050 * or1k-ibld.c: Regenerate.
2051 * xc16x-ibld.c: Regenerate.
2052 * xstormy16-ibld.c: Regenerate.
2054 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
2056 * epiphany-dis.c: Regenerated from latest cpu files.
2058 2016-02-01 Michael McConville <mmcco@mykolab.com>
2060 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
2063 2016-01-25 Renlin Li <renlin.li@arm.com>
2065 * arm-dis.c (mapping_symbol_for_insn): New function.
2066 (find_ifthen_state): Call mapping_symbol_for_insn().
2068 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
2070 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
2071 of MSR UAO immediate operand.
2073 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
2075 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
2076 instruction support.
2078 2016-01-17 Alan Modra <amodra@gmail.com>
2080 * configure: Regenerate.
2082 2016-01-14 Nick Clifton <nickc@redhat.com>
2084 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
2085 instructions that can support stack pointer operations.
2086 * rl78-decode.c: Regenerate.
2087 * rl78-dis.c: Fix display of stack pointer in MOVW based
2090 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
2092 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
2093 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
2094 erxtatus_el1 and erxaddr_el1.
2096 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
2098 * arm-dis.c (arm_opcodes): Add "esb".
2099 (thumb_opcodes): Likewise.
2101 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
2103 * ppc-opc.c <xscmpnedp>: Delete.
2104 <xvcmpnedp>: Likewise.
2105 <xvcmpnedp.>: Likewise.
2106 <xvcmpnesp>: Likewise.
2107 <xvcmpnesp.>: Likewise.
2109 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
2112 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
2115 2016-01-01 Alan Modra <amodra@gmail.com>
2117 Update year range in copyright notice of all files.
2119 For older changes see ChangeLog-2015
2121 Copyright (C) 2016 Free Software Foundation, Inc.
2123 Copying and distribution of this file, with or without modification,
2124 are permitted in any medium without royalty provided the copyright
2125 notice and this notice are preserved.
2131 version-control: never
projects / deliverable / binutils-gdb.git / blob