1 2018-10-05 Richard Henderson <rth@twiddle.net>
2 Stafford Horne <shorne@gmail.com>
4 * or1k-desc.c: Regenerate.
5 * or1k-desc.h: Regenerate.
6 * or1k-opc.c: Regenerate.
7 * or1k-opc.h: Regenerate.
8 * or1k-opinst.c: Regenerate.
10 2018-10-05 Richard Henderson <rth@twiddle.net>
12 * or1k-asm.c: Regenerated.
13 * or1k-desc.c: Regenerated.
14 * or1k-desc.h: Regenerated.
15 * or1k-dis.c: Regenerated.
16 * or1k-ibld.c: Regenerated.
17 * or1k-opc.c: Regenerated.
18 * or1k-opc.h: Regenerated.
19 * or1k-opinst.c: Regenerated.
21 2018-10-05 Richard Henderson <rth@twiddle.net>
23 * or1k-asm.c: Regenerate.
25 2018-10-03 Tamar Christina <tamar.christina@arm.com>
27 * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
28 * aarch64-dis.c (print_operands): Refactor to take notes.
29 (print_verifier_notes): New.
30 (print_aarch64_insn): Apply constraint verifier.
31 (print_insn_aarch64_word): Update call to print_aarch64_insn.
32 * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
34 2018-10-03 Tamar Christina <tamar.christina@arm.com>
36 * aarch64-opc.c (init_insn_block): New.
37 (verify_constraints, aarch64_is_destructive_by_operands): New.
38 * aarch64-opc.h (verify_constraints): New.
40 2018-10-03 Tamar Christina <tamar.christina@arm.com>
42 * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
43 * aarch64-opc.c (verify_ldpsw): Update arguments.
45 2018-10-03 Tamar Christina <tamar.christina@arm.com>
47 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
48 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
50 2018-10-03 Tamar Christina <tamar.christina@arm.com>
52 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
53 * aarch64-dis.c (insn_sequence): New.
55 2018-10-03 Tamar Christina <tamar.christina@arm.com>
57 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
58 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
59 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
60 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
63 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
65 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
67 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
68 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
69 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
70 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
71 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
72 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
73 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
75 2018-10-02 Palmer Dabbelt <palmer@sifive.com>
77 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
79 2018-09-23 Sandra Loosemore <sandra@codesourcery.com>
81 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
82 are used when extracting signed fields and converting them to
83 potentially 64-bit types.
85 2018-09-21 Simon Marchi <simon.marchi@ericsson.com>
87 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
88 * Makefile.in: Re-generate.
89 * aclocal.m4: Re-generate.
90 * configure: Re-generate.
91 * configure.ac: Remove check for -Wno-missing-field-initializers.
92 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
93 (csky_v2_opcodes): Likewise.
95 2018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
97 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
99 2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
101 * nds32-asm.c (operand_fields): Remove the unused fields.
102 (nds32_opcodes): Remove the unused instructions.
103 * nds32-dis.c (nds32_ex9_info): Removed.
104 (nds32_parse_opcode): Updated.
105 (print_insn_nds32): Likewise.
106 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
107 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
108 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
109 build_opcode_hash_table): New functions.
110 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
111 nds32_opcode_table): New.
112 (hw_ktabs): Declare it to a pointer rather than an array.
113 (build_hash_table): Removed.
114 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
115 SYN_ROPT and upadte HW_GPR and HW_INT.
116 * nds32-dis.c (keywords): Remove const.
117 (match_field): New function.
118 (nds32_parse_opcode): Updated.
119 * disassemble.c (disassemble_init_for_target):
120 Add disassemble_init_nds32.
121 * nds32-dis.c (eum map_type): New.
122 (nds32_private_data): Likewise.
123 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
124 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
125 (print_insn_nds32): Updated.
126 * nds32-asm.c (parse_aext_reg): Add new parameter.
127 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
130 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
131 (operand_fields): Add new fields.
132 (nds32_opcodes): Add new instructions.
133 (keyword_aridxi_mx): New keyword.
134 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
136 (ALU2_1, ALU2_2, ALU2_3): New macros.
137 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
139 2018-09-17 Kito Cheng <kito@andestech.com>
141 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
143 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
146 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
147 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
148 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
149 (EVEX_LEN_0F7E_P_1): Likewise.
150 (EVEX_LEN_0F7E_P_2): Likewise.
151 (EVEX_LEN_0FD6_P_2): Likewise.
152 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
153 (EVEX_LEN_TABLE): Likewise.
154 (EVEX_LEN_0F6E_P_2): New enum.
155 (EVEX_LEN_0F7E_P_1): Likewise.
156 (EVEX_LEN_0F7E_P_2): Likewise.
157 (EVEX_LEN_0FD6_P_2): Likewise.
158 (evex_len_table): New.
159 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
160 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
161 * i386-tbl.h: Regenerated.
163 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
166 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
167 VEX_LEN_0F7E_P_2 entries.
168 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
169 * i386-tbl.h: Regenerated.
171 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
173 * i386-dis.c (VZERO_Fixup): Removed.
175 (VEX_LEN_0F10_P_1): Likewise.
176 (VEX_LEN_0F10_P_3): Likewise.
177 (VEX_LEN_0F11_P_1): Likewise.
178 (VEX_LEN_0F11_P_3): Likewise.
179 (VEX_LEN_0F2E_P_0): Likewise.
180 (VEX_LEN_0F2E_P_2): Likewise.
181 (VEX_LEN_0F2F_P_0): Likewise.
182 (VEX_LEN_0F2F_P_2): Likewise.
183 (VEX_LEN_0F51_P_1): Likewise.
184 (VEX_LEN_0F51_P_3): Likewise.
185 (VEX_LEN_0F52_P_1): Likewise.
186 (VEX_LEN_0F53_P_1): Likewise.
187 (VEX_LEN_0F58_P_1): Likewise.
188 (VEX_LEN_0F58_P_3): Likewise.
189 (VEX_LEN_0F59_P_1): Likewise.
190 (VEX_LEN_0F59_P_3): Likewise.
191 (VEX_LEN_0F5A_P_1): Likewise.
192 (VEX_LEN_0F5A_P_3): Likewise.
193 (VEX_LEN_0F5C_P_1): Likewise.
194 (VEX_LEN_0F5C_P_3): Likewise.
195 (VEX_LEN_0F5D_P_1): Likewise.
196 (VEX_LEN_0F5D_P_3): Likewise.
197 (VEX_LEN_0F5E_P_1): Likewise.
198 (VEX_LEN_0F5E_P_3): Likewise.
199 (VEX_LEN_0F5F_P_1): Likewise.
200 (VEX_LEN_0F5F_P_3): Likewise.
201 (VEX_LEN_0FC2_P_1): Likewise.
202 (VEX_LEN_0FC2_P_3): Likewise.
203 (VEX_LEN_0F3A0A_P_2): Likewise.
204 (VEX_LEN_0F3A0B_P_2): Likewise.
205 (VEX_W_0F10_P_0): Likewise.
206 (VEX_W_0F10_P_1): Likewise.
207 (VEX_W_0F10_P_2): Likewise.
208 (VEX_W_0F10_P_3): Likewise.
209 (VEX_W_0F11_P_0): Likewise.
210 (VEX_W_0F11_P_1): Likewise.
211 (VEX_W_0F11_P_2): Likewise.
212 (VEX_W_0F11_P_3): Likewise.
213 (VEX_W_0F12_P_0_M_0): Likewise.
214 (VEX_W_0F12_P_0_M_1): Likewise.
215 (VEX_W_0F12_P_1): Likewise.
216 (VEX_W_0F12_P_2): Likewise.
217 (VEX_W_0F12_P_3): Likewise.
218 (VEX_W_0F13_M_0): Likewise.
219 (VEX_W_0F14): Likewise.
220 (VEX_W_0F15): Likewise.
221 (VEX_W_0F16_P_0_M_0): Likewise.
222 (VEX_W_0F16_P_0_M_1): Likewise.
223 (VEX_W_0F16_P_1): Likewise.
224 (VEX_W_0F16_P_2): Likewise.
225 (VEX_W_0F17_M_0): Likewise.
226 (VEX_W_0F28): Likewise.
227 (VEX_W_0F29): Likewise.
228 (VEX_W_0F2B_M_0): Likewise.
229 (VEX_W_0F2E_P_0): Likewise.
230 (VEX_W_0F2E_P_2): Likewise.
231 (VEX_W_0F2F_P_0): Likewise.
232 (VEX_W_0F2F_P_2): Likewise.
233 (VEX_W_0F50_M_0): Likewise.
234 (VEX_W_0F51_P_0): Likewise.
235 (VEX_W_0F51_P_1): Likewise.
236 (VEX_W_0F51_P_2): Likewise.
237 (VEX_W_0F51_P_3): Likewise.
238 (VEX_W_0F52_P_0): Likewise.
239 (VEX_W_0F52_P_1): Likewise.
240 (VEX_W_0F53_P_0): Likewise.
241 (VEX_W_0F53_P_1): Likewise.
242 (VEX_W_0F58_P_0): Likewise.
243 (VEX_W_0F58_P_1): Likewise.
244 (VEX_W_0F58_P_2): Likewise.
245 (VEX_W_0F58_P_3): Likewise.
246 (VEX_W_0F59_P_0): Likewise.
247 (VEX_W_0F59_P_1): Likewise.
248 (VEX_W_0F59_P_2): Likewise.
249 (VEX_W_0F59_P_3): Likewise.
250 (VEX_W_0F5A_P_0): Likewise.
251 (VEX_W_0F5A_P_1): Likewise.
252 (VEX_W_0F5A_P_3): Likewise.
253 (VEX_W_0F5B_P_0): Likewise.
254 (VEX_W_0F5B_P_1): Likewise.
255 (VEX_W_0F5B_P_2): Likewise.
256 (VEX_W_0F5C_P_0): Likewise.
257 (VEX_W_0F5C_P_1): Likewise.
258 (VEX_W_0F5C_P_2): Likewise.
259 (VEX_W_0F5C_P_3): Likewise.
260 (VEX_W_0F5D_P_0): Likewise.
261 (VEX_W_0F5D_P_1): Likewise.
262 (VEX_W_0F5D_P_2): Likewise.
263 (VEX_W_0F5D_P_3): Likewise.
264 (VEX_W_0F5E_P_0): Likewise.
265 (VEX_W_0F5E_P_1): Likewise.
266 (VEX_W_0F5E_P_2): Likewise.
267 (VEX_W_0F5E_P_3): Likewise.
268 (VEX_W_0F5F_P_0): Likewise.
269 (VEX_W_0F5F_P_1): Likewise.
270 (VEX_W_0F5F_P_2): Likewise.
271 (VEX_W_0F5F_P_3): Likewise.
272 (VEX_W_0F60_P_2): Likewise.
273 (VEX_W_0F61_P_2): Likewise.
274 (VEX_W_0F62_P_2): Likewise.
275 (VEX_W_0F63_P_2): Likewise.
276 (VEX_W_0F64_P_2): Likewise.
277 (VEX_W_0F65_P_2): Likewise.
278 (VEX_W_0F66_P_2): Likewise.
279 (VEX_W_0F67_P_2): Likewise.
280 (VEX_W_0F68_P_2): Likewise.
281 (VEX_W_0F69_P_2): Likewise.
282 (VEX_W_0F6A_P_2): Likewise.
283 (VEX_W_0F6B_P_2): Likewise.
284 (VEX_W_0F6C_P_2): Likewise.
285 (VEX_W_0F6D_P_2): Likewise.
286 (VEX_W_0F6F_P_1): Likewise.
287 (VEX_W_0F6F_P_2): Likewise.
288 (VEX_W_0F70_P_1): Likewise.
289 (VEX_W_0F70_P_2): Likewise.
290 (VEX_W_0F70_P_3): Likewise.
291 (VEX_W_0F71_R_2_P_2): Likewise.
292 (VEX_W_0F71_R_4_P_2): Likewise.
293 (VEX_W_0F71_R_6_P_2): Likewise.
294 (VEX_W_0F72_R_2_P_2): Likewise.
295 (VEX_W_0F72_R_4_P_2): Likewise.
296 (VEX_W_0F72_R_6_P_2): Likewise.
297 (VEX_W_0F73_R_2_P_2): Likewise.
298 (VEX_W_0F73_R_3_P_2): Likewise.
299 (VEX_W_0F73_R_6_P_2): Likewise.
300 (VEX_W_0F73_R_7_P_2): Likewise.
301 (VEX_W_0F74_P_2): Likewise.
302 (VEX_W_0F75_P_2): Likewise.
303 (VEX_W_0F76_P_2): Likewise.
304 (VEX_W_0F77_P_0): Likewise.
305 (VEX_W_0F7C_P_2): Likewise.
306 (VEX_W_0F7C_P_3): Likewise.
307 (VEX_W_0F7D_P_2): Likewise.
308 (VEX_W_0F7D_P_3): Likewise.
309 (VEX_W_0F7E_P_1): Likewise.
310 (VEX_W_0F7F_P_1): Likewise.
311 (VEX_W_0F7F_P_2): Likewise.
312 (VEX_W_0FAE_R_2_M_0): Likewise.
313 (VEX_W_0FAE_R_3_M_0): Likewise.
314 (VEX_W_0FC2_P_0): Likewise.
315 (VEX_W_0FC2_P_1): Likewise.
316 (VEX_W_0FC2_P_2): Likewise.
317 (VEX_W_0FC2_P_3): Likewise.
318 (VEX_W_0FD0_P_2): Likewise.
319 (VEX_W_0FD0_P_3): Likewise.
320 (VEX_W_0FD1_P_2): Likewise.
321 (VEX_W_0FD2_P_2): Likewise.
322 (VEX_W_0FD3_P_2): Likewise.
323 (VEX_W_0FD4_P_2): Likewise.
324 (VEX_W_0FD5_P_2): Likewise.
325 (VEX_W_0FD6_P_2): Likewise.
326 (VEX_W_0FD7_P_2_M_1): Likewise.
327 (VEX_W_0FD8_P_2): Likewise.
328 (VEX_W_0FD9_P_2): Likewise.
329 (VEX_W_0FDA_P_2): Likewise.
330 (VEX_W_0FDB_P_2): Likewise.
331 (VEX_W_0FDC_P_2): Likewise.
332 (VEX_W_0FDD_P_2): Likewise.
333 (VEX_W_0FDE_P_2): Likewise.
334 (VEX_W_0FDF_P_2): Likewise.
335 (VEX_W_0FE0_P_2): Likewise.
336 (VEX_W_0FE1_P_2): Likewise.
337 (VEX_W_0FE2_P_2): Likewise.
338 (VEX_W_0FE3_P_2): Likewise.
339 (VEX_W_0FE4_P_2): Likewise.
340 (VEX_W_0FE5_P_2): Likewise.
341 (VEX_W_0FE6_P_1): Likewise.
342 (VEX_W_0FE6_P_2): Likewise.
343 (VEX_W_0FE6_P_3): Likewise.
344 (VEX_W_0FE7_P_2_M_0): Likewise.
345 (VEX_W_0FE8_P_2): Likewise.
346 (VEX_W_0FE9_P_2): Likewise.
347 (VEX_W_0FEA_P_2): Likewise.
348 (VEX_W_0FEB_P_2): Likewise.
349 (VEX_W_0FEC_P_2): Likewise.
350 (VEX_W_0FED_P_2): Likewise.
351 (VEX_W_0FEE_P_2): Likewise.
352 (VEX_W_0FEF_P_2): Likewise.
353 (VEX_W_0FF0_P_3_M_0): Likewise.
354 (VEX_W_0FF1_P_2): Likewise.
355 (VEX_W_0FF2_P_2): Likewise.
356 (VEX_W_0FF3_P_2): Likewise.
357 (VEX_W_0FF4_P_2): Likewise.
358 (VEX_W_0FF5_P_2): Likewise.
359 (VEX_W_0FF6_P_2): Likewise.
360 (VEX_W_0FF7_P_2): Likewise.
361 (VEX_W_0FF8_P_2): Likewise.
362 (VEX_W_0FF9_P_2): Likewise.
363 (VEX_W_0FFA_P_2): Likewise.
364 (VEX_W_0FFB_P_2): Likewise.
365 (VEX_W_0FFC_P_2): Likewise.
366 (VEX_W_0FFD_P_2): Likewise.
367 (VEX_W_0FFE_P_2): Likewise.
368 (VEX_W_0F3800_P_2): Likewise.
369 (VEX_W_0F3801_P_2): Likewise.
370 (VEX_W_0F3802_P_2): Likewise.
371 (VEX_W_0F3803_P_2): Likewise.
372 (VEX_W_0F3804_P_2): Likewise.
373 (VEX_W_0F3805_P_2): Likewise.
374 (VEX_W_0F3806_P_2): Likewise.
375 (VEX_W_0F3807_P_2): Likewise.
376 (VEX_W_0F3808_P_2): Likewise.
377 (VEX_W_0F3809_P_2): Likewise.
378 (VEX_W_0F380A_P_2): Likewise.
379 (VEX_W_0F380B_P_2): Likewise.
380 (VEX_W_0F3817_P_2): Likewise.
381 (VEX_W_0F381C_P_2): Likewise.
382 (VEX_W_0F381D_P_2): Likewise.
383 (VEX_W_0F381E_P_2): Likewise.
384 (VEX_W_0F3820_P_2): Likewise.
385 (VEX_W_0F3821_P_2): Likewise.
386 (VEX_W_0F3822_P_2): Likewise.
387 (VEX_W_0F3823_P_2): Likewise.
388 (VEX_W_0F3824_P_2): Likewise.
389 (VEX_W_0F3825_P_2): Likewise.
390 (VEX_W_0F3828_P_2): Likewise.
391 (VEX_W_0F3829_P_2): Likewise.
392 (VEX_W_0F382A_P_2_M_0): Likewise.
393 (VEX_W_0F382B_P_2): Likewise.
394 (VEX_W_0F3830_P_2): Likewise.
395 (VEX_W_0F3831_P_2): Likewise.
396 (VEX_W_0F3832_P_2): Likewise.
397 (VEX_W_0F3833_P_2): Likewise.
398 (VEX_W_0F3834_P_2): Likewise.
399 (VEX_W_0F3835_P_2): Likewise.
400 (VEX_W_0F3837_P_2): Likewise.
401 (VEX_W_0F3838_P_2): Likewise.
402 (VEX_W_0F3839_P_2): Likewise.
403 (VEX_W_0F383A_P_2): Likewise.
404 (VEX_W_0F383B_P_2): Likewise.
405 (VEX_W_0F383C_P_2): Likewise.
406 (VEX_W_0F383D_P_2): Likewise.
407 (VEX_W_0F383E_P_2): Likewise.
408 (VEX_W_0F383F_P_2): Likewise.
409 (VEX_W_0F3840_P_2): Likewise.
410 (VEX_W_0F3841_P_2): Likewise.
411 (VEX_W_0F38DB_P_2): Likewise.
412 (VEX_W_0F3A08_P_2): Likewise.
413 (VEX_W_0F3A09_P_2): Likewise.
414 (VEX_W_0F3A0A_P_2): Likewise.
415 (VEX_W_0F3A0B_P_2): Likewise.
416 (VEX_W_0F3A0C_P_2): Likewise.
417 (VEX_W_0F3A0D_P_2): Likewise.
418 (VEX_W_0F3A0E_P_2): Likewise.
419 (VEX_W_0F3A0F_P_2): Likewise.
420 (VEX_W_0F3A21_P_2): Likewise.
421 (VEX_W_0F3A40_P_2): Likewise.
422 (VEX_W_0F3A41_P_2): Likewise.
423 (VEX_W_0F3A42_P_2): Likewise.
424 (VEX_W_0F3A62_P_2): Likewise.
425 (VEX_W_0F3A63_P_2): Likewise.
426 (VEX_W_0F3ADF_P_2): Likewise.
427 (VEX_LEN_0F77_P_0): New.
428 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
429 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
430 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
431 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
432 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
433 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
434 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
435 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
436 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
437 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
438 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
439 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
440 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
441 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
442 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
443 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
444 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
445 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
446 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
447 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
448 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
449 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
450 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
451 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
452 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
453 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
454 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
455 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
456 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
457 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
458 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
459 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
460 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
461 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
462 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
463 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
464 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
465 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
466 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
467 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
468 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
469 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
470 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
471 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
472 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
473 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
474 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
475 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
476 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
477 (vex_table): Update VEX 0F28 and 0F29 entries.
478 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
479 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
480 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
481 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
482 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
483 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
484 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
485 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
486 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
487 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
488 VEX_LEN_0F3A0B_P_2 entries.
489 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
490 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
491 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
492 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
493 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
494 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
495 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
496 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
497 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
498 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
499 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
500 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
501 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
502 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
503 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
504 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
505 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
506 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
507 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
508 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
509 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
510 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
511 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
512 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
513 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
514 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
515 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
516 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
517 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
518 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
519 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
520 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
521 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
522 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
523 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
524 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
525 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
526 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
527 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
528 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
529 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
530 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
531 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
532 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
533 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
534 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
535 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
536 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
537 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
538 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
539 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
540 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
541 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
542 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
543 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
544 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
545 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
546 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
547 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
548 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
549 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
550 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
551 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
552 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
553 VEX_W_0F3ADF_P_2 entries.
554 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
555 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
556 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
558 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
560 * i386-opc.tbl (VexWIG): New.
561 Replace VexW=3 with VexWIG.
563 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
565 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
566 * i386-tbl.h: Regenerated.
568 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
571 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
572 VEX_LEN_0FD6_P_2 entries.
573 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
574 * i386-tbl.h: Regenerated.
576 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
579 * i386-opc.h (VEXWIG): New.
580 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
581 * i386-tbl.h: Regenerated.
583 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
586 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
587 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
588 * i386-dis.c (EXxEVexR64): New.
589 (evex_rounding_64_mode): Likewise.
590 (OP_Rounding): Handle evex_rounding_64_mode.
592 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
595 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
596 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
597 * i386-dis.c (Edqa): New.
598 (dqa_mode): Likewise.
599 (intel_operand_size): Handle dqa_mode as m_mode.
600 (OP_E_register): Handle dqa_mode as dq_mode.
601 (OP_E_memory): Set shift for dqa_mode based on address_mode.
603 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
605 * i386-dis.c (OP_E_memory): Reformat.
607 2018-09-14 Jan Beulich <jbeulich@suse.com>
609 * i386-opc.tbl (crc32): Fold byte and word forms.
610 * i386-tbl.h: Re-generate.
612 2018-09-13 H.J. Lu <hongjiu.lu@intel.com>
614 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
615 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
616 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
617 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
618 * i386-tbl.h: Regenerated.
620 2018-09-13 Jan Beulich <jbeulich@suse.com>
622 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
624 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
625 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
626 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
627 * i386-tbl.h: Re-generate.
629 2018-09-13 Jan Beulich <jbeulich@suse.com>
631 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
633 * i386-tbl.h: Re-generate.
635 2018-09-13 Jan Beulich <jbeulich@suse.com>
637 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
639 * i386-tbl.h: Re-generate.
641 2018-09-13 Jan Beulich <jbeulich@suse.com>
643 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
645 * i386-tbl.h: Re-generate.
647 2018-09-13 Jan Beulich <jbeulich@suse.com>
649 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
651 * i386-tbl.h: Re-generate.
653 2018-09-13 Jan Beulich <jbeulich@suse.com>
655 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
657 * i386-tbl.h: Re-generate.
659 2018-09-13 Jan Beulich <jbeulich@suse.com>
661 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
663 * i386-tbl.h: Re-generate.
665 2018-09-13 Jan Beulich <jbeulich@suse.com>
667 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
668 * i386-tbl.h: Re-generate.
670 2018-09-13 Jan Beulich <jbeulich@suse.com>
672 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
673 * i386-tbl.h: Re-generate.
675 2018-09-13 Jan Beulich <jbeulich@suse.com>
677 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
679 * i386-tbl.h: Re-generate.
681 2018-09-13 Jan Beulich <jbeulich@suse.com>
683 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
685 * i386-tbl.h: Re-generate.
687 2018-09-13 Jan Beulich <jbeulich@suse.com>
689 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
690 * i386-tbl.h: Re-generate.
692 2018-09-13 Jan Beulich <jbeulich@suse.com>
694 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
695 * i386-tbl.h: Re-generate.
697 2018-09-13 Jan Beulich <jbeulich@suse.com>
699 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
700 * i386-tbl.h: Re-generate.
702 2018-09-13 Jan Beulich <jbeulich@suse.com>
704 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
706 * i386-tbl.h: Re-generate.
708 2018-09-13 Jan Beulich <jbeulich@suse.com>
710 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
712 * i386-tbl.h: Re-generate.
714 2018-09-13 Jan Beulich <jbeulich@suse.com>
716 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
718 * i386-tbl.h: Re-generate.
720 2018-09-13 Jan Beulich <jbeulich@suse.com>
722 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
723 * i386-tbl.h: Re-generate.
725 2018-09-13 Jan Beulich <jbeulich@suse.com>
727 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
728 * i386-tbl.h: Re-generate.
730 2018-09-13 Jan Beulich <jbeulich@suse.com>
732 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
733 * i386-tbl.h: Re-generate.
735 2018-09-13 Jan Beulich <jbeulich@suse.com>
737 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
738 (vpbroadcastw, rdpid): Drop NoRex64.
739 * i386-tbl.h: Re-generate.
741 2018-09-13 Jan Beulich <jbeulich@suse.com>
743 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
744 store templates, adding D.
745 * i386-tbl.h: Re-generate.
747 2018-09-13 Jan Beulich <jbeulich@suse.com>
749 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
750 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
751 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
752 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
753 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
754 Fold load and store templates where possible, adding D. Drop
755 IgnoreSize where it was pointlessly present. Drop redundant
757 * i386-tbl.h: Re-generate.
759 2018-09-13 Jan Beulich <jbeulich@suse.com>
761 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
762 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
763 (intel_operand_size): Handle v_bndmk_mode.
764 (OP_E_memory): Likewise. Produce (bad) when also riprel.
766 2018-09-08 John Darrington <john@darrington.wattle.id.au>
768 * disassemble.c (ARCH_s12z): Define if ARCH_all.
770 2018-08-31 Kito Cheng <kito@andestech.com>
772 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
773 compressed floating point instructions.
775 2018-08-30 Kito Cheng <kito@andestech.com>
777 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
778 riscv_opcode.xlen_requirement.
779 * riscv-opc.c (riscv_opcodes): Update for struct change.
781 2018-08-29 Martin Aberg <maberg@gaisler.com>
783 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
784 psr (PWRPSR) instruction.
786 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
788 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
790 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
792 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
794 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
796 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
797 loongson3a as an alias of gs464 for compatibility.
798 * mips-opc.c (mips_opcodes): Change Comments.
800 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
802 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
804 (print_mips_disassembler_options): Document -M loongson-ext.
805 * mips-opc.c (LEXT2): New macro.
806 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
808 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
810 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
812 (parse_mips_ase_option): Handle -M loongson-ext option.
813 (print_mips_disassembler_options): Document -M loongson-ext.
814 * mips-opc.c (IL3A): Delete.
815 * mips-opc.c (LEXT): New macro.
816 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
819 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
821 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
823 (parse_mips_ase_option): Handle -M loongson-cam option.
824 (print_mips_disassembler_options): Document -M loongson-cam.
825 * mips-opc.c (LCAM): New macro.
826 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
829 2018-08-21 Alan Modra <amodra@gmail.com>
831 * ppc-dis.c (operand_value_powerpc): Init "invalid".
832 (skip_optional_operands): Count optional operands, and update
833 ppc_optional_operand_value call.
834 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
835 (extract_vlensi): Likewise.
836 (extract_fxm): Return default value for missing optional operand.
837 (extract_ls, extract_raq, extract_tbr): Likewise.
838 (insert_sxl, extract_sxl): New functions.
839 (insert_esync, extract_esync): Remove Power9 handling and simplify.
840 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
841 flag and extra entry.
842 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
845 2018-08-20 Alan Modra <amodra@gmail.com>
847 * sh-opc.h (MASK): Simplify.
849 2018-08-18 John Darrington <john@darrington.wattle.id.au>
851 * s12z-dis.c (bm_decode): Deal with cases where the mode is
852 BM_RESERVED0 or BM_RESERVED1
853 (bm_rel_decode, bm_n_bytes): Ditto.
855 2018-08-18 John Darrington <john@darrington.wattle.id.au>
859 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
861 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
862 address with the addr32 prefix and without base nor index
865 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
867 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
868 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
869 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
870 (cpu_flags): Add CpuCMOV and CpuFXSR.
871 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
872 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
873 * i386-init.h: Regenerated.
874 * i386-tbl.h: Likewise.
876 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
878 * arc-regs.h: Update auxiliary registers.
880 2018-08-06 Jan Beulich <jbeulich@suse.com>
882 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
883 (RegIP, RegIZ): Define.
884 * i386-reg.tbl: Adjust comments.
885 (rip): Use Qword instead of BaseIndex. Use RegIP.
886 (eip): Use Dword instead of BaseIndex. Use RegIP.
887 (riz): Add Qword. Use RegIZ.
888 (eiz): Add Dword. Use RegIZ.
889 * i386-tbl.h: Re-generate.
891 2018-08-03 Jan Beulich <jbeulich@suse.com>
893 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
894 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
895 vpmovzxdq, vpmovzxwd): Remove NoRex64.
896 * i386-tbl.h: Re-generate.
898 2018-08-03 Jan Beulich <jbeulich@suse.com>
900 * i386-gen.c (operand_types): Remove Mem field.
901 * i386-opc.h (union i386_operand_type): Remove mem field.
902 * i386-init.h, i386-tbl.h: Re-generate.
904 2018-08-01 Alan Modra <amodra@gmail.com>
906 * po/POTFILES.in: Regenerate.
908 2018-07-31 Nick Clifton <nickc@redhat.com>
910 * po/sv.po: Updated Swedish translation.
912 2018-07-31 Jan Beulich <jbeulich@suse.com>
914 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
915 * i386-init.h, i386-tbl.h: Re-generate.
917 2018-07-31 Jan Beulich <jbeulich@suse.com>
919 * i386-opc.h (ZEROING_MASKING) Rename to ...
920 (DYNAMIC_MASKING): ... this. Adjust comment.
921 * i386-opc.tbl (MaskingMorZ): Define.
922 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
923 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
924 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
925 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
926 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
927 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
928 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
929 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
930 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
932 2018-07-31 Jan Beulich <jbeulich@suse.com>
934 * i386-opc.tbl: Use element rather than vector size for AVX512*
935 scatter/gather insns.
936 * i386-tbl.h: Re-generate.
938 2018-07-31 Jan Beulich <jbeulich@suse.com>
940 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
941 (cpu_flags): Drop CpuVREX.
942 * i386-opc.h (CpuVREX): Delete.
943 (union i386_cpu_flags): Remove cpuvrex.
944 * i386-init.h, i386-tbl.h: Re-generate.
946 2018-07-30 Jim Wilson <jimw@sifive.com>
948 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
950 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
952 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
954 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
955 * Makefile.in: Regenerated.
956 * configure.ac: Add C-SKY.
957 * configure: Regenerated.
958 * csky-dis.c: New file.
959 * csky-opc.h: New file.
960 * disassemble.c (ARCH_csky): Define.
961 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
962 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
964 2018-07-27 Alan Modra <amodra@gmail.com>
966 * ppc-opc.c (insert_sprbat): Correct function parameter and
968 (extract_sprbat): Likewise, variable too.
970 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
971 Alan Modra <amodra@gmail.com>
973 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
974 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
975 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
976 support disjointed BAT.
977 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
978 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
979 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
981 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
982 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
984 * i386-gen.c (adjust_broadcast_modifier): New function.
985 (process_i386_opcode_modifier): Add an argument for operands.
986 Adjust the Broadcast value based on operands.
987 (output_i386_opcode): Pass operand_types to
988 process_i386_opcode_modifier.
989 (process_i386_opcodes): Pass NULL as operands to
990 process_i386_opcode_modifier.
991 * i386-opc.h (BYTE_BROADCAST): New.
992 (WORD_BROADCAST): Likewise.
993 (DWORD_BROADCAST): Likewise.
994 (QWORD_BROADCAST): Likewise.
995 (i386_opcode_modifier): Expand broadcast to 3 bits.
996 * i386-tbl.h: Regenerated.
998 2018-07-24 Alan Modra <amodra@gmail.com>
1001 * or1k-desc.h: Regenerate.
1003 2018-07-24 Jan Beulich <jbeulich@suse.com>
1005 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1006 vcvtusi2ss, and vcvtusi2sd.
1007 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1008 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1009 * i386-tbl.h: Re-generate.
1011 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1013 * arc-opc.c (extract_w6): Fix extending the sign.
1015 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1017 * arc-tbl.h (vewt): Allow it for ARC EM family.
1019 2018-07-23 Alan Modra <amodra@gmail.com>
1022 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1023 opcode variants for mtspr/mfspr encodings.
1025 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
1026 Maciej W. Rozycki <macro@mips.com>
1028 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1029 loongson3a descriptors.
1030 (parse_mips_ase_option): Handle -M loongson-mmi option.
1031 (print_mips_disassembler_options): Document -M loongson-mmi.
1032 * mips-opc.c (LMMI): New macro.
1033 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1036 2018-07-19 Jan Beulich <jbeulich@suse.com>
1038 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1039 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1040 IgnoreSize and [XYZ]MMword where applicable.
1041 * i386-tbl.h: Re-generate.
1043 2018-07-19 Jan Beulich <jbeulich@suse.com>
1045 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1046 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1047 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1048 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1049 * i386-tbl.h: Re-generate.
1051 2018-07-19 Jan Beulich <jbeulich@suse.com>
1053 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1054 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1055 VPCLMULQDQ templates into their respective AVX512VL counterparts
1056 where possible, using Disp8ShiftVL and CheckRegSize instead of
1057 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1058 * i386-tbl.h: Re-generate.
1060 2018-07-19 Jan Beulich <jbeulich@suse.com>
1062 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1063 AVX512VL counterparts where possible, using Disp8ShiftVL and
1064 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1065 IgnoreSize) as appropriate.
1066 * i386-tbl.h: Re-generate.
1068 2018-07-19 Jan Beulich <jbeulich@suse.com>
1070 * i386-opc.tbl: Fold AVX512BW templates into their respective
1071 AVX512VL counterparts where possible, using Disp8ShiftVL and
1072 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1073 IgnoreSize) as appropriate.
1074 * i386-tbl.h: Re-generate.
1076 2018-07-19 Jan Beulich <jbeulich@suse.com>
1078 * i386-opc.tbl: Fold AVX512CD templates into their respective
1079 AVX512VL counterparts where possible, using Disp8ShiftVL and
1080 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1081 IgnoreSize) as appropriate.
1082 * i386-tbl.h: Re-generate.
1084 2018-07-19 Jan Beulich <jbeulich@suse.com>
1086 * i386-opc.h (DISP8_SHIFT_VL): New.
1087 * i386-opc.tbl (Disp8ShiftVL): Define.
1088 (various): Fold AVX512VL templates into their respective
1089 AVX512F counterparts where possible, using Disp8ShiftVL and
1090 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1091 IgnoreSize) as appropriate.
1092 * i386-tbl.h: Re-generate.
1094 2018-07-19 Jan Beulich <jbeulich@suse.com>
1096 * Makefile.am: Change dependencies and rule for
1097 $(srcdir)/i386-init.h.
1098 * Makefile.in: Re-generate.
1099 * i386-gen.c (process_i386_opcodes): New local variable
1100 "marker". Drop opening of input file. Recognize marker and line
1102 * i386-opc.tbl (OPCODE_I386_H): Define.
1103 (i386-opc.h): Include it.
1106 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1109 * i386-opc.h (Byte): Update comments.
1115 (Xmmword): Likewise.
1116 (Ymmword): Likewise.
1117 (Zmmword): Likewise.
1118 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1120 * i386-tbl.h: Regenerated.
1122 2018-07-12 Sudakshina Das <sudi.das@arm.com>
1124 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1125 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1126 * aarch64-asm-2.c: Regenerate.
1127 * aarch64-dis-2.c: Regenerate.
1128 * aarch64-opc-2.c: Regenerate.
1130 2018-07-12 Tamar Christina <tamar.christina@arm.com>
1133 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1134 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1135 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1136 sqdmulh, sqrdmulh): Use Em16.
1138 2018-07-11 Sudakshina Das <sudi.das@arm.com>
1140 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1141 csdb together with them.
1142 (thumb32_opcodes): Likewise.
1144 2018-07-11 Jan Beulich <jbeulich@suse.com>
1146 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1147 requiring 32-bit registers as operands 2 and 3. Improve
1149 (mwait, mwaitx): Fold templates. Improve comments.
1150 OPERAND_TYPE_INOUTPORTREG.
1151 * i386-tbl.h: Re-generate.
1153 2018-07-11 Jan Beulich <jbeulich@suse.com>
1155 * i386-gen.c (operand_type_init): Remove
1156 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1157 OPERAND_TYPE_INOUTPORTREG.
1158 * i386-init.h: Re-generate.
1160 2018-07-11 Jan Beulich <jbeulich@suse.com>
1162 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1163 (wrssq, wrussq): Add Qword.
1164 * i386-tbl.h: Re-generate.
1166 2018-07-11 Jan Beulich <jbeulich@suse.com>
1168 * i386-opc.h: Rename OTMax to OTNum.
1169 (OTNumOfUints): Adjust calculation.
1170 (OTUnused): Directly alias to OTNum.
1172 2018-07-09 Maciej W. Rozycki <macro@mips.com>
1174 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1176 (lea_reg_xys): Likewise.
1177 (print_insn_loop_primitive): Rename `reg' local variable to
1180 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1183 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1185 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1188 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1189 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1191 2018-07-02 Maciej W. Rozycki <macro@mips.com>
1194 * mips-dis.c (mips_option_arg_t): New enumeration.
1195 (mips_options): New variable.
1196 (disassembler_options_mips): New function.
1197 (print_mips_disassembler_options): Reimplement in terms of
1198 `disassembler_options_mips'.
1199 * arm-dis.c (disassembler_options_arm): Adapt to using the
1200 `disasm_options_and_args_t' structure.
1201 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1202 * s390-dis.c (disassembler_options_s390): Likewise.
1204 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1206 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1208 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1209 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1210 * testsuite/ld-arm/tls-longplt.d: Likewise.
1212 2018-06-29 Tamar Christina <tamar.christina@arm.com>
1215 * aarch64-asm-2.c: Regenerate.
1216 * aarch64-dis-2.c: Likewise.
1217 * aarch64-opc-2.c: Likewise.
1218 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1219 * aarch64-opc.c (operand_general_constraint_met_p,
1220 aarch64_print_operand): Likewise.
1221 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1222 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1224 (AARCH64_OPERANDS): Add Em2.
1226 2018-06-26 Nick Clifton <nickc@redhat.com>
1228 * po/uk.po: Updated Ukranian translation.
1229 * po/de.po: Updated German translation.
1230 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1232 2018-06-26 Nick Clifton <nickc@redhat.com>
1234 * nfp-dis.c: Fix spelling mistake.
1236 2018-06-24 Nick Clifton <nickc@redhat.com>
1238 * configure: Regenerate.
1239 * po/opcodes.pot: Regenerate.
1241 2018-06-24 Nick Clifton <nickc@redhat.com>
1243 2.31 branch created.
1245 2018-06-19 Tamar Christina <tamar.christina@arm.com>
1247 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1248 * aarch64-asm-2.c: Regenerate.
1249 * aarch64-dis-2.c: Likewise.
1251 2018-06-21 Maciej W. Rozycki <macro@mips.com>
1253 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1254 `-M ginv' option description.
1256 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1259 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1262 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1264 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1265 * configure.ac: Remove AC_PREREQ.
1266 * Makefile.in: Re-generate.
1267 * aclocal.m4: Re-generate.
1268 * configure: Re-generate.
1270 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1272 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1273 mips64r6 descriptors.
1274 (parse_mips_ase_option): Handle -Mginv option.
1275 (print_mips_disassembler_options): Document -Mginv.
1276 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1278 (mips_opcodes): Define ginvi and ginvt.
1280 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1281 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1283 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1284 * mips-opc.c (CRC, CRC64): New macros.
1285 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1286 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1289 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1292 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1293 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1295 2018-06-06 Alan Modra <amodra@gmail.com>
1297 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1298 setjmp. Move init for some other vars later too.
1300 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1302 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1303 (dis_private): Add new fields for property section tracking.
1304 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1305 (xtensa_instruction_fits): New functions.
1306 (fetch_data): Bump minimal fetch size to 4.
1307 (print_insn_xtensa): Make struct dis_private static.
1308 Load and prepare property table on section change.
1309 Don't disassemble literals. Don't disassemble instructions that
1310 cross property table boundaries.
1312 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1314 * configure: Regenerated.
1316 2018-06-01 Jan Beulich <jbeulich@suse.com>
1318 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1319 * i386-tbl.h: Re-generate.
1321 2018-06-01 Jan Beulich <jbeulich@suse.com>
1323 * i386-opc.tbl (sldt, str): Add NoRex64.
1324 * i386-tbl.h: Re-generate.
1326 2018-06-01 Jan Beulich <jbeulich@suse.com>
1328 * i386-opc.tbl (invpcid): Add Oword.
1329 * i386-tbl.h: Re-generate.
1331 2018-06-01 Alan Modra <amodra@gmail.com>
1333 * sysdep.h (_bfd_error_handler): Don't declare.
1334 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1335 * rl78-decode.opc: Likewise.
1336 * msp430-decode.c: Regenerate.
1337 * rl78-decode.c: Regenerate.
1339 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1341 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1342 * i386-init.h : Regenerated.
1344 2018-05-25 Alan Modra <amodra@gmail.com>
1346 * Makefile.in: Regenerate.
1347 * po/POTFILES.in: Regenerate.
1349 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1351 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1352 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1353 (insert_bab, extract_bab, insert_btab, extract_btab,
1354 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1355 (BAT, BBA VBA RBS XB6S): Delete macros.
1356 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1357 (BB, BD, RBX, XC6): Update for new macros.
1358 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1359 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1360 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1361 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1363 2018-05-18 John Darrington <john@darrington.wattle.id.au>
1365 * Makefile.am: Add support for s12z architecture.
1366 * configure.ac: Likewise.
1367 * disassemble.c: Likewise.
1368 * disassemble.h: Likewise.
1369 * Makefile.in: Regenerate.
1370 * configure: Regenerate.
1371 * s12z-dis.c: New file.
1374 2018-05-18 Alan Modra <amodra@gmail.com>
1376 * nfp-dis.c: Don't #include libbfd.h.
1377 (init_nfp3200_priv): Use bfd_get_section_contents.
1378 (nit_nfp6000_mecsr_sec): Likewise.
1380 2018-05-17 Nick Clifton <nickc@redhat.com>
1382 * po/zh_CN.po: Updated simplified Chinese translation.
1384 2018-05-16 Tamar Christina <tamar.christina@arm.com>
1387 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1388 * aarch64-dis-2.c: Regenerate.
1390 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1393 * aarch64-asm.c (opintl.h): Include.
1394 (aarch64_ins_sysreg): Enforce read/write constraints.
1395 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1396 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1397 (F_REG_READ, F_REG_WRITE): New.
1398 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1399 AARCH64_OPND_SYSREG.
1400 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1401 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1402 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1403 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1404 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1405 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1406 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1407 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1408 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1409 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1410 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1411 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1412 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1413 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1414 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1415 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1416 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1418 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1421 * aarch64-dis.c (no_notes: New.
1422 (parse_aarch64_dis_option): Support notes.
1423 (aarch64_decode_insn, print_operands): Likewise.
1424 (print_aarch64_disassembler_options): Document notes.
1425 * aarch64-opc.c (aarch64_print_operand): Support notes.
1427 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1430 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1431 and take error struct.
1432 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1433 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1434 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1435 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1436 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1437 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1438 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1439 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1440 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1441 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1442 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1443 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1444 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1445 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1446 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1447 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1448 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1449 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1450 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1451 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1452 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1453 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1454 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1455 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1456 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1457 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1458 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1459 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1460 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1461 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1462 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1463 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1464 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1465 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1466 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1467 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1468 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1469 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1470 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1471 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1472 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1473 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1474 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1475 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1476 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1477 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1478 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1479 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1480 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1481 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1482 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1483 (determine_disassembling_preference, aarch64_decode_insn,
1484 print_insn_aarch64_word, print_insn_data): Take errors struct.
1485 (print_insn_aarch64): Use errors.
1486 * aarch64-asm-2.c: Regenerate.
1487 * aarch64-dis-2.c: Regenerate.
1488 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1489 boolean in aarch64_insert_operan.
1490 (print_operand_extractor): Likewise.
1491 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1493 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
1495 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1497 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1499 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1501 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1503 * cr16-opc.c (cr16_instruction): Comment typo fix.
1504 * hppa-dis.c (print_insn_hppa): Likewise.
1506 2018-05-08 Jim Wilson <jimw@sifive.com>
1508 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1509 (match_c_slli64, match_srxi_as_c_srxi): New.
1510 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1511 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1512 <c.slli, c.srli, c.srai>: Use match_s_slli.
1513 <c.slli64, c.srli64, c.srai64>: New.
1515 2018-05-08 Alan Modra <amodra@gmail.com>
1517 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1518 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1519 partition opcode space for index lookup.
1521 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1523 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1524 <insn_length>: ...with this. Update usage.
1525 Remove duplicate call to *info->memory_error_func.
1527 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1528 H.J. Lu <hongjiu.lu@intel.com>
1530 * i386-dis.c (Gva): New.
1531 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1532 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1533 (prefix_table): New instructions (see prefix above).
1534 (mod_table): New instructions (see prefix above).
1535 (OP_G): Handle va_mode.
1536 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1537 CPU_MOVDIR64B_FLAGS.
1538 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1539 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1540 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1541 * i386-opc.tbl: Add movidir{i,64b}.
1542 * i386-init.h: Regenerated.
1543 * i386-tbl.h: Likewise.
1545 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1547 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1549 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1550 (AddrPrefixOpReg): This.
1551 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1552 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1554 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1556 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1557 (vle_num_opcodes): Likewise.
1558 (spe2_num_opcodes): Likewise.
1559 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1560 initialization loop.
1561 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1562 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1565 2018-05-01 Tamar Christina <tamar.christina@arm.com>
1567 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1569 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
1571 Makefile.am: Added nfp-dis.c.
1572 configure.ac: Added bfd_nfp_arch.
1573 disassemble.h: Added print_insn_nfp prototype.
1574 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1575 nfp-dis.c: New, for NFP support.
1576 po/POTFILES.in: Added nfp-dis.c to the list.
1577 Makefile.in: Regenerate.
1578 configure: Regenerate.
1580 2018-04-26 Jan Beulich <jbeulich@suse.com>
1582 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1583 templates into their base ones.
1584 * i386-tlb.h: Re-generate.
1586 2018-04-26 Jan Beulich <jbeulich@suse.com>
1588 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1589 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1590 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1591 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1592 * i386-init.h: Re-generate.
1594 2018-04-26 Jan Beulich <jbeulich@suse.com>
1596 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1597 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1598 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1599 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1601 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1603 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1605 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1606 cpuregzmm, and cpuregmask.
1607 * i386-init.h: Re-generate.
1608 * i386-tbl.h: Re-generate.
1610 2018-04-26 Jan Beulich <jbeulich@suse.com>
1612 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1613 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1614 * i386-init.h: Re-generate.
1616 2018-04-26 Jan Beulich <jbeulich@suse.com>
1618 * i386-gen.c (VexImmExt): Delete.
1619 * i386-opc.h (VexImmExt, veximmext): Delete.
1620 * i386-opc.tbl: Drop all VexImmExt uses.
1621 * i386-tlb.h: Re-generate.
1623 2018-04-25 Jan Beulich <jbeulich@suse.com>
1625 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1626 register-only forms.
1627 * i386-tlb.h: Re-generate.
1629 2018-04-25 Tamar Christina <tamar.christina@arm.com>
1631 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1633 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1635 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1637 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1638 (cpu_flags): Add CpuCLDEMOTE.
1639 * i386-init.h: Regenerate.
1640 * i386-opc.h (enum): Add CpuCLDEMOTE,
1641 (i386_cpu_flags): Add cpucldemote.
1642 * i386-opc.tbl: Add cldemote.
1643 * i386-tbl.h: Regenerate.
1645 2018-04-16 Alan Modra <amodra@gmail.com>
1647 * Makefile.am: Remove sh5 and sh64 support.
1648 * configure.ac: Likewise.
1649 * disassemble.c: Likewise.
1650 * disassemble.h: Likewise.
1651 * sh-dis.c: Likewise.
1652 * sh64-dis.c: Delete.
1653 * sh64-opc.c: Delete.
1654 * sh64-opc.h: Delete.
1655 * Makefile.in: Regenerate.
1656 * configure: Regenerate.
1657 * po/POTFILES.in: Regenerate.
1659 2018-04-16 Alan Modra <amodra@gmail.com>
1661 * Makefile.am: Remove w65 support.
1662 * configure.ac: Likewise.
1663 * disassemble.c: Likewise.
1664 * disassemble.h: Likewise.
1665 * w65-dis.c: Delete.
1666 * w65-opc.h: Delete.
1667 * Makefile.in: Regenerate.
1668 * configure: Regenerate.
1669 * po/POTFILES.in: Regenerate.
1671 2018-04-16 Alan Modra <amodra@gmail.com>
1673 * configure.ac: Remove we32k support.
1674 * configure: Regenerate.
1676 2018-04-16 Alan Modra <amodra@gmail.com>
1678 * Makefile.am: Remove m88k support.
1679 * configure.ac: Likewise.
1680 * disassemble.c: Likewise.
1681 * disassemble.h: Likewise.
1682 * m88k-dis.c: Delete.
1683 * Makefile.in: Regenerate.
1684 * configure: Regenerate.
1685 * po/POTFILES.in: Regenerate.
1687 2018-04-16 Alan Modra <amodra@gmail.com>
1689 * Makefile.am: Remove i370 support.
1690 * configure.ac: Likewise.
1691 * disassemble.c: Likewise.
1692 * disassemble.h: Likewise.
1693 * i370-dis.c: Delete.
1694 * i370-opc.c: Delete.
1695 * Makefile.in: Regenerate.
1696 * configure: Regenerate.
1697 * po/POTFILES.in: Regenerate.
1699 2018-04-16 Alan Modra <amodra@gmail.com>
1701 * Makefile.am: Remove h8500 support.
1702 * configure.ac: Likewise.
1703 * disassemble.c: Likewise.
1704 * disassemble.h: Likewise.
1705 * h8500-dis.c: Delete.
1706 * h8500-opc.h: Delete.
1707 * Makefile.in: Regenerate.
1708 * configure: Regenerate.
1709 * po/POTFILES.in: Regenerate.
1711 2018-04-16 Alan Modra <amodra@gmail.com>
1713 * configure.ac: Remove tahoe support.
1714 * configure: Regenerate.
1716 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1718 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1720 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1722 * i386-tbl.h: Regenerated.
1724 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1726 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1727 PREFIX_MOD_1_0FAE_REG_6.
1729 (OP_E_register): Use va_mode.
1730 * i386-dis-evex.h (prefix_table):
1731 New instructions (see prefixes above).
1732 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1733 (cpu_flags): Likewise.
1734 * i386-opc.h (enum): Likewise.
1735 (i386_cpu_flags): Likewise.
1736 * i386-opc.tbl: Add umonitor, umwait, tpause.
1737 * i386-init.h: Regenerate.
1738 * i386-tbl.h: Likewise.
1740 2018-04-11 Alan Modra <amodra@gmail.com>
1742 * opcodes/i860-dis.c: Delete.
1743 * opcodes/i960-dis.c: Delete.
1744 * Makefile.am: Remove i860 and i960 support.
1745 * configure.ac: Likewise.
1746 * disassemble.c: Likewise.
1747 * disassemble.h: Likewise.
1748 * Makefile.in: Regenerate.
1749 * configure: Regenerate.
1750 * po/POTFILES.in: Regenerate.
1752 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1755 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1757 (print_insn): Clear vex instead of vex.evex.
1759 2018-04-04 Nick Clifton <nickc@redhat.com>
1761 * po/es.po: Updated Spanish translation.
1763 2018-03-28 Jan Beulich <jbeulich@suse.com>
1765 * i386-gen.c (opcode_modifiers): Delete VecESize.
1766 * i386-opc.h (VecESize): Delete.
1767 (struct i386_opcode_modifier): Delete vecesize.
1768 * i386-opc.tbl: Drop VecESize.
1769 * i386-tlb.h: Re-generate.
1771 2018-03-28 Jan Beulich <jbeulich@suse.com>
1773 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1774 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1775 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1776 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1777 * i386-tlb.h: Re-generate.
1779 2018-03-28 Jan Beulich <jbeulich@suse.com>
1781 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1783 * i386-tlb.h: Re-generate.
1785 2018-03-28 Jan Beulich <jbeulich@suse.com>
1787 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1788 (vex_len_table): Drop Y for vcvt*2si.
1789 (putop): Replace plain 'Y' handling by abort().
1791 2018-03-28 Nick Clifton <nickc@redhat.com>
1794 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1795 instructions with only a base address register.
1796 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1797 handle AARHC64_OPND_SVE_ADDR_R.
1798 (aarch64_print_operand): Likewise.
1799 * aarch64-asm-2.c: Regenerate.
1800 * aarch64_dis-2.c: Regenerate.
1801 * aarch64-opc-2.c: Regenerate.
1803 2018-03-22 Jan Beulich <jbeulich@suse.com>
1805 * i386-opc.tbl: Drop VecESize from register only insn forms and
1806 memory forms not allowing broadcast.
1807 * i386-tlb.h: Re-generate.
1809 2018-03-22 Jan Beulich <jbeulich@suse.com>
1811 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1812 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1813 sha256*): Drop Disp<N>.
1815 2018-03-22 Jan Beulich <jbeulich@suse.com>
1817 * i386-dis.c (EbndS, bnd_swap_mode): New.
1818 (prefix_table): Use EbndS.
1819 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1820 * i386-opc.tbl (bndmov): Move misplaced Load.
1821 * i386-tlb.h: Re-generate.
1823 2018-03-22 Jan Beulich <jbeulich@suse.com>
1825 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1826 templates allowing memory operands and folded ones for register
1828 * i386-tlb.h: Re-generate.
1830 2018-03-22 Jan Beulich <jbeulich@suse.com>
1832 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1833 256-bit templates. Drop redundant leftover Disp<N>.
1834 * i386-tlb.h: Re-generate.
1836 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1838 * riscv-opc.c (riscv_insn_types): New.
1840 2018-03-13 Nick Clifton <nickc@redhat.com>
1842 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1844 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1846 * i386-opc.tbl: Add Optimize to clr.
1847 * i386-tbl.h: Regenerated.
1849 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1851 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1852 * i386-opc.h (OldGcc): Removed.
1853 (i386_opcode_modifier): Remove oldgcc.
1854 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1855 instructions for old (<= 2.8.1) versions of gcc.
1856 * i386-tbl.h: Regenerated.
1858 2018-03-08 Jan Beulich <jbeulich@suse.com>
1860 * i386-opc.h (EVEXDYN): New.
1861 * i386-opc.tbl: Fold various AVX512VL templates.
1862 * i386-tlb.h: Re-generate.
1864 2018-03-08 Jan Beulich <jbeulich@suse.com>
1866 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1867 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1868 vpexpandd, vpexpandq): Fold AFX512VF templates.
1869 * i386-tlb.h: Re-generate.
1871 2018-03-08 Jan Beulich <jbeulich@suse.com>
1873 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1874 Fold 128- and 256-bit VEX-encoded templates.
1875 * i386-tlb.h: Re-generate.
1877 2018-03-08 Jan Beulich <jbeulich@suse.com>
1879 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1880 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1881 vpexpandd, vpexpandq): Fold AVX512F templates.
1882 * i386-tlb.h: Re-generate.
1884 2018-03-08 Jan Beulich <jbeulich@suse.com>
1886 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1887 64-bit templates. Drop Disp<N>.
1888 * i386-tlb.h: Re-generate.
1890 2018-03-08 Jan Beulich <jbeulich@suse.com>
1892 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1893 and 256-bit templates.
1894 * i386-tlb.h: Re-generate.
1896 2018-03-08 Jan Beulich <jbeulich@suse.com>
1898 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1899 * i386-tlb.h: Re-generate.
1901 2018-03-08 Jan Beulich <jbeulich@suse.com>
1903 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1905 * i386-tlb.h: Re-generate.
1907 2018-03-08 Jan Beulich <jbeulich@suse.com>
1909 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1910 * i386-tlb.h: Re-generate.
1912 2018-03-08 Jan Beulich <jbeulich@suse.com>
1914 * i386-gen.c (opcode_modifiers): Delete FloatD.
1915 * i386-opc.h (FloatD): Delete.
1916 (struct i386_opcode_modifier): Delete floatd.
1917 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1919 * i386-tlb.h: Re-generate.
1921 2018-03-08 Jan Beulich <jbeulich@suse.com>
1923 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1925 2018-03-08 Jan Beulich <jbeulich@suse.com>
1927 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1928 * i386-tlb.h: Re-generate.
1930 2018-03-08 Jan Beulich <jbeulich@suse.com>
1932 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1934 * i386-tlb.h: Re-generate.
1936 2018-03-07 Alan Modra <amodra@gmail.com>
1938 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1940 * disassemble.h (print_insn_rs6000): Delete.
1941 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1942 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1943 (print_insn_rs6000): Delete.
1945 2018-03-03 Alan Modra <amodra@gmail.com>
1947 * sysdep.h (opcodes_error_handler): Define.
1948 (_bfd_error_handler): Declare.
1949 * Makefile.am: Remove stray #.
1950 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1952 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1953 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1954 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1955 opcodes_error_handler to print errors. Standardize error messages.
1956 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1957 and include opintl.h.
1958 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1959 * i386-gen.c: Standardize error messages.
1960 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1961 * Makefile.in: Regenerate.
1962 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1963 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1964 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1965 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1966 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1967 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1968 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1969 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1970 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1971 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1972 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1973 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1974 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1976 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1978 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1979 vpsub[bwdq] instructions.
1980 * i386-tbl.h: Regenerated.
1982 2018-03-01 Alan Modra <amodra@gmail.com>
1984 * configure.ac (ALL_LINGUAS): Sort.
1985 * configure: Regenerate.
1987 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1989 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1990 macro by assignements.
1992 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1995 * i386-gen.c (opcode_modifiers): Add Optimize.
1996 * i386-opc.h (Optimize): New enum.
1997 (i386_opcode_modifier): Add optimize.
1998 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1999 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2000 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2001 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2002 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2004 * i386-tbl.h: Regenerated.
2006 2018-02-26 Alan Modra <amodra@gmail.com>
2008 * crx-dis.c (getregliststring): Allocate a large enough buffer
2009 to silence false positive gcc8 warning.
2011 2018-02-22 Shea Levy <shea@shealevy.com>
2013 * disassemble.c (ARCH_riscv): Define if ARCH_all.
2015 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
2017 * i386-opc.tbl: Add {rex},
2018 * i386-tbl.h: Regenerated.
2020 2018-02-20 Maciej W. Rozycki <macro@mips.com>
2022 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2023 (mips16_opcodes): Replace `M' with `m' for "restore".
2025 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
2027 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2029 2018-02-13 Maciej W. Rozycki <macro@mips.com>
2031 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2032 variable to `function_index'.
2034 2018-02-13 Nick Clifton <nickc@redhat.com>
2037 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2038 about truncation of printing.
2040 2018-02-12 Henry Wong <henry@stuffedcow.net>
2042 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2044 2018-02-05 Nick Clifton <nickc@redhat.com>
2046 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2048 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2050 * i386-dis.c (enum): Add pconfig.
2051 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2052 (cpu_flags): Add CpuPCONFIG.
2053 * i386-opc.h (enum): Add CpuPCONFIG.
2054 (i386_cpu_flags): Add cpupconfig.
2055 * i386-opc.tbl: Add PCONFIG instruction.
2056 * i386-init.h: Regenerate.
2057 * i386-tbl.h: Likewise.
2059 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2061 * i386-dis.c (enum): Add PREFIX_0F09.
2062 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2063 (cpu_flags): Add CpuWBNOINVD.
2064 * i386-opc.h (enum): Add CpuWBNOINVD.
2065 (i386_cpu_flags): Add cpuwbnoinvd.
2066 * i386-opc.tbl: Add WBNOINVD instruction.
2067 * i386-init.h: Regenerate.
2068 * i386-tbl.h: Likewise.
2070 2018-01-17 Jim Wilson <jimw@sifive.com>
2072 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2074 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2076 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2077 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2078 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2079 (cpu_flags): Add CpuIBT, CpuSHSTK.
2080 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2081 (i386_cpu_flags): Add cpuibt, cpushstk.
2082 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2083 * i386-init.h: Regenerate.
2084 * i386-tbl.h: Likewise.
2086 2018-01-16 Nick Clifton <nickc@redhat.com>
2088 * po/pt_BR.po: Updated Brazilian Portugese translation.
2089 * po/de.po: Updated German translation.
2091 2018-01-15 Jim Wilson <jimw@sifive.com>
2093 * riscv-opc.c (match_c_nop): New.
2094 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2096 2018-01-15 Nick Clifton <nickc@redhat.com>
2098 * po/uk.po: Updated Ukranian translation.
2100 2018-01-13 Nick Clifton <nickc@redhat.com>
2102 * po/opcodes.pot: Regenerated.
2104 2018-01-13 Nick Clifton <nickc@redhat.com>
2106 * configure: Regenerate.
2108 2018-01-13 Nick Clifton <nickc@redhat.com>
2110 2.30 branch created.
2112 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2114 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2115 * i386-tbl.h: Regenerate.
2117 2018-01-10 Jan Beulich <jbeulich@suse.com>
2119 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2120 * i386-tbl.h: Re-generate.
2122 2018-01-10 Jan Beulich <jbeulich@suse.com>
2124 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2125 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2126 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2127 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2128 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2129 Disp8MemShift of AVX512VL forms.
2130 * i386-tbl.h: Re-generate.
2132 2018-01-09 Jim Wilson <jimw@sifive.com>
2134 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2135 then the hi_addr value is zero.
2137 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2139 * arm-dis.c (arm_opcodes): Add csdb.
2140 (thumb32_opcodes): Add csdb.
2142 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2144 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2145 * aarch64-asm-2.c: Regenerate.
2146 * aarch64-dis-2.c: Regenerate.
2147 * aarch64-opc-2.c: Regenerate.
2149 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2152 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2153 Remove AVX512 vmovd with 64-bit operands.
2154 * i386-tbl.h: Regenerated.
2156 2018-01-05 Jim Wilson <jimw@sifive.com>
2158 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2161 2018-01-03 Alan Modra <amodra@gmail.com>
2163 Update year range in copyright notice of all files.
2165 2018-01-02 Jan Beulich <jbeulich@suse.com>
2167 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2168 and OPERAND_TYPE_REGZMM entries.
2170 For older changes see ChangeLog-2017
2172 Copyright (C) 2018 Free Software Foundation, Inc.
2174 Copying and distribution of this file, with or without modification,
2175 are permitted in any medium without royalty provided the copyright
2176 notice and this notice are preserved.
2182 version-control: never