opcodes/ChangeLog

   1 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
   2             Lili Cui  <lili.cui@intel.com>
   3
   4         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
   5         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
   6         instructions.
   7         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
   8         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
   9         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
  10         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
  11         (i386_cpu_flags): Add cpuavx512_vp2intersect.
  12         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
  13         * i386-init.h: Regenerated.
  14         * i386-tbl.h: Likewise.
  15
  16 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
  17             Lili Cui  <lili.cui@intel.com>
  18
  19         * doc/c-i386.texi: Document enqcmd.
  20         * testsuite/gas/i386/enqcmd-intel.d: New file.
  21         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
  22         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
  23         * testsuite/gas/i386/enqcmd.d: Likewise.
  24         * testsuite/gas/i386/enqcmd.s: Likewise.
  25         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
  26         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
  27         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
  28         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
  29         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
  30         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
  31         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
  32         and x86-64-enqcmd.
  33
  34 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
  35
  36         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
  37
  38 2019-06-03  Alan Modra  <amodra@gmail.com>
  39
  40         * ppc-dis.c (prefix_opcd_indices): Correct size.
  41
  42 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
  43
  44         PR gas/24625
  45         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
  46         Disp8ShiftVL.
  47         * i386-tbl.h: Regenerated.
  48
  49 2019-05-24  Alan Modra  <amodra@gmail.com>
  50
  51         * po/POTFILES.in: Regenerate.
  52
  53 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
  54             Alan Modra  <amodra@gmail.com>
  55
  56         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
  57         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
  58         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
  59         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
  60         XTOP>): Define and add entries.
  61         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
  62         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
  63         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
  64         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
  65
  66 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
  67             Alan Modra  <amodra@gmail.com>
  68
  69         * ppc-dis.c (ppc_opts): Add "future" entry.
  70         (PREFIX_OPCD_SEGS): Define.
  71         (prefix_opcd_indices): New array.
  72         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
  73         (lookup_prefix): New function.
  74         (print_insn_powerpc): Handle 64-bit prefix instructions.
  75         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
  76         (PMRR, POWERXX): Define.
  77         (prefix_opcodes): New instruction table.
  78         (prefix_num_opcodes): New constant.
  79
  80 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
  81
  82         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
  83         * configure: Regenerated.
  84         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
  85         and cpu/bpf.opc.
  86         (HFILES): Add bpf-desc.h and bpf-opc.h.
  87         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
  88         bpf-ibld.c and bpf-opc.c.
  89         (BPF_DEPS): Define.
  90         * Makefile.in: Regenerated.
  91         * disassemble.c (ARCH_bpf): Define.
  92         (disassembler): Add case for bfd_arch_bpf.
  93         (disassemble_init_for_target): Likewise.
  94         (enum epbf_isa_attr): Define.
  95         * disassemble.h: extern print_insn_bpf.
  96         * bpf-asm.c: Generated.
  97         * bpf-opc.h: Likewise.
  98         * bpf-opc.c: Likewise.
  99         * bpf-ibld.c: Likewise.
 100         * bpf-dis.c: Likewise.
 101         * bpf-desc.h: Likewise.
 102         * bpf-desc.c: Likewise.
 103
 104 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 105
 106         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 107         and VMSR with the new operands.
 108
 109 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 110
 111         * arm-dis.c (enum mve_instructions): New enum
 112         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 113         and cneg.
 114         (mve_opcodes): New instructions as above.
 115         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 116         csneg and csel.
 117         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 118
 119 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 120
 121         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 122         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 123         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 124         uqshl, urshrl and urshr.
 125         (is_mve_okay_in_it): Add new instructions to TRUE list.
 126         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 127         (print_insn_mve): Updated to accept new %j,
 128         %<bitfield>m and %<bitfield>n patterns.
 129
 130 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 131
 132         * mips-opc.c (mips_builtin_opcodes): Change source register
 133         constraint for DAUI.
 134
 135 2019-05-20  Nick Clifton  <nickc@redhat.com>
 136
 137         * po/fr.po: Updated French translation.
 138
 139 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 140             Michael Collison <michael.collison@arm.com>
 141
 142         * arm-dis.c (thumb32_opcodes): Add new instructions.
 143         (enum mve_instructions): Likewise.
 144         (enum mve_undefined): Add new reasons.
 145         (is_mve_encoding_conflict): Handle new instructions.
 146         (is_mve_undefined): Likewise.
 147         (is_mve_unpredictable): Likewise.
 148         (print_mve_undefined): Likewise.
 149         (print_mve_size): Likewise.
 150
 151 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 152             Michael Collison <michael.collison@arm.com>
 153
 154         * arm-dis.c (thumb32_opcodes): Add new instructions.
 155         (enum mve_instructions): Likewise.
 156         (is_mve_encoding_conflict): Handle new instructions.
 157         (is_mve_undefined): Likewise.
 158         (is_mve_unpredictable): Likewise.
 159         (print_mve_size): Likewise.
 160
 161 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 162             Michael Collison <michael.collison@arm.com>
 163
 164         * arm-dis.c (thumb32_opcodes): Add new instructions.
 165         (enum mve_instructions): Likewise.
 166         (is_mve_encoding_conflict): Likewise.
 167         (is_mve_unpredictable): Likewise.
 168         (print_mve_size): Likewise.
 169
 170 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 171             Michael Collison <michael.collison@arm.com>
 172
 173         * arm-dis.c (thumb32_opcodes): Add new instructions.
 174         (enum mve_instructions): Likewise.
 175         (is_mve_encoding_conflict): Handle new instructions.
 176         (is_mve_undefined): Likewise.
 177         (is_mve_unpredictable): Likewise.
 178         (print_mve_size): Likewise.
 179
 180 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 181             Michael Collison <michael.collison@arm.com>
 182
 183         * arm-dis.c (thumb32_opcodes): Add new instructions.
 184         (enum mve_instructions): Likewise.
 185         (is_mve_encoding_conflict): Handle new instructions.
 186         (is_mve_undefined): Likewise.
 187         (is_mve_unpredictable): Likewise.
 188         (print_mve_size): Likewise.
 189         (print_insn_mve): Likewise.
 190
 191 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 192             Michael Collison <michael.collison@arm.com>
 193
 194         * arm-dis.c (thumb32_opcodes): Add new instructions.
 195         (print_insn_thumb32): Handle new instructions.
 196
 197 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 198             Michael Collison <michael.collison@arm.com>
 199
 200         * arm-dis.c (enum mve_instructions): Add new instructions.
 201         (enum mve_undefined): Add new reasons.
 202         (is_mve_encoding_conflict): Handle new instructions.
 203         (is_mve_undefined): Likewise.
 204         (is_mve_unpredictable): Likewise.
 205         (print_mve_undefined): Likewise.
 206         (print_mve_size): Likewise.
 207         (print_mve_shift_n): Likewise.
 208         (print_insn_mve): Likewise.
 209
 210 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 211             Michael Collison <michael.collison@arm.com>
 212
 213         * arm-dis.c (enum mve_instructions): Add new instructions.
 214         (is_mve_encoding_conflict): Handle new instructions.
 215         (is_mve_unpredictable): Likewise.
 216         (print_mve_rotate): Likewise.
 217         (print_mve_size): Likewise.
 218         (print_insn_mve): Likewise.
 219
 220 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 221             Michael Collison <michael.collison@arm.com>
 222
 223         * arm-dis.c (enum mve_instructions): Add new instructions.
 224         (is_mve_encoding_conflict): Handle new instructions.
 225         (is_mve_unpredictable): Likewise.
 226         (print_mve_size): Likewise.
 227         (print_insn_mve): Likewise.
 228
 229 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 230             Michael Collison <michael.collison@arm.com>
 231
 232         * arm-dis.c (enum mve_instructions): Add new instructions.
 233         (enum mve_undefined): Add new reasons.
 234         (is_mve_encoding_conflict): Handle new instructions.
 235         (is_mve_undefined): Likewise.
 236         (is_mve_unpredictable): Likewise.
 237         (print_mve_undefined): Likewise.
 238         (print_mve_size): Likewise.
 239         (print_insn_mve): Likewise.
 240
 241 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 242             Michael Collison <michael.collison@arm.com>
 243
 244         * arm-dis.c (enum mve_instructions): Add new instructions.
 245         (is_mve_encoding_conflict): Handle new instructions.
 246         (is_mve_undefined): Likewise.
 247         (is_mve_unpredictable): Likewise.
 248         (print_mve_size): Likewise.
 249         (print_insn_mve): Likewise.
 250
 251 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 252             Michael Collison <michael.collison@arm.com>
 253
 254         * arm-dis.c (enum mve_instructions): Add new instructions.
 255         (enum mve_unpredictable): Add new reasons.
 256         (enum mve_undefined): Likewise.
 257         (is_mve_okay_in_it): Handle new isntructions.
 258         (is_mve_encoding_conflict): Likewise.
 259         (is_mve_undefined): Likewise.
 260         (is_mve_unpredictable): Likewise.
 261         (print_mve_vmov_index): Likewise.
 262         (print_simd_imm8): Likewise.
 263         (print_mve_undefined): Likewise.
 264         (print_mve_unpredictable): Likewise.
 265         (print_mve_size): Likewise.
 266         (print_insn_mve): Likewise.
 267
 268 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 269             Michael Collison <michael.collison@arm.com>
 270
 271         * arm-dis.c (enum mve_instructions): Add new instructions.
 272         (enum mve_unpredictable): Add new reasons.
 273         (enum mve_undefined): Likewise.
 274         (is_mve_encoding_conflict): Handle new instructions.
 275         (is_mve_undefined): Likewise.
 276         (is_mve_unpredictable): Likewise.
 277         (print_mve_undefined): Likewise.
 278         (print_mve_unpredictable): Likewise.
 279         (print_mve_rounding_mode): Likewise.
 280         (print_mve_vcvt_size): Likewise.
 281         (print_mve_size): Likewise.
 282         (print_insn_mve): Likewise.
 283
 284 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 285             Michael Collison <michael.collison@arm.com>
 286
 287         * arm-dis.c (enum mve_instructions): Add new instructions.
 288         (enum mve_unpredictable): Add new reasons.
 289         (enum mve_undefined): Likewise.
 290         (is_mve_undefined): Handle new instructions.
 291         (is_mve_unpredictable): Likewise.
 292         (print_mve_undefined): Likewise.
 293         (print_mve_unpredictable): Likewise.
 294         (print_mve_size): Likewise.
 295         (print_insn_mve): Likewise.
 296
 297 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 298             Michael Collison <michael.collison@arm.com>
 299
 300         * arm-dis.c (enum mve_instructions): Add new instructions.
 301         (enum mve_undefined): Add new reasons.
 302         (insns): Add new instructions.
 303         (is_mve_encoding_conflict):
 304         (print_mve_vld_str_addr): New print function.
 305         (is_mve_undefined): Handle new instructions.
 306         (is_mve_unpredictable): Likewise.
 307         (print_mve_undefined): Likewise.
 308         (print_mve_size): Likewise.
 309         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 310         (print_insn_mve):  Handle new operands.
 311
 312 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 313             Michael Collison <michael.collison@arm.com>
 314
 315         * arm-dis.c (enum mve_instructions): Add new instructions.
 316         (enum mve_unpredictable): Add new reasons.
 317         (is_mve_encoding_conflict): Handle new instructions.
 318         (is_mve_unpredictable): Likewise.
 319         (mve_opcodes): Add new instructions.
 320         (print_mve_unpredictable): Handle new reasons.
 321         (print_mve_register_blocks): New print function.
 322         (print_mve_size): Handle new instructions.
 323         (print_insn_mve): Likewise.
 324
 325 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 326             Michael Collison <michael.collison@arm.com>
 327
 328         * arm-dis.c (enum mve_instructions): Add new instructions.
 329         (enum mve_unpredictable): Add new reasons.
 330         (enum mve_undefined): Likewise.
 331         (is_mve_encoding_conflict): Handle new instructions.
 332         (is_mve_undefined): Likewise.
 333         (is_mve_unpredictable): Likewise.
 334         (coprocessor_opcodes): Move NEON VDUP from here...
 335         (neon_opcodes): ... to here.
 336         (mve_opcodes): Add new instructions.
 337         (print_mve_undefined):  Handle new reasons.
 338         (print_mve_unpredictable): Likewise.
 339         (print_mve_size): Handle new instructions.
 340         (print_insn_neon): Handle vdup.
 341         (print_insn_mve): Handle new operands.
 342
 343 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 344             Michael Collison <michael.collison@arm.com>
 345
 346         * arm-dis.c (enum mve_instructions): Add new instructions.
 347         (enum mve_unpredictable): Add new values.
 348         (mve_opcodes): Add new instructions.
 349         (vec_condnames): New array with vector conditions.
 350         (mve_predicatenames): New array with predicate suffixes.
 351         (mve_vec_sizename): New array with vector sizes.
 352         (enum vpt_pred_state): New enum with vector predication states.
 353         (struct vpt_block): New struct type for vpt blocks.
 354         (vpt_block_state): Global struct to keep track of state.
 355         (mve_extract_pred_mask): New helper function.
 356         (num_instructions_vpt_block): Likewise.
 357         (mark_outside_vpt_block): Likewise.
 358         (mark_inside_vpt_block): Likewise.
 359         (invert_next_predicate_state): Likewise.
 360         (update_next_predicate_state): Likewise.
 361         (update_vpt_block_state): Likewise.
 362         (is_vpt_instruction): Likewise.
 363         (is_mve_encoding_conflict): Add entries for new instructions.
 364         (is_mve_unpredictable): Likewise.
 365         (print_mve_unpredictable): Handle new cases.
 366         (print_instruction_predicate): Likewise.
 367         (print_mve_size): New function.
 368         (print_vec_condition): New function.
 369         (print_insn_mve): Handle vpt blocks and new print operands.
 370
 371 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 372
 373         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 374         8, 14 and 15 for Armv8.1-M Mainline.
 375
 376 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 377             Michael Collison <michael.collison@arm.com>
 378
 379         * arm-dis.c (enum mve_instructions): New enum.
 380         (enum mve_unpredictable): Likewise.
 381         (enum mve_undefined): Likewise.
 382         (struct mopcode32): New struct.
 383         (is_mve_okay_in_it): New function.
 384         (is_mve_architecture): Likewise.
 385         (arm_decode_field): Likewise.
 386         (arm_decode_field_multiple): Likewise.
 387         (is_mve_encoding_conflict): Likewise.
 388         (is_mve_undefined): Likewise.
 389         (is_mve_unpredictable): Likewise.
 390         (print_mve_undefined): Likewise.
 391         (print_mve_unpredictable): Likewise.
 392         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 393         (print_insn_mve): New function.
 394         (print_insn_thumb32): Handle MVE architecture.
 395         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 396
 397 2019-05-10  Nick Clifton  <nickc@redhat.com>
 398
 399         PR 24538
 400         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 401         end of the table prematurely.
 402
 403 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 404
 405         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 406         macros for R6.
 407
 408 2019-05-11  Alan Modra  <amodra@gmail.com>
 409
 410         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 411         when -Mraw is in effect.
 412
 413 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 414
 415         * aarch64-dis-2.c: Regenerate.
 416         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 417         (OP_SVE_BBB): New variant set.
 418         (OP_SVE_DDDD): New variant set.
 419         (OP_SVE_HHH): New variant set.
 420         (OP_SVE_HHHU): New variant set.
 421         (OP_SVE_SSS): New variant set.
 422         (OP_SVE_SSSU): New variant set.
 423         (OP_SVE_SHH): New variant set.
 424         (OP_SVE_SBBU): New variant set.
 425         (OP_SVE_DSS): New variant set.
 426         (OP_SVE_DHHU): New variant set.
 427         (OP_SVE_VMV_HSD_BHS): New variant set.
 428         (OP_SVE_VVU_HSD_BHS): New variant set.
 429         (OP_SVE_VVVU_SD_BH): New variant set.
 430         (OP_SVE_VVVU_BHSD): New variant set.
 431         (OP_SVE_VVV_QHD_DBS): New variant set.
 432         (OP_SVE_VVV_HSD_BHS): New variant set.
 433         (OP_SVE_VVV_HSD_BHS2): New variant set.
 434         (OP_SVE_VVV_BHS_HSD): New variant set.
 435         (OP_SVE_VV_BHS_HSD): New variant set.
 436         (OP_SVE_VVV_SD): New variant set.
 437         (OP_SVE_VVU_BHS_HSD): New variant set.
 438         (OP_SVE_VZVV_SD): New variant set.
 439         (OP_SVE_VZVV_BH): New variant set.
 440         (OP_SVE_VZV_SD): New variant set.
 441         (aarch64_opcode_table): Add sve2 instructions.
 442
 443 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 444
 445         * aarch64-asm-2.c: Regenerated.
 446         * aarch64-dis-2.c: Regenerated.
 447         * aarch64-opc-2.c: Regenerated.
 448         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 449         for SVE_SHLIMM_UNPRED_22.
 450         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 451         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 452         operand.
 453
 454 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 455
 456         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 457         sve_size_tsz_bhs iclass encode.
 458         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 459         sve_size_tsz_bhs iclass decode.
 460
 461 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 462
 463         * aarch64-asm-2.c: Regenerated.
 464         * aarch64-dis-2.c: Regenerated.
 465         * aarch64-opc-2.c: Regenerated.
 466         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 467         for SVE_Zm4_11_INDEX.
 468         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 469         (fields): Handle SVE_i2h field.
 470         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 471         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 472
 473 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 474
 475         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 476         sve_shift_tsz_bhsd iclass encode.
 477         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 478         sve_shift_tsz_bhsd iclass decode.
 479
 480 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 481
 482         * aarch64-asm-2.c: Regenerated.
 483         * aarch64-dis-2.c: Regenerated.
 484         * aarch64-opc-2.c: Regenerated.
 485         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 486         (aarch64_encode_variant_using_iclass): Handle
 487         sve_shift_tsz_hsd iclass encode.
 488         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 489         sve_shift_tsz_hsd iclass decode.
 490         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 491         for SVE_SHRIMM_UNPRED_22.
 492         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 493         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 494         operand.
 495
 496 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 497
 498         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 499         sve_size_013 iclass encode.
 500         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 501         sve_size_013 iclass decode.
 502
 503 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 504
 505         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 506         sve_size_bh iclass encode.
 507         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 508         sve_size_bh iclass decode.
 509
 510 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 511
 512         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 513         sve_size_sd2 iclass encode.
 514         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 515         sve_size_sd2 iclass decode.
 516         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 517         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 518
 519 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 520
 521         * aarch64-asm-2.c: Regenerated.
 522         * aarch64-dis-2.c: Regenerated.
 523         * aarch64-opc-2.c: Regenerated.
 524         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 525         for SVE_ADDR_ZX.
 526         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 527         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 528
 529 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 530
 531         * aarch64-asm-2.c: Regenerated.
 532         * aarch64-dis-2.c: Regenerated.
 533         * aarch64-opc-2.c: Regenerated.
 534         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 535         for SVE_Zm3_11_INDEX.
 536         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 537         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 538         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 539         fields.
 540         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 541
 542 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 543
 544         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 545         sve_size_hsd2 iclass encode.
 546         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 547         sve_size_hsd2 iclass decode.
 548         * aarch64-opc.c (fields): Handle SVE_size field.
 549         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 550
 551 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 552
 553         * aarch64-asm-2.c: Regenerated.
 554         * aarch64-dis-2.c: Regenerated.
 555         * aarch64-opc-2.c: Regenerated.
 556         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 557         for SVE_IMM_ROT3.
 558         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 559         (fields): Handle SVE_rot3 field.
 560         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 561         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 562
 563 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 564
 565         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 566         instructions.
 567
 568 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 569
 570         * aarch64-tbl.h
 571         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 572         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 573         aarch64_feature_sve2bitperm): New feature sets.
 574         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 575         for feature set addresses.
 576         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 577         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 578
 579 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 580             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 581
 582         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 583         argument and set ASE_EVA_R6 appropriately.
 584         (set_default_mips_dis_options): Pass ISA to above.
 585         (parse_mips_dis_option): Likewise.
 586         * mips-opc.c (EVAR6): New macro.
 587         (mips_builtin_opcodes): Add llwpe, scwpe.
 588
 589 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 590
 591         * aarch64-asm-2.c: Regenerated.
 592         * aarch64-dis-2.c: Regenerated.
 593         * aarch64-opc-2.c: Regenerated.
 594         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 595         AARCH64_OPND_TME_UIMM16.
 596         (aarch64_print_operand): Likewise.
 597         * aarch64-tbl.h (QL_IMM_NIL): New.
 598         (TME): New.
 599         (_TME_INSN): New.
 600         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 601
 602 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 603
 604         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 605
 606 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 607             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 608
 609         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 610
 611 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 612
 613         * s12z-opc.h: Add extern "C" bracketing to help
 614         users who wish to use this interface in c++ code.
 615
 616 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 617
 618         * s12z-opc.c (bm_decode): Handle bit map operations with the
 619         "reserved0" mode.
 620
 621 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 622
 623         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 624         specifier.  Add entries for VLDR and VSTR of system registers.
 625         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 626         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 627         of %J and %K format specifier.
 628
 629 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 630
 631         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 632         Add new entries for VSCCLRM instruction.
 633         (print_insn_coprocessor): Handle new %C format control code.
 634
 635 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 636
 637         * arm-dis.c (enum isa): New enum.
 638         (struct sopcode32): New structure.
 639         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 640         set isa field of all current entries to ANY.
 641         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 642         Only match an entry if its isa field allows the current mode.
 643
 644 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 645
 646         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 647         CLRM.
 648         (print_insn_thumb32): Add logic to print %n CLRM register list.
 649
 650 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 651
 652         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 653         and %Q patterns.
 654
 655 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 656
 657         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 658         (print_insn_thumb32): Edit the switch case for %Z.
 659
 660 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 661
 662         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 663
 664 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 665
 666         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 667
 668 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 669
 670         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 671
 672 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 673
 674         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 675         Arm register with r13 and r15 unpredictable.
 676         (thumb32_opcodes): New instructions for bfx and bflx.
 677
 678 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 679
 680         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 681
 682 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 683
 684         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 685
 686 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 687
 688         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 689
 690 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 691
 692         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 693
 694 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 695
 696         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 697         "optr". ("operator" is a reserved word in c++).
 698
 699 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 700
 701         * aarch64-opc.c (aarch64_print_operand): Add case for
 702         AARCH64_OPND_Rt_SP.
 703         (verify_constraints): Likewise.
 704         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 705         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 706         to accept Rt|SP as first operand.
 707         (AARCH64_OPERANDS): Add new Rt_SP.
 708         * aarch64-asm-2.c: Regenerated.
 709         * aarch64-dis-2.c: Regenerated.
 710         * aarch64-opc-2.c: Regenerated.
 711
 712 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 713
 714         * aarch64-asm-2.c: Regenerated.
 715         * aarch64-dis-2.c: Likewise.
 716         * aarch64-opc-2.c: Likewise.
 717         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 718
 719 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 720
 721         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 722
 723 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 724
 725         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 726         * i386-init.h: Regenerated.
 727
 728 2019-04-07  Alan Modra  <amodra@gmail.com>
 729
 730         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 731         op_separator to control printing of spaces, comma and parens
 732         rather than need_comma, need_paren and spaces vars.
 733
 734 2019-04-07  Alan Modra  <amodra@gmail.com>
 735
 736         PR 24421
 737         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 738         (print_insn_neon, print_insn_arm): Likewise.
 739
 740 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 741
 742         * i386-dis-evex.h (evex_table): Updated to support BF16
 743         instructions.
 744         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 745         and EVEX_W_0F3872_P_3.
 746         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 747         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 748         * i386-opc.h (enum): Add CpuAVX512_BF16.
 749         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 750         * i386-opc.tbl: Add AVX512 BF16 instructions.
 751         * i386-init.h: Regenerated.
 752         * i386-tbl.h: Likewise.
 753
 754 2019-04-05  Alan Modra  <amodra@gmail.com>
 755
 756         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 757         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 758         to favour printing of "-" branch hint when using the "y" bit.
 759         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 760
 761 2019-04-05  Alan Modra  <amodra@gmail.com>
 762
 763         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 764         opcode until first operand is output.
 765
 766 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 767
 768         PR gas/24349
 769         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 770         (valid_bo_post_v2): Add support for 'at' branch hints.
 771         (insert_bo): Only error on branch on ctr.
 772         (get_bo_hint_mask): New function.
 773         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 774         for inserting 'at' branch hints.
 775         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 776         for extracting 'at' branch hints.
 777         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 778         (BOE): Delete operand.
 779         (BOM, BOP): New operands.
 780         (RM): Update value.
 781         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 782         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 783         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 784         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 785         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 786         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 787         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 788         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 789         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 790         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 791         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 792         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 793         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 794         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 795         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 796         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 797         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 798         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 799         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 800         bttarl+>: New extended mnemonics.
 801
 802 2019-03-28  Alan Modra  <amodra@gmail.com>
 803
 804         PR 24390
 805         * ppc-opc.c (BTF): Define.
 806         (powerpc_opcodes): Use for mtfsb*.
 807         * ppc-dis.c (print_insn_powerpc): Print fields with both
 808         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 809
 810 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 811
 812         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 813         (mapping_symbol_for_insn): Implement new algorithm.
 814         (print_insn): Remove duplicate code.
 815
 816 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 817
 818         * aarch64-dis.c (print_insn_aarch64):
 819         Implement override.
 820
 821 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 822
 823         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 824         order.
 825
 826 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 827
 828         * aarch64-dis.c (last_stop_offset): New.
 829         (print_insn_aarch64): Use stop_offset.
 830
 831 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 832
 833         PR gas/24359
 834         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 835         CPU_ANY_AVX2_FLAGS.
 836         * i386-init.h: Regenerated.
 837
 838 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 839
 840         PR gas/24348
 841         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 842         vmovdqu16, vmovdqu32 and vmovdqu64.
 843         * i386-tbl.h: Regenerated.
 844
 845 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 846
 847         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 848         from vstrszb, vstrszh, and vstrszf.
 849
 850 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 851
 852         * s390-opc.txt: Add instruction descriptions.
 853
 854 2019-02-08  Jim Wilson  <jimw@sifive.com>
 855
 856         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 857         <bne>: Likewise.
 858
 859 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 860
 861         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 862
 863 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 864
 865         PR binutils/23212
 866         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 867         * aarch64-opc.c (verify_elem_sd): New.
 868         (fields): Add FLD_sz entr.
 869         * aarch64-tbl.h (_SIMD_INSN): New.
 870         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 871         fmulx scalar and vector by element isns.
 872
 873 2019-02-07  Nick Clifton  <nickc@redhat.com>
 874
 875         * po/sv.po: Updated Swedish translation.
 876
 877 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 878
 879         * s390-mkopc.c (main): Accept arch13 as cpu string.
 880         * s390-opc.c: Add new instruction formats and instruction opcode
 881         masks.
 882         * s390-opc.txt: Add new arch13 instructions.
 883
 884 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 885
 886         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 887         (aarch64_opcode): Change encoding for stg, stzg
 888         st2g and st2zg.
 889         * aarch64-asm-2.c: Regenerated.
 890         * aarch64-dis-2.c: Regenerated.
 891         * aarch64-opc-2.c: Regenerated.
 892
 893 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 894
 895         * aarch64-asm-2.c: Regenerated.
 896         * aarch64-dis-2.c: Likewise.
 897         * aarch64-opc-2.c: Likewise.
 898         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 899
 900 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 901             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 902
 903         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 904         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 905         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 906         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 907         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 908         case for ldstgv_indexed.
 909         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 910         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 911         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 912         * aarch64-asm-2.c: Regenerated.
 913         * aarch64-dis-2.c: Regenerated.
 914         * aarch64-opc-2.c: Regenerated.
 915
 916 2019-01-23  Nick Clifton  <nickc@redhat.com>
 917
 918         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 919
 920 2019-01-21  Nick Clifton  <nickc@redhat.com>
 921
 922         * po/de.po: Updated German translation.
 923         * po/uk.po: Updated Ukranian translation.
 924
 925 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 926         * mips-dis.c (mips_arch_choices): Fix typo in
 927         gs464, gs464e and gs264e descriptors.
 928
 929 2019-01-19  Nick Clifton  <nickc@redhat.com>
 930
 931         * configure: Regenerate.
 932         * po/opcodes.pot: Regenerate.
 933
 934 2018-06-24  Nick Clifton  <nickc@redhat.com>
 935
 936         2.32 branch created.
 937
 938 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 939
 940         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 941         if it is null.
 942         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 943         zero.
 944
 945 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 946
 947         * configure: Regenerate.
 948
 949 2019-01-07  Alan Modra  <amodra@gmail.com>
 950
 951         * configure: Regenerate.
 952         * po/POTFILES.in: Regenerate.
 953
 954 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 955
 956         * s12z-opc.c: New file.
 957         * s12z-opc.h: New file.
 958         * s12z-dis.c: Removed all code not directly related to display
 959         of instructions.  Used the interface provided by the new files
 960         instead.
 961         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 962         * Makefile.in: Regenerate.
 963         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 964         * configure: Regenerate.
 965
 966 2019-01-01  Alan Modra  <amodra@gmail.com>
 967
 968         Update year range in copyright notice of all files.
 969
 970 For older changes see ChangeLog-2018
 971 \f
 972 Copyright (C) 2019 Free Software Foundation, Inc.
 973
 974 Copying and distribution of this file, with or without modification,
 975 are permitted in any medium without royalty provided the copyright
 976 notice and this notice are preserved.
 977
 978 Local Variables:
 979 mode: change-log
 980 left-margin: 8
 981 fill-column: 74
 982 version-control: never
 983 End: