opcodes/ChangeLog

   1 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-opc.tbl (movsx): Remove Intel syntax comments.
   4         (movzx): Likewise.
   5
   6 2020-02-14  Jan Beulich  <jbeulich@suse.com>
   7
   8         PR gas/25438
   9         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
  10         destination for Cpu64-only variant.
  11         (movzx): Fold patterns.
  12         * i386-tbl.h: Re-generate.
  13
  14 2020-02-13  Jan Beulich  <jbeulich@suse.com>
  15
  16         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
  17         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
  18         CPU_ANY_SSE4_FLAGS entry.
  19         * i386-init.h: Re-generate.
  20
  21 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  22
  23         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
  24         with Unspecified, making the present one AT&T syntax only.
  25         * i386-tbl.h: Re-generate.
  26
  27 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  28
  29         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
  30         * i386-tbl.h: Re-generate.
  31
  32 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  33
  34         PR gas/24546
  35         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
  36         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
  37         Amd64 and Intel64 templates.
  38         (call, jmp): Likewise for far indirect variants. Dro
  39         Unspecified.
  40         * i386-tbl.h: Re-generate.
  41
  42 2020-02-11  Jan Beulich  <jbeulich@suse.com>
  43
  44         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
  45         * i386-opc.h (ShortForm): Delete.
  46         (struct i386_opcode_modifier): Remove shortform field.
  47         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
  48         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
  49         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
  50         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
  51         Drop ShortForm.
  52         * i386-tbl.h: Re-generate.
  53
  54 2020-02-11  Jan Beulich  <jbeulich@suse.com>
  55
  56         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
  57         fucompi): Drop ShortForm from operand-less templates.
  58         * i386-tbl.h: Re-generate.
  59
  60 2020-02-11  Alan Modra  <amodra@gmail.com>
  61
  62         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
  63         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
  64         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
  65         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
  66         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
  67
  68 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
  69
  70         * arm-dis.c (print_insn_cde): Define 'V' parse character.
  71         (cde_opcodes): Add VCX* instructions.
  72
  73 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
  74             Matthew Malcomson  <matthew.malcomson@arm.com>
  75
  76         * arm-dis.c (struct cdeopcode32): New.
  77         (CDE_OPCODE): New macro.
  78         (cde_opcodes): New disassembly table.
  79         (regnames): New option to table.
  80         (cde_coprocs): New global variable.
  81         (print_insn_cde): New
  82         (print_insn_thumb32): Use print_insn_cde.
  83         (parse_arm_disassembler_options): Parse coprocN args.
  84
  85 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
  86
  87         PR gas/25516
  88         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
  89         with ISA64.
  90         * i386-opc.h (AMD64): Removed.
  91         (Intel64): Likewose.
  92         (AMD64): New.
  93         (INTEL64): Likewise.
  94         (INTEL64ONLY): Likewise.
  95         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
  96         * i386-opc.tbl (Amd64): New.
  97         (Intel64): Likewise.
  98         (Intel64Only): Likewise.
  99         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 100         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 101         * i386-tbl.h: Regenerated.
 102
 103 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 104
 105         PR 25469
 106         * z80-dis.c: Add support for GBZ80 opcodes.
 107
 108 2020-02-04  Alan Modra  <amodra@gmail.com>
 109
 110         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 111
 112 2020-02-03  Alan Modra  <amodra@gmail.com>
 113
 114         * m32c-ibld.c: Regenerate.
 115
 116 2020-02-01  Alan Modra  <amodra@gmail.com>
 117
 118         * frv-ibld.c: Regenerate.
 119
 120 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 121
 122         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 123         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 124         (OP_E_memory): Replace xmm_mdq_mode case label by
 125         vex_scalar_w_dq_mode one.
 126         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 127
 128 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 129
 130         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 131         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 132         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 133         (intel_operand_size): Drop vex_w_dq_mode case label.
 134
 135 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 136
 137         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 138         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 139
 140 2020-01-30  Alan Modra  <amodra@gmail.com>
 141
 142         * m32c-ibld.c: Regenerate.
 143
 144 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 145
 146         * bpf-opc.c: Regenerate.
 147
 148 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 149
 150         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 151         (dis386): Use them to replace C2/C3 table entries.
 152         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 153         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 154         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 155         * i386-tbl.h: Re-generate.
 156
 157 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 158
 159         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 160         forms.
 161         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 162         DefaultSize.
 163         * i386-tbl.h: Re-generate.
 164
 165 2020-01-30  Alan Modra  <amodra@gmail.com>
 166
 167         * tic4x-dis.c (tic4x_dp): Make unsigned.
 168
 169 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 170             Jan Beulich  <jbeulich@suse.com>
 171
 172         PR binutils/25445
 173         * i386-dis.c (MOVSXD_Fixup): New function.
 174         (movsxd_mode): New enum.
 175         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 176         (intel_operand_size): Handle movsxd_mode.
 177         (OP_E_register): Likewise.
 178         (OP_G): Likewise.
 179         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 180         register on movsxd.  Add movsxd with 16-bit destination register
 181         for AMD64 and Intel64 ISAs.
 182         * i386-tbl.h: Regenerated.
 183
 184 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 185
 186         PR 25403
 187         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 188         * aarch64-asm-2.c: Regenerate
 189         * aarch64-dis-2.c: Likewise.
 190         * aarch64-opc-2.c: Likewise.
 191
 192 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 193
 194         * i386-opc.tbl (sysret): Drop DefaultSize.
 195         * i386-tbl.h: Re-generate.
 196
 197 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 198
 199         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 200         Dword.
 201         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 202         * i386-tbl.h: Re-generate.
 203
 204 2020-01-20  Nick Clifton  <nickc@redhat.com>
 205
 206         * po/de.po: Updated German translation.
 207         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 208         * po/uk.po: Updated Ukranian translation.
 209
 210 2020-01-20  Alan Modra  <amodra@gmail.com>
 211
 212         * hppa-dis.c (fput_const): Remove useless cast.
 213
 214 2020-01-20  Alan Modra  <amodra@gmail.com>
 215
 216         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 217
 218 2020-01-18  Nick Clifton  <nickc@redhat.com>
 219
 220         * configure: Regenerate.
 221         * po/opcodes.pot: Regenerate.
 222
 223 2020-01-18  Nick Clifton  <nickc@redhat.com>
 224
 225         Binutils 2.34 branch created.
 226
 227 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 228
 229         * opintl.h: Fix spelling error (seperate).
 230
 231 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 232
 233         * i386-opc.tbl: Add {vex} pseudo prefix.
 234         * i386-tbl.h: Regenerated.
 235
 236 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 237
 238         PR 25376
 239         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 240         (neon_opcodes): Likewise.
 241         (select_arm_features): Make sure we enable MVE bits when selecting
 242         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 243         any architecture.
 244
 245 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 246
 247         * i386-opc.tbl: Drop stale comment from XOP section.
 248
 249 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 250
 251         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 252         (extractps): Add VexWIG to SSE2AVX forms.
 253         * i386-tbl.h: Re-generate.
 254
 255 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 256
 257         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 258         Size64 from and use VexW1 on SSE2AVX forms.
 259         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 260         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 261         * i386-tbl.h: Re-generate.
 262
 263 2020-01-15  Alan Modra  <amodra@gmail.com>
 264
 265         * tic4x-dis.c (tic4x_version): Make unsigned long.
 266         (optab, optab_special, registernames): New file scope vars.
 267         (tic4x_print_register): Set up registernames rather than
 268         malloc'd registertable.
 269         (tic4x_disassemble): Delete optable and optable_special.  Use
 270         optab and optab_special instead.  Throw away old optab,
 271         optab_special and registernames when info->mach changes.
 272
 273 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 274
 275         PR 25377
 276         * z80-dis.c (suffix): Use .db instruction to generate double
 277         prefix.
 278
 279 2020-01-14  Alan Modra  <amodra@gmail.com>
 280
 281         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 282         values to unsigned before shifting.
 283
 284 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 285
 286         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 287         flow instructions.
 288         (print_insn_thumb16, print_insn_thumb32): Likewise.
 289         (print_insn): Initialize the insn info.
 290         * i386-dis.c (print_insn): Initialize the insn info fields, and
 291         detect jumps.
 292
 293 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 294
 295         * arc-opc.c (C_NE): Make it required.
 296
 297 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 298
 299         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 300         reserved register name.
 301
 302 2020-01-13  Alan Modra  <amodra@gmail.com>
 303
 304         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 305         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 306
 307 2020-01-13  Alan Modra  <amodra@gmail.com>
 308
 309         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 310         result of wasm_read_leb128 in a uint64_t and check that bits
 311         are not lost when copying to other locals.  Use uint32_t for
 312         most locals.  Use PRId64 when printing int64_t.
 313
 314 2020-01-13  Alan Modra  <amodra@gmail.com>
 315
 316         * score-dis.c: Formatting.
 317         * score7-dis.c: Formatting.
 318
 319 2020-01-13  Alan Modra  <amodra@gmail.com>
 320
 321         * score-dis.c (print_insn_score48): Use unsigned variables for
 322         unsigned values.  Don't left shift negative values.
 323         (print_insn_score32): Likewise.
 324         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 325
 326 2020-01-13  Alan Modra  <amodra@gmail.com>
 327
 328         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 329
 330 2020-01-13  Alan Modra  <amodra@gmail.com>
 331
 332         * fr30-ibld.c: Regenerate.
 333
 334 2020-01-13  Alan Modra  <amodra@gmail.com>
 335
 336         * xgate-dis.c (print_insn): Don't left shift signed value.
 337         (ripBits): Formatting, use 1u.
 338
 339 2020-01-10  Alan Modra  <amodra@gmail.com>
 340
 341         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 342         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 343
 344 2020-01-10  Alan Modra  <amodra@gmail.com>
 345
 346         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 347         and XRREG value earlier to avoid a shift with negative exponent.
 348         * m10200-dis.c (disassemble): Similarly.
 349
 350 2020-01-09  Nick Clifton  <nickc@redhat.com>
 351
 352         PR 25224
 353         * z80-dis.c (ld_ii_ii): Use correct cast.
 354
 355 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 356
 357         PR 25224
 358         * z80-dis.c (ld_ii_ii): Use character constant when checking
 359         opcode byte value.
 360
 361 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 362
 363         * i386-dis.c (SEP_Fixup): New.
 364         (SEP): Define.
 365         (dis386_twobyte): Use it for sysenter/sysexit.
 366         (enum x86_64_isa): Change amd64 enumerator to value 1.
 367         (OP_J): Compare isa64 against intel64 instead of amd64.
 368         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 369         forms.
 370         * i386-tbl.h: Re-generate.
 371
 372 2020-01-08  Alan Modra  <amodra@gmail.com>
 373
 374         * z8k-dis.c: Include libiberty.h
 375         (instr_data_s): Make max_fetched unsigned.
 376         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 377         Don't exceed byte_info bounds.
 378         (output_instr): Make num_bytes unsigned.
 379         (unpack_instr): Likewise for nibl_count and loop.
 380         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 381         idx unsigned.
 382         * z8k-opc.h: Regenerate.
 383
 384 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 385
 386         * arc-tbl.h (llock): Use 'LLOCK' as class.
 387         (llockd): Likewise.
 388         (scond): Use 'SCOND' as class.
 389         (scondd): Likewise.
 390         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 391         (scondd): Likewise.
 392
 393 2020-01-06  Alan Modra  <amodra@gmail.com>
 394
 395         * m32c-ibld.c: Regenerate.
 396
 397 2020-01-06  Alan Modra  <amodra@gmail.com>
 398
 399         PR 25344
 400         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 401         Peek at next byte to prevent recursion on repeated prefix bytes.
 402         Ensure uninitialised "mybuf" is not accessed.
 403         (print_insn_z80): Don't zero n_fetch and n_used here,..
 404         (print_insn_z80_buf): ..do it here instead.
 405
 406 2020-01-04  Alan Modra  <amodra@gmail.com>
 407
 408         * m32r-ibld.c: Regenerate.
 409
 410 2020-01-04  Alan Modra  <amodra@gmail.com>
 411
 412         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 413
 414 2020-01-04  Alan Modra  <amodra@gmail.com>
 415
 416         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 417
 418 2020-01-04  Alan Modra  <amodra@gmail.com>
 419
 420         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 421
 422 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 423
 424         * aarch64-tbl.h (aarch64_opcode_table): Use
 425         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 426
 427 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 428
 429         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 430         forms of SUDOT and USDOT.
 431
 432 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 433
 434         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 435         uzip{1,2}.
 436         * opcodes/aarch64-dis-2.c: Re-generate.
 437
 438 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 439
 440         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 441         FMMLA encoding.
 442         * opcodes/aarch64-dis-2.c: Re-generate.
 443
 444 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 445
 446         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 447
 448 2020-01-01  Alan Modra  <amodra@gmail.com>
 449
 450         Update year range in copyright notice of all files.
 451
 452 For older changes see ChangeLog-2019
 453 \f
 454 Copyright (C) 2020 Free Software Foundation, Inc.
 455
 456 Copying and distribution of this file, with or without modification,
 457 are permitted in any medium without royalty provided the copyright
 458 notice and this notice are preserved.
 459
 460 Local Variables:
 461 mode: change-log
 462 left-margin: 8
 463 fill-column: 74
 464 version-control: never
 465 End: