opcodes/ChangeLog

   1 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
   2
   3         * i386-dis.c (OP_Mwaitx): New.
   4         (rm_table): Add monitorx/mwaitx.
   5         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
   6         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
   7         (operand_type_init): Add CpuMWAITX.
   8         * i386-opc.h (CpuMWAITX): New.
   9         (i386_cpu_flags): Add cpumwaitx.
  10         * i386-opc.tbl: Add monitorx and mwaitx.
  11         * i386-init.h: Regenerated.
  12         * i386-tbl.h: Likewise.
  13
  14 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
  15
  16         * ppc-opc.c (insert_ls): Test for invalid LS operands.
  17         (insert_esync): New function.
  18         (LS, WC): Use insert_ls.
  19         (ESYNC): Use insert_esync.
  20
  21 2015-06-22  Nick Clifton  <nickc@redhat.com>
  22
  23         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
  24         requested region lies beyond it.
  25         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
  26         looking for 32-bit insns.
  27         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
  28         data.
  29         * sh-dis.c (print_insn_sh): Likewise.
  30         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
  31         blocks of instructions.
  32         * vax-dis.c (print_insn_vax): Check that the requested address
  33         does not clash with the stop_vma.
  34
  35 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
  36
  37         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
  38         * ppc-opc.c (FXM4): Add non-zero optional value.
  39         (TBR): Likewise.
  40         (SXL): Likewise.
  41         (insert_fxm): Handle new default operand value.
  42         (extract_fxm): Likewise.
  43         (insert_tbr): Likewise.
  44         (extract_tbr): Likewise.
  45
  46 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
  47
  48         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
  49
  50 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  51
  52         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
  53
  54 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
  55
  56         * ppc-opc.c: Add comment accidentally removed by old commit.
  57         (MTMSRD_L): Delete.
  58
  59 2015-06-04  Nick Clifton  <nickc@redhat.com>
  60
  61         PR 18474
  62         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
  63
  64 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
  65
  66         * arm-dis.c (arm_opcodes): Add "setpan".
  67         (thumb_opcodes): Add "setpan".
  68
  69 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
  70
  71         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
  72         macros.
  73
  74 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
  75
  76         * aarch64-tbl.h (aarch64_feature_rdma): New.
  77         (RDMA): New.
  78         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
  79         * aarch64-asm-2.c: Regenerate.
  80         * aarch64-dis-2.c: Regenerate.
  81         * aarch64-opc-2.c: Regenerate.
  82
  83 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
  84
  85         * aarch64-tbl.h (aarch64_feature_lor): New.
  86         (LOR): New.
  87         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
  88         "stllrb", "stllrh".
  89         * aarch64-asm-2.c: Regenerate.
  90         * aarch64-dis-2.c: Regenerate.
  91         * aarch64-opc-2.c: Regenerate.
  92
  93 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
  94
  95         * aarch64-opc.c (F_ARCHEXT): New.
  96         (aarch64_sys_regs): Add "pan".
  97         (aarch64_sys_reg_supported_p): New.
  98         (aarch64_pstatefields): Add "pan".
  99         (aarch64_pstatefield_supported_p): New.
 100
 101 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 102
 103         * i386-tbl.h: Regenerate.
 104
 105 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 106
 107         * i386-dis.c (print_insn): Swap rounding mode specifier and
 108         general purpose register in Intel mode.
 109
 110 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 111
 112         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 113         * i386-tbl.h: Regenerate.
 114
 115 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 116
 117         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 118         * i386-init.h: Regenerated.
 119
 120 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 121
 122         PR binutis/18386
 123         * i386-dis.c: Add comments for '@'.
 124         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 125         (enum x86_64_isa): New.
 126         (isa64): Likewise.
 127         (print_i386_disassembler_options): Add amd64 and intel64.
 128         (print_insn): Handle amd64 and intel64.
 129         (putop): Handle '@'.
 130         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 131         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 132         * i386-opc.h (AMD64): New.
 133         (CpuIntel64): Likewise.
 134         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 135         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 136         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 137         * i386-init.h: Regenerated.
 138         * i386-tbl.h: Likewise.
 139
 140 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 141
 142         * ppc-opc.c (IH) New define.
 143         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 144         <tlbie>: Add RS operand for POWER7.
 145         <slbia>: Add IH operand for POWER6.
 146
 147 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 148
 149         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 150         direct branch.
 151         (jmp): Likewise.
 152         * i386-tbl.h: Regenerated.
 153
 154 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 155
 156         * configure.ac: Support bfd_iamcu_arch.
 157         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 158         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 159         CPU_IAMCU_COMPAT_FLAGS.
 160         (cpu_flags): Add CpuIAMCU.
 161         * i386-opc.h (CpuIAMCU): New.
 162         (i386_cpu_flags): Add cpuiamcu.
 163         * configure: Regenerated.
 164         * i386-init.h: Likewise.
 165         * i386-tbl.h: Likewise.
 166
 167 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 168
 169         PR binutis/18386
 170         * i386-dis.c (X86_64_E8): New.
 171         (X86_64_E9): Likewise.
 172         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 173         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 174         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 175         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 176         (putop): Handle '^'.
 177         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 178         REX_W.
 179
 180 2015-04-30  DJ Delorie  <dj@redhat.com>
 181
 182         * disassemble.c (disassembler): Choose suitable disassembler based
 183         on E_ABI.
 184         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 185         it to decode mul/div insns.
 186         * rl78-decode.c: Regenerate.
 187         * rl78-dis.c (print_insn_rl78): Rename to...
 188         (print_insn_rl78_common): ...this, take ISA parameter.
 189         (print_insn_rl78): New.
 190         (print_insn_rl78_g10): New.
 191         (print_insn_rl78_g13): New.
 192         (print_insn_rl78_g14): New.
 193         (rl78_get_disassembler): New.
 194
 195 2015-04-29  Nick Clifton  <nickc@redhat.com>
 196
 197         * po/fr.po: Updated French translation.
 198
 199 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 200
 201         * ppc-opc.c (DCBT_EO): New define.
 202         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 203         <lharx>: Likewise.
 204         <stbcx.>: Likewise.
 205         <sthcx.>: Likewise.
 206         <waitrsv>: Do not enable for POWER7 and later.
 207         <waitimpl>: Likewise.
 208         <dcbt>: Default to the two operand form of the instruction for all
 209         "old" cpus.  For "new" cpus, use the operand ordering that matches
 210         whether the cpu is server or embedded.
 211         <dcbtst>: Likewise.
 212
 213 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 214
 215         * s390-opc.c: New instruction type VV0UU2.
 216         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 217         and WFC.
 218
 219 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 220
 221         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 222         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 223         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 224         (vfpclasspd, vfpclassps): Add %XZ.
 225
 226 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 227
 228         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 229         (PREFIX_UD_REPZ): Likewise.
 230         (PREFIX_UD_REPNZ): Likewise.
 231         (PREFIX_UD_DATA): Likewise.
 232         (PREFIX_UD_ADDR): Likewise.
 233         (PREFIX_UD_LOCK): Likewise.
 234
 235 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 236
 237         * i386-dis.c (prefix_requirement): Removed.
 238         (print_insn): Don't set prefix_requirement.  Check
 239         dp->prefix_requirement instead of prefix_requirement.
 240
 241 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 242
 243         PR binutils/17898
 244         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 245         (PREFIX_MOD_0_0FC7_REG_6): This.
 246         (PREFIX_MOD_3_0FC7_REG_6): New.
 247         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 248         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 249         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 250         PREFIX_MOD_3_0FC7_REG_7.
 251         (mod_table): Replace PREFIX_0FC7_REG_6 with
 252         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 253         PREFIX_MOD_3_0FC7_REG_7.
 254
 255 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 256
 257         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 258         (PREFIX_MANDATORY_REPNZ): Likewise.
 259         (PREFIX_MANDATORY_DATA): Likewise.
 260         (PREFIX_MANDATORY_ADDR): Likewise.
 261         (PREFIX_MANDATORY_LOCK): Likewise.
 262         (PREFIX_MANDATORY): Likewise.
 263         (PREFIX_UD_SHIFT): Set to 8
 264         (PREFIX_UD_REPZ): Updated.
 265         (PREFIX_UD_REPNZ): Likewise.
 266         (PREFIX_UD_DATA): Likewise.
 267         (PREFIX_UD_ADDR): Likewise.
 268         (PREFIX_UD_LOCK): Likewise.
 269         (PREFIX_IGNORED_SHIFT): New.
 270         (PREFIX_IGNORED_REPZ): Likewise.
 271         (PREFIX_IGNORED_REPNZ): Likewise.
 272         (PREFIX_IGNORED_DATA): Likewise.
 273         (PREFIX_IGNORED_ADDR): Likewise.
 274         (PREFIX_IGNORED_LOCK): Likewise.
 275         (PREFIX_OPCODE): Likewise.
 276         (PREFIX_IGNORED): Likewise.
 277         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 278         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 279         (three_byte_table): Likewise.
 280         (mod_table): Likewise.
 281         (mandatory_prefix): Renamed to ...
 282         (prefix_requirement): This.
 283         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 284         Update PREFIX_90 entry.
 285         (get_valid_dis386): Check prefix_requirement to see if a prefix
 286         should be ignored.
 287         (print_insn): Replace mandatory_prefix with prefix_requirement.
 288
 289 2015-04-15  Renlin Li  <renlin.li@arm.com>
 290
 291         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 292         use it for ssat and ssat16.
 293         (print_insn_thumb32): Add handle case for 'D' control code.
 294
 295 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 296             H.J. Lu  <hongjiu.lu@intel.com>
 297
 298         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 299         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 300         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 301         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 302         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 303         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 304         Fill prefix_requirement field.
 305         (struct dis386): Add prefix_requirement field.
 306         (dis386): Fill prefix_requirement field.
 307         (dis386_twobyte): Ditto.
 308         (twobyte_has_mandatory_prefix_: Remove.
 309         (reg_table): Fill prefix_requirement field.
 310         (prefix_table): Ditto.
 311         (x86_64_table): Ditto.
 312         (three_byte_table): Ditto.
 313         (xop_table): Ditto.
 314         (vex_table): Ditto.
 315         (vex_len_table): Ditto.
 316         (vex_w_table): Ditto.
 317         (mod_table): Ditto.
 318         (bad_opcode): Ditto.
 319         (print_insn): Use prefix_requirement.
 320         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 321         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 322         (float_reg): Ditto.
 323
 324 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 325
 326         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 327
 328 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 329
 330         * Makefile.in: Regenerated.
 331
 332 2015-03-25  Anton Blanchard  <anton@samba.org>
 333
 334         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 335         powerpc_opcd_indices and vle_opcd_indices once.
 336
 337 2015-03-25  Anton Blanchard  <anton@samba.org>
 338
 339         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 340
 341 2015-03-24  Terry Guo  <terry.guo@arm.com>
 342
 343         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 344         (opcode16): Likewise.
 345         (coprocessor_opcodes): Replace bit with feature struct.
 346         (neon_opcodes): Likewise.
 347         (arm_opcodes): Likewise.
 348         (thumb_opcodes): Likewise.
 349         (thumb32_opcodes): Likewise.
 350         (print_insn_coprocessor): Likewise.
 351         (print_insn_arm): Likewise.
 352         (select_arm_features): Follow new feature struct.
 353
 354 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 355
 356         * i386-dis.c (rm_table): Add clzero.
 357         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 358         Add CPU_CLZERO_FLAGS.
 359         (cpu_flags): Add CpuCLZERO.
 360         * i386-opc.h: Add CpuCLZERO.
 361         * i386-opc.tbl: Add clzero.
 362         * i386-init.h: Re-generated.
 363         * i386-tbl.h: Re-generated.
 364
 365 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 366
 367         * mips-opc.c (decode_mips_operand): Fix constraint issues
 368         with u and y operands.
 369
 370 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 371
 372         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 373
 374 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 375
 376         * s390-opc.c: Add new IBM z13 instructions.
 377         * s390-opc.txt: Likewise.
 378
 379 2015-03-10  Renlin Li  <renlin.li@arm.com>
 380
 381         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 382         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 383         related alias.
 384         * aarch64-asm-2.c: Regenerate.
 385         * aarch64-dis-2.c: Likewise.
 386         * aarch64-opc-2.c: Likewise.
 387
 388 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 389
 390         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 391
 392 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 393
 394         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 395         arch_sh_up.
 396         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 397         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 398
 399 2015-02-23  Vinay  <Vinay.G@kpit.com>
 400
 401         * rl78-decode.opc (MOV): Added space between two operands for
 402         'mov' instruction in index addressing mode.
 403         * rl78-decode.c: Regenerate.
 404
 405 2015-02-19  Pedro Alves  <palves@redhat.com>
 406
 407         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 408
 409 2015-02-10  Pedro Alves  <palves@redhat.com>
 410             Tom Tromey  <tromey@redhat.com>
 411
 412         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 413         microblaze_and, microblaze_xor.
 414         * microblaze-opc.h (opcodes): Adjust.
 415
 416 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 417
 418         * Makefile.am: Add FT32 files.
 419         * configure.ac: Handle FT32.
 420         * disassemble.c (disassembler): Call print_insn_ft32.
 421         * ft32-dis.c: New file.
 422         * ft32-opc.c: New file.
 423         * Makefile.in: Regenerate.
 424         * configure: Regenerate.
 425         * po/POTFILES.in: Regenerate.
 426
 427 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 428
 429         * nds32-asm.c (keyword_sr): Add new system registers.
 430
 431 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 432
 433         * s390-dis.c (s390_extract_operand): Support vector register
 434         operands.
 435         (s390_print_insn_with_opcode): Support new operands types and add
 436         new handling of optional operands.
 437         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 438         and include opcode/s390.h instead.
 439         (struct op_struct): New field `flags'.
 440         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 441         (dumpTable): Dump flags.
 442         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 443         string.
 444         * s390-opc.c: Add new operands types, instruction formats, and
 445         instruction masks.
 446         (s390_opformats): Add new formats for .insn.
 447         * s390-opc.txt: Add new instructions.
 448
 449 2015-01-01  Alan Modra  <amodra@gmail.com>
 450
 451         Update year range in copyright notice of all files.
 452
 453 For older changes see ChangeLog-2014
 454 \f
 455 Copyright (C) 2015 Free Software Foundation, Inc.
 456
 457 Copying and distribution of this file, with or without modification,
 458 are permitted in any medium without royalty provided the copyright
 459 notice and this notice are preserved.
 460
 461 Local Variables:
 462 mode: change-log
 463 left-margin: 8
 464 fill-column: 74
 465 version-control: never
 466 End: