opcodes/ChangeLog

   1 2004-07-22  Nick Clifton  <nickc@redhat.com>
   2
   3         PR/280
   4         * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
   5         insns - this is done by objdump itself.
   6         * h8500-dis.c (print_insn_h8500): Likewise.
   7
   8 2004-07-21  Jan Beulich <jbeulich@novell.com>
   9
  10         * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
  11         regardless of address size prefix in effect.
  12         (ptr_reg): Size or address registers does not depend on rex64, but
  13         on the presence of an address size override.
  14         (OP_MMX): Use rex.x only for xmm registers.
  15         (OP_EM): Use rex.z only for xmm registers.
  16
  17 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
  18
  19         * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
  20         move/branch operations to the bottom so that VR5400 multimedia
  21         instructions take precedence in disassembly.
  22
  23 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
  24
  25         * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
  26         ISA-specific "break" encoding.
  27
  28 2004-07-13  Elvis Chiang  <elvisfb@gmail.com>
  29
  30         * arm-opc.h: Fix typo in comment.
  31
  32 2004-07-11  Andreas Schwab  <schwab@suse.de>
  33
  34         * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
  35
  36 2004-07-09  Andreas Schwab  <schwab@suse.de>
  37
  38         * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
  39
  40 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
  41
  42         * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
  43         (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
  44         (crx-dis.lo): New target.
  45         (crx-opc.lo): Likewise.
  46         * Makefile.in: Regenerate.
  47         * configure.in: Handle bfd_crx_arch.
  48         * configure: Regenerate.
  49         * crx-dis.c: New file.
  50         * crx-opc.c: New file.
  51         * disassemble.c (ARCH_crx): Define.
  52         (disassembler): Handle ARCH_crx.
  53
  54 2004-06-29  James E Wilson  <wilson@specifixinc.com>
  55
  56         * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
  57         * ia64-asmtab.c: Regnerate.
  58
  59 2004-06-28  Alan Modra  <amodra@bigpond.net.au>
  60
  61         * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
  62         (extract_fxm): Don't test dialect.
  63         (XFXFXM_MASK): Include the power4 bit.
  64         (XFXM): Add p4 param.
  65         (powerpc_opcodes): Add mfocrf and mtocrf.  Adjust mtcr.
  66
  67 2004-06-27  Alexandre Oliva  <aoliva@redhat.com>
  68
  69         2003-07-21  Richard Sandiford  <rsandifo@redhat.com>
  70         * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
  71
  72 2004-06-26  Alan Modra  <amodra@bigpond.net.au>
  73
  74         * ppc-opc.c (BH, XLBH_MASK): Define.
  75         (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
  76
  77 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
  78
  79         * i386-dis.c (x_mode): Comment.
  80         (two_source_ops): File scope.
  81         (float_mem): Correct fisttpll and fistpll.
  82         (float_mem_mode): New table.
  83         (dofloat): Use it.
  84         (OP_E): Correct intel mode PTR output.
  85         (ptr_reg): Use open_char and close_char.
  86         (PNI_Fixup): Handle possible suffix on sidt.  Use op1out etc. for
  87         operands.  Set two_source_ops.
  88
  89 2004-06-15  Alan Modra  <amodra@bigpond.net.au>
  90
  91         * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
  92         instead of _raw_size.
  93
  94 2004-06-08  Jakub Jelinek  <jakub@redhat.com>
  95
  96         * ia64-gen.c (in_iclass): Handle more postinc st
  97         and ld variants.
  98         * ia64-asmtab.c: Rebuilt.
  99
 100 2004-06-01  Martin Schwidefsky  <schwidefsky@de.ibm.com>
 101
 102         * s390-opc.txt: Correct architecture mask for some opcodes.
 103         lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
 104         in the esa mode as well.
 105
 106 2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
 107
 108         * sh-dis.c (target_arch): Make unsigned.
 109         (print_insn_sh): Replace (most of) switch with a call to
 110         sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
 111         * sh-opc.h: Redefine architecture flags values.
 112         Add sh3-nommu architecture.
 113         Reorganise <arch>_up macros so they make more visual sense.
 114         (SH_MERGE_ARCH_SET): Define new macro.
 115         (SH_VALID_BASE_ARCH_SET): Likewise.
 116         (SH_VALID_MMU_ARCH_SET): Likewise.
 117         (SH_VALID_CO_ARCH_SET): Likewise.
 118         (SH_VALID_ARCH_SET): Likewise.
 119         (SH_MERGE_ARCH_SET_VALID): Likewise.
 120         (SH_ARCH_SET_HAS_FPU): Likewise.
 121         (SH_ARCH_SET_HAS_DSP): Likewise.
 122         (SH_ARCH_UNKNOWN_ARCH): Likewise.
 123         (sh_get_arch_from_bfd_mach): Add prototype.
 124         (sh_get_arch_up_from_bfd_mach): Likewise.
 125         (sh_get_bfd_mach_from_arch_set): Likewise.
 126         (sh_merge_bfd_arc): Likewise.
 127
 128 2004-05-24  Peter Barada  <peter@the-baradas.com>
 129
 130         * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
 131         into new match_insn_m68k function.  Loop over canidate
 132         matches and select first that completely matches.
 133         * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
 134         * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
 135         to verify addressing for MAC/EMAC.
 136         * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
 137         reigster halves since 'fpu' and 'spl' look misleading.
 138         * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
 139         * m68k-opc.c: Rearragne mac/emac cases to use longest for
 140         first, tighten up match masks.
 141         * m68k-opc.c: Add 'size' field to struct m68k_opcode.  Produce
 142         'size' from special case code in print_insn_m68k to
 143         determine decode size of insns.
 144
 145 2004-05-19  Alan Modra  <amodra@bigpond.net.au>
 146
 147         * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
 148         well as when -mpower4.
 149
 150 2004-05-13  Nick Clifton  <nickc@redhat.com>
 151
 152         * po/fr.po: Updated French translation.
 153
 154 2004-05-05  Peter Barada  <peter@the-baradas.com>
 155
 156         * m68k-dis.c(print_insn_m68k): Add new chips, use core
 157         variants in arch_mask.  Only set m68881/68851 for 68k chips.
 158         * m68k-op.c: Switch from ColdFire chips to core variants.
 159
 160 2004-05-05  Alan Modra  <amodra@bigpond.net.au>
 161
 162         PR 147.
 163         * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
 164
 165 2004-04-29  Ben Elliston  <bje@au.ibm.com>
 166
 167         * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
 168         (powerpc_opcodes): Add "dbczl" instruction for PPC970.
 169
 170 2004-04-22  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
 171
 172         * sh-dis.c (print_insn_sh): Print the value in constant pool
 173         as a symbol if it looks like a symbol.
 174
 175 2004-04-22  Peter Barada <peter@the-baradas.com>
 176
 177         * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
 178         appropriate ColdFire architectures.
 179         (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
 180         mask addressing.
 181         Add EMAC instructions, fix MAC instructions. Remove
 182         macmw/macml/msacmw/msacml instructions since mask addressing now
 183         supported.
 184
 185 2004-04-20  Jakub Jelinek  <jakub@redhat.com>
 186
 187         * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
 188         (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
 189         suffix.  Use fmov*x macros, create all 3 fpsize variants in one
 190         macro.  Adjust all users.
 191
 192 2004-04-15  Anil Paranjpe  <anilp1@kpitcummins.com>
 193
 194         * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
 195         separately.
 196
 197 2004-03-30  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 198
 199         * m32r-asm.c: Regenerate.
 200
 201 2004-03-29  Stan Shebs  <shebs@apple.com>
 202
 203         * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
 204         used.
 205
 206 2004-03-19  Alan Modra  <amodra@bigpond.net.au>
 207
 208         * aclocal.m4: Regenerate.
 209         * config.in: Regenerate.
 210         * configure: Regenerate.
 211         * po/POTFILES.in: Regenerate.
 212         * po/opcodes.pot: Regenerate.
 213
 214 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 215
 216         * ppc-dis.c (print_insn_powerpc): Don't print tabs.  Handle
 217         PPC_OPERANDS_GPR_0.
 218         * ppc-opc.c (RA0): Define.
 219         (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
 220         (RAOPT): Rename from RAO.  Update all uses.
 221         (powerpc_opcodes): Use RA0 as appropriate.
 222
 223 2004-03-15  Aldy Hernandez  <aldyh@redhat.com>
 224
 225         * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
 226
 227 2004-03-15  Alan Modra  <amodra@bigpond.net.au>
 228
 229         * sparc-dis.c (print_insn_sparc): Update getword prototype.
 230
 231 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 232
 233         * i386-dis.c (GRPPLOCK): Delete.
 234         (grps): Delete GRPPLOCK entry.
 235
 236 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 237
 238         * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
 239         (M, Mp): Use OP_M.
 240         (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
 241         (GRPPADLCK): Define.
 242         (dis386): Use NOP_Fixup on "nop".
 243         (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
 244         (twobyte_has_modrm): Set for 0xa7.
 245         (padlock_table): Delete.  Move to..
 246         (grps): ..here, using OP_0f07.  Use OP_Ofae on lfence, mfence
 247         and clflush.
 248         (print_insn): Revert PADLOCK_SPECIAL code.
 249         (OP_E): Delete sfence, lfence, mfence checks.
 250
 251 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 252
 253         * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
 254         (INVLPG_Fixup): New function.
 255         (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
 256
 257 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 258
 259         * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
 260         (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
 261         (padlock_table): New struct with PadLock instructions.
 262         (print_insn): Handle PADLOCK_SPECIAL.
 263
 264 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 265
 266         * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
 267         (OP_E): Twiddle clflush to sfence here.
 268
 269 2004-03-08  Nick Clifton  <nickc@redhat.com>
 270
 271         * po/de.po: Updated German translation.
 272
 273 2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
 274
 275         * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
 276         nofpu mode.  Add BFD type bfd_mach_sh4_nommu_nofpu.
 277         * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
 278         accordingly.
 279
 280 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 281
 282         * frv-asm.c: Regenerate.
 283         * frv-desc.c: Regenerate.
 284         * frv-desc.h: Regenerate.
 285         * frv-dis.c: Regenerate.
 286         * frv-ibld.c: Regenerate.
 287         * frv-opc.c: Regenerate.
 288         * frv-opc.h: Regenerate.
 289
 290 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 291
 292         * frv-desc.c, frv-opc.c: Regenerate.
 293
 294 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 295
 296         * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
 297
 298 2004-02-26  Andrew Stubbs  <andrew.stubbs@superh.com>
 299
 300         * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
 301         Also correct mistake in the comment.
 302
 303 2004-02-26  Andrew Stubbs <andrew.stubbs@superh.com>
 304
 305         * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
 306         ensure that double registers have even numbers.
 307         Add REG_N_B01 for nn01 (binary 01) nibble to ensure
 308         that reserved instruction 0xfffd does not decode the same
 309         as 0xfdfd (ftrv).
 310         * sh-opc.h: Add REG_N_D nibble type and use it whereever
 311         REG_N refers to a double register.
 312         Add REG_N_B01 nibble type and use it instead of REG_NM
 313         in ftrv.
 314         Adjust the bit patterns in a few comments.
 315
 316 2004-02-25  Aldy Hernandez  <aldyh@redhat.com>
 317
 318         * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
 319
 320 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 321
 322         * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
 323
 324 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 325
 326         * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
 327
 328 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 329
 330         * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
 331         mtivor32, mtivor33, mtivor34.
 332
 333 2004-02-19  Aldy Hernandez  <aldyh@redhat.com>
 334
 335         * ppc-opc.c (powerpc_opcodes): Add mfmcar.
 336
 337 2004-02-10  Petko Manolov  <petkan@nucleusys.com>
 338
 339         * arm-opc.h Maverick accumulator register opcode fixes.
 340
 341 2004-02-13  Ben Elliston  <bje@wasabisystems.com>
 342
 343         * m32r-dis.c: Regenerate.
 344
 345 2004-01-27  Michael Snyder  <msnyder@redhat.com>
 346
 347         * sh-opc.h (sh_table): "fsrra", not "fssra".
 348
 349 2004-01-23  Andrew Over <andrew.over@cs.anu.edu.au>
 350
 351         * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
 352         contraints.
 353
 354 2004-01-19  Andrew Over  <andrew.over@cs.anu.edu.au>
 355
 356         * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
 357
 358 2004-01-19  Alan Modra  <amodra@bigpond.net.au>
 359
 360         * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
 361         1.  Don't print scale factor on AT&T mode when index missing.
 362
 363 2004-01-16  Alexandre Oliva  <aoliva@redhat.com>
 364
 365         * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
 366         when loaded into XR registers.
 367
 368 2004-01-14  Richard Sandiford  <rsandifo@redhat.com>
 369
 370         * frv-desc.h: Regenerate.
 371         * frv-desc.c: Regenerate.
 372         * frv-opc.c: Regenerate.
 373
 374 2004-01-13  Michael Snyder  <msnyder@redhat.com>
 375
 376         * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
 377
 378 2004-01-09  Paul Brook  <paul@codesourcery.com>
 379
 380         * arm-opc.h (arm_opcodes): Move generic mcrr after known
 381         specific opcodes.
 382
 383 2004-01-07  Daniel Jacobowitz  <drow@mvista.com>
 384
 385         * Makefile.am (libopcodes_la_DEPENDENCIES)
 386         (libopcodes_la_LIBADD): Revert 2003-05-17 change.  Add explanatory
 387         comment about the problem.
 388         * Makefile.in: Regenerate.
 389
 390 2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
 391
 392         2003-12-19  Alexandre Oliva  <aoliva@redhat.com>
 393         * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
 394         cut&paste errors in shifting/truncating numerical operands.
 395         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 396         * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
 397         (parse_uslo16): Likewise.
 398         (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
 399         (parse_d12): Parse gotoff12 and gotofffuncdesc12.
 400         (parse_s12): Likewise.
 401         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 402         * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
 403         (parse_uslo16): Likewise.
 404         (parse_uhi16): Parse gothi and gotfuncdeschi.
 405         (parse_d12): Parse got12 and gotfuncdesc12.
 406         (parse_s12): Likewise.
 407
 408 2004-01-02  Albert Bartoszko  <albar@nt.kegel.com.pl>
 409
 410         * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
 411         instruction which looks similar to an 'rla' instruction.
 412
 413 For older changes see ChangeLog-0203
 414 \f
 415 Local Variables:
 416 mode: change-log
 417 left-margin: 8
 418 fill-column: 74
 419 version-control: never
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