1 2019-12-04 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
4 * i386-tbl.h: Re-generate.
6 2019-12-04 Jan Beulich <jbeulich@suse.com>
8 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
10 2019-12-04 Jan Beulich <jbeulich@suse.com>
12 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
14 (xbegin): Drop DefaultSize.
15 * i386-tbl.h: Re-generate.
17 2019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
19 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
20 Change the coproc CRC conditions to use the extension
21 feature set, second word, base on ARM_EXT2_CRC.
23 2019-11-14 Jan Beulich <jbeulich@suse.com>
25 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
26 * i386-tbl.h: Re-generate.
28 2019-11-14 Jan Beulich <jbeulich@suse.com>
30 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
31 JumpInterSegment, and JumpAbsolute entries.
32 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
33 JUMP_ABSOLUTE): Define.
34 (struct i386_opcode_modifier): Extend jump field to 3 bits.
35 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
37 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
38 JumpInterSegment): Define.
39 * i386-tbl.h: Re-generate.
41 2019-11-14 Jan Beulich <jbeulich@suse.com>
43 * i386-gen.c (operand_type_init): Remove
44 OPERAND_TYPE_JUMPABSOLUTE entry.
45 (opcode_modifiers): Add JumpAbsolute entry.
46 (operand_types): Remove JumpAbsolute entry.
47 * i386-opc.h (JumpAbsolute): Move between enums.
48 (struct i386_opcode_modifier): Add jumpabsolute field.
49 (union i386_operand_type): Remove jumpabsolute field.
50 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
51 * i386-init.h, i386-tbl.h: Re-generate.
53 2019-11-14 Jan Beulich <jbeulich@suse.com>
55 * i386-gen.c (opcode_modifiers): Add AnySize entry.
56 (operand_types): Remove AnySize entry.
57 * i386-opc.h (AnySize): Move between enums.
58 (struct i386_opcode_modifier): Add anysize field.
59 (OTUnused): Un-comment.
60 (union i386_operand_type): Remove anysize field.
61 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
62 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
63 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
65 * i386-tbl.h: Re-generate.
67 2019-11-12 Nelson Chu <nelson.chu@sifive.com>
69 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
70 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
71 use the floating point register (FPR).
73 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
75 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
77 (is_mve_encoding_conflict): Update cmode conflict checks for
80 2019-11-12 Jan Beulich <jbeulich@suse.com>
82 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
84 (operand_types): Remove EsSeg entry.
85 (main): Replace stale use of OTMax.
86 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
87 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
89 (OTUnused): Comment out.
90 (union i386_operand_type): Remove esseg field.
91 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
92 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
93 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
94 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
95 * i386-init.h, i386-tbl.h: Re-generate.
97 2019-11-12 Jan Beulich <jbeulich@suse.com>
99 * i386-gen.c (operand_instances): Add RegB entry.
100 * i386-opc.h (enum operand_instance): Add RegB.
101 * i386-opc.tbl (RegC, RegD, RegB): Define.
102 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
103 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
104 monitorx, mwaitx): Drop ImmExt and convert encodings
106 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
107 (edx, rdx): Add Instance=RegD.
108 (ebx, rbx): Add Instance=RegB.
109 * i386-tbl.h: Re-generate.
111 2019-11-12 Jan Beulich <jbeulich@suse.com>
113 * i386-gen.c (operand_type_init): Adjust
114 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
115 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
116 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
117 (operand_instances): New.
118 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
119 (output_operand_type): New parameter "instance". Process it.
120 (process_i386_operand_type): New local variable "instance".
121 (main): Adjust static assertions.
122 * i386-opc.h (INSTANCE_WIDTH): Define.
123 (enum operand_instance): New.
124 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
125 (union i386_operand_type): Replace acc, inoutportreg, and
126 shiftcount by instance.
127 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
128 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
130 * i386-init.h, i386-tbl.h: Re-generate.
132 2019-11-11 Jan Beulich <jbeulich@suse.com>
134 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
135 smaxp/sminp entries' "tied_operand" field to 2.
137 2019-11-11 Jan Beulich <jbeulich@suse.com>
139 * aarch64-opc.c (operand_general_constraint_met_p): Replace
140 "index" local variable by that of the already existing "num".
142 2019-11-08 H.J. Lu <hongjiu.lu@intel.com>
145 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
146 * i386-tbl.h: Regenerated.
148 2019-11-08 Jan Beulich <jbeulich@suse.com>
150 * i386-gen.c (operand_type_init): Add Class= to
151 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
152 OPERAND_TYPE_REGBND entry.
153 (operand_classes): Add RegMask and RegBND entries.
154 (operand_types): Drop RegMask and RegBND entry.
155 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
156 (RegMask, RegBND): Delete.
157 (union i386_operand_type): Remove regmask and regbnd fields.
158 * i386-opc.tbl (RegMask, RegBND): Define.
159 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
161 * i386-init.h, i386-tbl.h: Re-generate.
163 2019-11-08 Jan Beulich <jbeulich@suse.com>
165 * i386-gen.c (operand_type_init): Add Class= to
166 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
167 OPERAND_TYPE_REGZMM entries.
168 (operand_classes): Add RegMMX and RegSIMD entries.
169 (operand_types): Drop RegMMX and RegSIMD entries.
170 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
171 (RegMMX, RegSIMD): Delete.
172 (union i386_operand_type): Remove regmmx and regsimd fields.
173 * i386-opc.tbl (RegMMX): Define.
174 (RegXMM, RegYMM, RegZMM): Add Class=.
175 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
177 * i386-init.h, i386-tbl.h: Re-generate.
179 2019-11-08 Jan Beulich <jbeulich@suse.com>
181 * i386-gen.c (operand_type_init): Add Class= to
182 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
184 (operand_classes): Add RegCR, RegDR, and RegTR entries.
185 (operand_types): Drop Control, Debug, and Test entries.
186 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
187 (Control, Debug, Test): Delete.
188 (union i386_operand_type): Remove control, debug, and test
190 * i386-opc.tbl (Control, Debug, Test): Define.
191 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
192 Class=RegDR, and Test by Class=RegTR.
193 * i386-init.h, i386-tbl.h: Re-generate.
195 2019-11-08 Jan Beulich <jbeulich@suse.com>
197 * i386-gen.c (operand_type_init): Add Class= to
198 OPERAND_TYPE_SREG entry.
199 (operand_classes): Add SReg entry.
200 (operand_types): Drop SReg entry.
201 * i386-opc.h (enum operand_class): Add SReg.
203 (union i386_operand_type): Remove sreg field.
204 * i386-opc.tbl (SReg): Define.
205 * i386-reg.tbl: Replace SReg by Class=SReg.
206 * i386-init.h, i386-tbl.h: Re-generate.
208 2019-11-08 Jan Beulich <jbeulich@suse.com>
210 * i386-gen.c (operand_type_init): Add Class=. New
211 OPERAND_TYPE_ANYIMM entry.
212 (operand_classes): New.
213 (operand_types): Drop Reg entry.
214 (output_operand_type): New parameter "class". Process it.
215 (process_i386_operand_type): New local variable "class".
216 (main): Adjust static assertions.
217 * i386-opc.h (CLASS_WIDTH): Define.
218 (enum operand_class): New.
219 (Reg): Replace by Class. Adjust comment.
220 (union i386_operand_type): Replace reg by class.
221 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
223 * i386-reg.tbl: Replace Reg by Class=Reg.
224 * i386-init.h: Re-generate.
226 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
228 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
229 (aarch64_opcode_table): Add data gathering hint mnemonic.
230 * opcodes/aarch64-dis-2.c: Account for new instruction.
232 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
234 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
237 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
239 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
240 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
241 aarch64_feature_f64mm): New feature sets.
242 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
243 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
245 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
247 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
248 (OP_SVE_QQQ): New qualifier.
249 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
250 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
251 the movprfx constraint.
252 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
253 (aarch64_opcode_table): Define new instructions smmla,
254 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
256 * aarch64-opc.c (operand_general_constraint_met_p): Handle
257 AARCH64_OPND_SVE_ADDR_RI_S4x32.
258 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
259 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
260 Account for new instructions.
261 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
263 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
265 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
266 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
268 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
270 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
271 (neon_opcodes): Add bfloat SIMD instructions.
272 (print_insn_coprocessor): Add new control character %b to print
273 condition code without checking cp_num.
274 (print_insn_neon): Account for BFloat16 instructions that have no
275 special top-byte handling.
277 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
278 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
280 * arm-dis.c (print_insn_coprocessor,
281 print_insn_generic_coprocessor): Create wrapper functions around
282 the implementation of the print_insn_coprocessor control codes.
283 (print_insn_coprocessor_1): Original print_insn_coprocessor
284 function that now takes which array to look at as an argument.
285 (print_insn_arm): Use both print_insn_coprocessor and
286 print_insn_generic_coprocessor.
287 (print_insn_thumb32): As above.
289 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
290 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
292 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
293 in reglane special case.
294 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
295 aarch64_find_next_opcode): Account for new instructions.
296 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
297 in reglane special case.
298 * aarch64-opc.c (struct operand_qualifier_data): Add data for
299 new AARCH64_OPND_QLF_S_2H qualifier.
300 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
301 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
302 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
304 (BFLOAT_SVE, BFLOAT): New feature set macros.
305 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
307 (aarch64_opcode_table): Define new instructions bfdot,
308 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
311 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
312 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
314 * aarch64-tbl.h (ARMV8_6): New macro.
316 2019-11-07 Jan Beulich <jbeulich@suse.com>
318 * i386-dis.c (prefix_table): Add mcommit.
319 (rm_table): Add rdpru.
320 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
321 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
322 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
323 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
324 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
325 * i386-opc.tbl (mcommit, rdpru): New.
326 * i386-init.h, i386-tbl.h: Re-generate.
328 2019-11-07 Jan Beulich <jbeulich@suse.com>
330 * i386-dis.c (OP_Mwait): Drop local variable "names", use
332 (OP_Monitor): Drop local variable "op1_names", re-purpose
333 "names" for it instead, and replace former "names" uses by
336 2019-11-07 Jan Beulich <jbeulich@suse.com>
339 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
341 * opcodes/i386-tbl.h: Re-generate.
343 2019-11-05 Jan Beulich <jbeulich@suse.com>
345 * i386-dis.c (OP_Mwaitx): Delete.
346 (prefix_table): Use OP_Mwait for mwaitx entry.
347 (OP_Mwait): Also handle mwaitx.
349 2019-11-05 Jan Beulich <jbeulich@suse.com>
351 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
352 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
353 (prefix_table): Add respective entries.
354 (rm_table): Link to those entries.
356 2019-11-05 Jan Beulich <jbeulich@suse.com>
358 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
359 (REG_0F1C_P_0_MOD_0): ... this.
360 (REG_0F1E_MOD_3): Rename to ...
361 (REG_0F1E_P_1_MOD_3): ... this.
362 (RM_0F01_REG_5): Rename to ...
363 (RM_0F01_REG_5_MOD_3): ... this.
364 (RM_0F01_REG_7): Rename to ...
365 (RM_0F01_REG_7_MOD_3): ... this.
366 (RM_0F1E_MOD_3_REG_7): Rename to ...
367 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
368 (RM_0FAE_REG_6): Rename to ...
369 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
370 (RM_0FAE_REG_7): Rename to ...
371 (RM_0FAE_REG_7_MOD_3): ... this.
372 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
373 (PREFIX_0F01_REG_5_MOD_0): ... this.
374 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
375 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
376 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
377 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
378 (PREFIX_0FAE_REG_0): Rename to ...
379 (PREFIX_0FAE_REG_0_MOD_3): ... this.
380 (PREFIX_0FAE_REG_1): Rename to ...
381 (PREFIX_0FAE_REG_1_MOD_3): ... this.
382 (PREFIX_0FAE_REG_2): Rename to ...
383 (PREFIX_0FAE_REG_2_MOD_3): ... this.
384 (PREFIX_0FAE_REG_3): Rename to ...
385 (PREFIX_0FAE_REG_3_MOD_3): ... this.
386 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
387 (PREFIX_0FAE_REG_4_MOD_0): ... this.
388 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
389 (PREFIX_0FAE_REG_4_MOD_3): ... this.
390 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
391 (PREFIX_0FAE_REG_5_MOD_0): ... this.
392 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
393 (PREFIX_0FAE_REG_5_MOD_3): ... this.
394 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
395 (PREFIX_0FAE_REG_6_MOD_0): ... this.
396 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
397 (PREFIX_0FAE_REG_6_MOD_3): ... this.
398 (PREFIX_0FAE_REG_7): Rename to ...
399 (PREFIX_0FAE_REG_7_MOD_0): ... this.
400 (PREFIX_MOD_0_0FC3): Rename to ...
401 (PREFIX_0FC3_MOD_0): ... this.
402 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
403 (PREFIX_0FC7_REG_6_MOD_0): ... this.
404 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
405 (PREFIX_0FC7_REG_6_MOD_3): ... this.
406 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
407 (PREFIX_0FC7_REG_7_MOD_3): ... this.
408 (reg_table, prefix_table, mod_table, rm_table): Adjust
411 2019-11-04 Nick Clifton <nickc@redhat.com>
413 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
414 of a v850 system register. Move the v850_sreg_names array into
416 (get_v850_reg_name): Likewise for ordinary register names.
417 (get_v850_vreg_name): Likewise for vector register names.
418 (get_v850_cc_name): Likewise for condition codes.
419 * get_v850_float_cc_name): Likewise for floating point condition
421 (get_v850_cacheop_name): Likewise for cache-ops.
422 (get_v850_prefop_name): Likewise for pref-ops.
423 (disassemble): Use the new accessor functions.
425 2019-10-30 Delia Burduv <delia.burduv@arm.com>
427 * aarch64-opc.c (print_immediate_offset_address): Don't print the
428 immediate for the writeback form of ldraa/ldrab if it is 0.
429 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
430 * aarch64-opc-2.c: Regenerated.
432 2019-10-30 Jan Beulich <jbeulich@suse.com>
434 * i386-gen.c (operand_type_shorthands): Delete.
435 (operand_type_init): Expand previous shorthands.
436 (set_bitfield_from_shorthand): Rename back to ...
437 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
438 of operand_type_init[].
439 (set_bitfield): Adjust call to the above function.
440 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
441 RegXMM, RegYMM, RegZMM): Define.
442 * i386-reg.tbl: Expand prior shorthands.
444 2019-10-30 Jan Beulich <jbeulich@suse.com>
446 * i386-gen.c (output_i386_opcode): Change order of fields
448 * i386-opc.h (struct insn_template): Move operands field.
449 Convert extension_opcode field to unsigned short.
450 * i386-tbl.h: Re-generate.
452 2019-10-30 Jan Beulich <jbeulich@suse.com>
454 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
456 * i386-opc.h (W): Extend comment.
457 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
458 general purpose variants not allowing for byte operands.
459 * i386-tbl.h: Re-generate.
461 2019-10-29 Nick Clifton <nickc@redhat.com>
463 * tic30-dis.c (print_branch): Correct size of operand array.
465 2019-10-29 Nick Clifton <nickc@redhat.com>
467 * d30v-dis.c (print_insn): Check that operand index is valid
468 before attempting to access the operands array.
470 2019-10-29 Nick Clifton <nickc@redhat.com>
472 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
473 locating the bit to be tested.
475 2019-10-29 Nick Clifton <nickc@redhat.com>
477 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
479 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
480 (print_insn_s12z): Check for illegal size values.
482 2019-10-28 Nick Clifton <nickc@redhat.com>
484 * csky-dis.c (csky_chars_to_number): Check for a negative
485 count. Use an unsigned integer to construct the return value.
487 2019-10-28 Nick Clifton <nickc@redhat.com>
489 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
490 operand buffer. Set value to 15 not 13.
491 (get_register_operand): Use OPERAND_BUFFER_LEN.
492 (get_indirect_operand): Likewise.
493 (print_two_operand): Likewise.
494 (print_three_operand): Likewise.
495 (print_oar_insn): Likewise.
497 2019-10-28 Nick Clifton <nickc@redhat.com>
499 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
500 (bit_extract_simple): Likewise.
501 (bit_copy): Likewise.
502 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
503 index_offset array are not accessed.
505 2019-10-28 Nick Clifton <nickc@redhat.com>
507 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
510 2019-10-25 Nick Clifton <nickc@redhat.com>
512 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
513 access to opcodes.op array element.
515 2019-10-23 Nick Clifton <nickc@redhat.com>
517 * rx-dis.c (get_register_name): Fix spelling typo in error
519 (get_condition_name, get_flag_name, get_double_register_name)
520 (get_double_register_high_name, get_double_register_low_name)
521 (get_double_control_register_name, get_double_condition_name)
522 (get_opsize_name, get_size_name): Likewise.
524 2019-10-22 Nick Clifton <nickc@redhat.com>
526 * rx-dis.c (get_size_name): New function. Provides safe
527 access to name array.
528 (get_opsize_name): Likewise.
529 (print_insn_rx): Use the accessor functions.
531 2019-10-16 Nick Clifton <nickc@redhat.com>
533 * rx-dis.c (get_register_name): New function. Provides safe
534 access to name array.
535 (get_condition_name, get_flag_name, get_double_register_name)
536 (get_double_register_high_name, get_double_register_low_name)
537 (get_double_control_register_name, get_double_condition_name):
539 (print_insn_rx): Use the accessor functions.
541 2019-10-09 Nick Clifton <nickc@redhat.com>
544 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
547 2019-10-07 Jan Beulich <jbeulich@suse.com>
549 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
550 (cmpsd): Likewise. Move EsSeg to other operand.
551 * opcodes/i386-tbl.h: Re-generate.
553 2019-09-23 Alan Modra <amodra@gmail.com>
555 * m68k-dis.c: Include cpu-m68k.h
557 2019-09-23 Alan Modra <amodra@gmail.com>
559 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
560 "elf/mips.h" earlier.
562 2018-09-20 Jan Beulich <jbeulich@suse.com>
565 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
567 * i386-tbl.h: Re-generate.
569 2019-09-18 Alan Modra <amodra@gmail.com>
571 * arc-ext.c: Update throughout for bfd section macro changes.
573 2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
575 * Makefile.in: Re-generate.
576 * configure: Re-generate.
578 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
580 * riscv-opc.c (riscv_opcodes): Change subset field
581 to insn_class field for all instructions.
582 (riscv_insn_types): Likewise.
584 2019-09-16 Phil Blundell <pb@pbcl.net>
586 * configure: Regenerated.
588 2019-09-10 Miod Vallat <miod@online.fr>
591 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
593 2019-09-09 Phil Blundell <pb@pbcl.net>
595 binutils 2.33 branch created.
597 2019-09-03 Nick Clifton <nickc@redhat.com>
600 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
601 greater than zero before indexing via (bufcnt -1).
603 2019-09-03 Nick Clifton <nickc@redhat.com>
606 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
607 (MAX_SPEC_REG_NAME_LEN): Define.
608 (struct mmix_dis_info): Use defined constants for array lengths.
609 (get_reg_name): New function.
610 (get_sprec_reg_name): New function.
611 (print_insn_mmix): Use new functions.
613 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
615 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
616 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
617 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
619 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
621 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
622 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
623 (aarch64_sys_reg_supported_p): Update checks for the above.
625 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
627 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
628 cases MVE_SQRSHRL and MVE_UQRSHLL.
629 (print_insn_mve): Add case for specifier 'k' to check
630 specific bit of the instruction.
632 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
635 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
636 encountering an unknown machine type.
637 (print_insn_arc): Handle arc_insn_length returning 0. In error
638 cases return -1 rather than calling abort.
640 2019-08-07 Jan Beulich <jbeulich@suse.com>
642 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
643 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
645 * i386-tbl.h: Re-generate.
647 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
649 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
652 2019-07-30 Mel Chen <mel.chen@sifive.com>
654 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
655 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
657 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
660 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
662 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
663 and MPY class instructions.
664 (parse_option): Add nps400 option.
665 (print_arc_disassembler_options): Add nps400 info.
667 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
669 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
672 * arc-opc.c (RAD_CHK): Add.
673 * arc-tbl.h: Regenerate.
675 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
677 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
678 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
680 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
682 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
683 instructions as UNPREDICTABLE.
685 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
687 * bpf-desc.c: Regenerated.
689 2019-07-17 Jan Beulich <jbeulich@suse.com>
691 * i386-gen.c (static_assert): Define.
693 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
694 (Opcode_Modifier_Num): ... this.
697 2019-07-16 Jan Beulich <jbeulich@suse.com>
699 * i386-gen.c (operand_types): Move RegMem ...
700 (opcode_modifiers): ... here.
701 * i386-opc.h (RegMem): Move to opcode modifer enum.
702 (union i386_operand_type): Move regmem field ...
703 (struct i386_opcode_modifier): ... here.
704 * i386-opc.tbl (RegMem): Define.
705 (mov, movq): Move RegMem on segment, control, debug, and test
707 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
708 to non-SSE2AVX flavor.
709 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
710 Move RegMem on register only flavors. Drop IgnoreSize from
711 legacy encoding flavors.
712 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
714 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
715 register only flavors.
716 (vmovd): Move RegMem and drop IgnoreSize on register only
717 flavor. Change opcode and operand order to store form.
718 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
720 2019-07-16 Jan Beulich <jbeulich@suse.com>
722 * i386-gen.c (operand_type_init, operand_types): Replace SReg
724 * i386-opc.h (SReg2, SReg3): Replace by ...
726 (union i386_operand_type): Replace sreg fields.
727 * i386-opc.tbl (mov, ): Use SReg.
728 (push, pop): Likewies. Drop i386 and x86-64 specific segment
730 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
731 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
733 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
735 * bpf-desc.c: Regenerate.
736 * bpf-opc.c: Likewise.
737 * bpf-opc.h: Likewise.
739 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
741 * bpf-desc.c: Regenerate.
742 * bpf-opc.c: Likewise.
744 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
746 * arm-dis.c (print_insn_coprocessor): Rename index to
749 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
751 * riscv-opc.c (riscv_insn_types): Add r4 type.
753 * riscv-opc.c (riscv_insn_types): Add b and j type.
755 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
756 format for sb type and correct s type.
758 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
760 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
761 SVE FMOV alias of FCPY.
763 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
765 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
766 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
768 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
770 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
771 registers in an instruction prefixed by MOVPRFX.
773 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
775 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
776 sve_size_13 icode to account for variant behaviour of
778 * aarch64-dis-2.c: Regenerate.
779 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
780 sve_size_13 icode to account for variant behaviour of
782 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
783 (OP_SVE_VVV_Q_D): Add new qualifier.
784 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
785 (struct aarch64_opcode): Split pmull{t,b} into those requiring
788 2019-07-01 Jan Beulich <jbeulich@suse.com>
790 * opcodes/i386-gen.c (operand_type_init): Remove
791 OPERAND_TYPE_VEC_IMM4 entry.
792 (operand_types): Remove Vec_Imm4.
793 * opcodes/i386-opc.h (Vec_Imm4): Delete.
794 (union i386_operand_type): Remove vec_imm4.
795 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
796 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
798 2019-07-01 Jan Beulich <jbeulich@suse.com>
800 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
801 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
802 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
803 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
804 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
805 monitorx, mwaitx): Drop ImmExt from operand-less forms.
806 * i386-tbl.h: Re-generate.
808 2019-07-01 Jan Beulich <jbeulich@suse.com>
810 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
812 * i386-tbl.h: Re-generate.
814 2019-07-01 Jan Beulich <jbeulich@suse.com>
816 * i386-opc.tbl (C): New.
817 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
818 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
819 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
820 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
821 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
822 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
823 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
824 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
825 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
826 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
827 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
828 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
829 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
830 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
831 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
832 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
833 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
834 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
835 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
836 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
837 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
838 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
839 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
840 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
841 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
842 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
844 * i386-tbl.h: Re-generate.
846 2019-07-01 Jan Beulich <jbeulich@suse.com>
848 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
850 * i386-tbl.h: Re-generate.
852 2019-07-01 Jan Beulich <jbeulich@suse.com>
854 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
855 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
856 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
857 * i386-tbl.h: Re-generate.
859 2019-07-01 Jan Beulich <jbeulich@suse.com>
861 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
862 Disp8MemShift from register only templates.
863 * i386-tbl.h: Re-generate.
865 2019-07-01 Jan Beulich <jbeulich@suse.com>
867 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
868 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
869 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
870 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
871 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
872 EVEX_W_0F11_P_3_M_1): Delete.
873 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
874 EVEX_W_0F11_P_3): New.
875 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
876 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
877 MOD_EVEX_0F11_PREFIX_3 table entries.
878 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
879 PREFIX_EVEX_0F11 table entries.
880 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
881 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
882 EVEX_W_0F11_P_3_M_{0,1} table entries.
884 2019-07-01 Jan Beulich <jbeulich@suse.com>
886 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
889 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
892 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
893 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
894 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
895 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
896 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
897 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
898 EVEX_LEN_0F38C7_R_6_P_2_W_1.
899 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
900 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
901 PREFIX_EVEX_0F38C6_REG_6 entries.
902 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
903 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
904 EVEX_W_0F38C7_R_6_P_2 entries.
905 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
906 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
907 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
908 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
909 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
910 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
911 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
913 2019-06-27 Jan Beulich <jbeulich@suse.com>
915 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
916 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
917 VEX_LEN_0F2D_P_3): Delete.
918 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
919 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
920 (prefix_table): ... here.
922 2019-06-27 Jan Beulich <jbeulich@suse.com>
924 * i386-dis.c (Iq): Delete.
926 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
928 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
929 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
930 (OP_E_memory): Also honor needindex when deciding whether an
931 address size prefix needs printing.
932 (OP_I): Remove handling of q_mode. Add handling of d_mode.
934 2019-06-26 Jim Wilson <jimw@sifive.com>
937 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
938 Set info->display_endian to info->endian_code.
940 2019-06-25 Jan Beulich <jbeulich@suse.com>
942 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
943 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
944 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
945 OPERAND_TYPE_ACC64 entries.
946 * i386-init.h: Re-generate.
948 2019-06-25 Jan Beulich <jbeulich@suse.com>
950 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
952 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
954 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
956 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
957 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
959 2019-06-25 Jan Beulich <jbeulich@suse.com>
961 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
964 2019-06-25 Jan Beulich <jbeulich@suse.com>
966 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
967 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
969 * i386-opc.tbl (movnti): Add IgnoreSize.
970 * i386-tbl.h: Re-generate.
972 2019-06-25 Jan Beulich <jbeulich@suse.com>
974 * i386-opc.tbl (and): Mark Imm8S form for optimization.
975 * i386-tbl.h: Re-generate.
977 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
979 * i386-dis-evex.h: Break into ...
980 * i386-dis-evex-len.h: New file.
981 * i386-dis-evex-mod.h: Likewise.
982 * i386-dis-evex-prefix.h: Likewise.
983 * i386-dis-evex-reg.h: Likewise.
984 * i386-dis-evex-w.h: Likewise.
985 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
986 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
989 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
992 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
993 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
995 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
996 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
997 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
998 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
999 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1000 EVEX_LEN_0F385B_P_2_W_1.
1001 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1002 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1003 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1004 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1005 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1006 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1007 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1008 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1009 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1010 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1012 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1015 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1016 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1017 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1018 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1019 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1020 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1021 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1022 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1023 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1024 EVEX_LEN_0F3A43_P_2_W_1.
1025 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1026 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1027 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1028 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1029 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1030 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1031 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1032 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1033 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1034 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1035 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1036 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1038 2019-06-14 Nick Clifton <nickc@redhat.com>
1040 * po/fr.po; Updated French translation.
1042 2019-06-13 Stafford Horne <shorne@gmail.com>
1044 * or1k-asm.c: Regenerated.
1045 * or1k-desc.c: Regenerated.
1046 * or1k-desc.h: Regenerated.
1047 * or1k-dis.c: Regenerated.
1048 * or1k-ibld.c: Regenerated.
1049 * or1k-opc.c: Regenerated.
1050 * or1k-opc.h: Regenerated.
1051 * or1k-opinst.c: Regenerated.
1053 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
1055 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1057 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1060 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1061 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1062 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1063 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1064 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1065 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1066 EVEX_LEN_0F3A1B_P_2_W_1.
1067 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1068 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1069 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1070 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1071 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1072 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1073 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1074 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1076 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1079 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1080 EVEX.vvvv when disassembling VEX and EVEX instructions.
1081 (OP_VEX): Set vex.register_specifier to 0 after readding
1082 vex.register_specifier.
1083 (OP_Vex_2src_1): Likewise.
1084 (OP_Vex_2src_2): Likewise.
1085 (OP_LWP_E): Likewise.
1086 (OP_EX_Vex): Don't check vex.register_specifier.
1087 (OP_XMM_Vex): Likewise.
1089 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1090 Lili Cui <lili.cui@intel.com>
1092 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1093 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1095 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1096 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1097 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1098 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1099 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1100 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1101 * i386-init.h: Regenerated.
1102 * i386-tbl.h: Likewise.
1104 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1105 Lili Cui <lili.cui@intel.com>
1107 * doc/c-i386.texi: Document enqcmd.
1108 * testsuite/gas/i386/enqcmd-intel.d: New file.
1109 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1110 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1111 * testsuite/gas/i386/enqcmd.d: Likewise.
1112 * testsuite/gas/i386/enqcmd.s: Likewise.
1113 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1114 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1115 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1116 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1117 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1118 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1119 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1122 2019-06-04 Alan Hayward <alan.hayward@arm.com>
1124 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1126 2019-06-03 Alan Modra <amodra@gmail.com>
1128 * ppc-dis.c (prefix_opcd_indices): Correct size.
1130 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1133 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1135 * i386-tbl.h: Regenerated.
1137 2019-05-24 Alan Modra <amodra@gmail.com>
1139 * po/POTFILES.in: Regenerate.
1141 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1142 Alan Modra <amodra@gmail.com>
1144 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1145 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1146 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1147 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1148 XTOP>): Define and add entries.
1149 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1150 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1151 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1152 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1154 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1155 Alan Modra <amodra@gmail.com>
1157 * ppc-dis.c (ppc_opts): Add "future" entry.
1158 (PREFIX_OPCD_SEGS): Define.
1159 (prefix_opcd_indices): New array.
1160 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1161 (lookup_prefix): New function.
1162 (print_insn_powerpc): Handle 64-bit prefix instructions.
1163 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1164 (PMRR, POWERXX): Define.
1165 (prefix_opcodes): New instruction table.
1166 (prefix_num_opcodes): New constant.
1168 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1170 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1171 * configure: Regenerated.
1172 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1174 (HFILES): Add bpf-desc.h and bpf-opc.h.
1175 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1176 bpf-ibld.c and bpf-opc.c.
1178 * Makefile.in: Regenerated.
1179 * disassemble.c (ARCH_bpf): Define.
1180 (disassembler): Add case for bfd_arch_bpf.
1181 (disassemble_init_for_target): Likewise.
1182 (enum epbf_isa_attr): Define.
1183 * disassemble.h: extern print_insn_bpf.
1184 * bpf-asm.c: Generated.
1185 * bpf-opc.h: Likewise.
1186 * bpf-opc.c: Likewise.
1187 * bpf-ibld.c: Likewise.
1188 * bpf-dis.c: Likewise.
1189 * bpf-desc.h: Likewise.
1190 * bpf-desc.c: Likewise.
1192 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1194 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1195 and VMSR with the new operands.
1197 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1199 * arm-dis.c (enum mve_instructions): New enum
1200 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1202 (mve_opcodes): New instructions as above.
1203 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1205 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1207 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1209 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1210 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1211 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1212 uqshl, urshrl and urshr.
1213 (is_mve_okay_in_it): Add new instructions to TRUE list.
1214 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1215 (print_insn_mve): Updated to accept new %j,
1216 %<bitfield>m and %<bitfield>n patterns.
1218 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1220 * mips-opc.c (mips_builtin_opcodes): Change source register
1221 constraint for DAUI.
1223 2019-05-20 Nick Clifton <nickc@redhat.com>
1225 * po/fr.po: Updated French translation.
1227 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1228 Michael Collison <michael.collison@arm.com>
1230 * arm-dis.c (thumb32_opcodes): Add new instructions.
1231 (enum mve_instructions): Likewise.
1232 (enum mve_undefined): Add new reasons.
1233 (is_mve_encoding_conflict): Handle new instructions.
1234 (is_mve_undefined): Likewise.
1235 (is_mve_unpredictable): Likewise.
1236 (print_mve_undefined): Likewise.
1237 (print_mve_size): Likewise.
1239 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1240 Michael Collison <michael.collison@arm.com>
1242 * arm-dis.c (thumb32_opcodes): Add new instructions.
1243 (enum mve_instructions): Likewise.
1244 (is_mve_encoding_conflict): Handle new instructions.
1245 (is_mve_undefined): Likewise.
1246 (is_mve_unpredictable): Likewise.
1247 (print_mve_size): Likewise.
1249 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1250 Michael Collison <michael.collison@arm.com>
1252 * arm-dis.c (thumb32_opcodes): Add new instructions.
1253 (enum mve_instructions): Likewise.
1254 (is_mve_encoding_conflict): Likewise.
1255 (is_mve_unpredictable): Likewise.
1256 (print_mve_size): Likewise.
1258 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1259 Michael Collison <michael.collison@arm.com>
1261 * arm-dis.c (thumb32_opcodes): Add new instructions.
1262 (enum mve_instructions): Likewise.
1263 (is_mve_encoding_conflict): Handle new instructions.
1264 (is_mve_undefined): Likewise.
1265 (is_mve_unpredictable): Likewise.
1266 (print_mve_size): Likewise.
1268 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1269 Michael Collison <michael.collison@arm.com>
1271 * arm-dis.c (thumb32_opcodes): Add new instructions.
1272 (enum mve_instructions): Likewise.
1273 (is_mve_encoding_conflict): Handle new instructions.
1274 (is_mve_undefined): Likewise.
1275 (is_mve_unpredictable): Likewise.
1276 (print_mve_size): Likewise.
1277 (print_insn_mve): Likewise.
1279 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1280 Michael Collison <michael.collison@arm.com>
1282 * arm-dis.c (thumb32_opcodes): Add new instructions.
1283 (print_insn_thumb32): Handle new instructions.
1285 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1286 Michael Collison <michael.collison@arm.com>
1288 * arm-dis.c (enum mve_instructions): Add new instructions.
1289 (enum mve_undefined): Add new reasons.
1290 (is_mve_encoding_conflict): Handle new instructions.
1291 (is_mve_undefined): Likewise.
1292 (is_mve_unpredictable): Likewise.
1293 (print_mve_undefined): Likewise.
1294 (print_mve_size): Likewise.
1295 (print_mve_shift_n): Likewise.
1296 (print_insn_mve): Likewise.
1298 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1299 Michael Collison <michael.collison@arm.com>
1301 * arm-dis.c (enum mve_instructions): Add new instructions.
1302 (is_mve_encoding_conflict): Handle new instructions.
1303 (is_mve_unpredictable): Likewise.
1304 (print_mve_rotate): Likewise.
1305 (print_mve_size): Likewise.
1306 (print_insn_mve): Likewise.
1308 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1309 Michael Collison <michael.collison@arm.com>
1311 * arm-dis.c (enum mve_instructions): Add new instructions.
1312 (is_mve_encoding_conflict): Handle new instructions.
1313 (is_mve_unpredictable): Likewise.
1314 (print_mve_size): Likewise.
1315 (print_insn_mve): Likewise.
1317 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1318 Michael Collison <michael.collison@arm.com>
1320 * arm-dis.c (enum mve_instructions): Add new instructions.
1321 (enum mve_undefined): Add new reasons.
1322 (is_mve_encoding_conflict): Handle new instructions.
1323 (is_mve_undefined): Likewise.
1324 (is_mve_unpredictable): Likewise.
1325 (print_mve_undefined): Likewise.
1326 (print_mve_size): Likewise.
1327 (print_insn_mve): Likewise.
1329 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1330 Michael Collison <michael.collison@arm.com>
1332 * arm-dis.c (enum mve_instructions): Add new instructions.
1333 (is_mve_encoding_conflict): Handle new instructions.
1334 (is_mve_undefined): Likewise.
1335 (is_mve_unpredictable): Likewise.
1336 (print_mve_size): Likewise.
1337 (print_insn_mve): Likewise.
1339 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1340 Michael Collison <michael.collison@arm.com>
1342 * arm-dis.c (enum mve_instructions): Add new instructions.
1343 (enum mve_unpredictable): Add new reasons.
1344 (enum mve_undefined): Likewise.
1345 (is_mve_okay_in_it): Handle new isntructions.
1346 (is_mve_encoding_conflict): Likewise.
1347 (is_mve_undefined): Likewise.
1348 (is_mve_unpredictable): Likewise.
1349 (print_mve_vmov_index): Likewise.
1350 (print_simd_imm8): Likewise.
1351 (print_mve_undefined): Likewise.
1352 (print_mve_unpredictable): Likewise.
1353 (print_mve_size): Likewise.
1354 (print_insn_mve): Likewise.
1356 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1357 Michael Collison <michael.collison@arm.com>
1359 * arm-dis.c (enum mve_instructions): Add new instructions.
1360 (enum mve_unpredictable): Add new reasons.
1361 (enum mve_undefined): Likewise.
1362 (is_mve_encoding_conflict): Handle new instructions.
1363 (is_mve_undefined): Likewise.
1364 (is_mve_unpredictable): Likewise.
1365 (print_mve_undefined): Likewise.
1366 (print_mve_unpredictable): Likewise.
1367 (print_mve_rounding_mode): Likewise.
1368 (print_mve_vcvt_size): Likewise.
1369 (print_mve_size): Likewise.
1370 (print_insn_mve): Likewise.
1372 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1373 Michael Collison <michael.collison@arm.com>
1375 * arm-dis.c (enum mve_instructions): Add new instructions.
1376 (enum mve_unpredictable): Add new reasons.
1377 (enum mve_undefined): Likewise.
1378 (is_mve_undefined): Handle new instructions.
1379 (is_mve_unpredictable): Likewise.
1380 (print_mve_undefined): Likewise.
1381 (print_mve_unpredictable): Likewise.
1382 (print_mve_size): Likewise.
1383 (print_insn_mve): Likewise.
1385 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1386 Michael Collison <michael.collison@arm.com>
1388 * arm-dis.c (enum mve_instructions): Add new instructions.
1389 (enum mve_undefined): Add new reasons.
1390 (insns): Add new instructions.
1391 (is_mve_encoding_conflict):
1392 (print_mve_vld_str_addr): New print function.
1393 (is_mve_undefined): Handle new instructions.
1394 (is_mve_unpredictable): Likewise.
1395 (print_mve_undefined): Likewise.
1396 (print_mve_size): Likewise.
1397 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1398 (print_insn_mve): Handle new operands.
1400 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1401 Michael Collison <michael.collison@arm.com>
1403 * arm-dis.c (enum mve_instructions): Add new instructions.
1404 (enum mve_unpredictable): Add new reasons.
1405 (is_mve_encoding_conflict): Handle new instructions.
1406 (is_mve_unpredictable): Likewise.
1407 (mve_opcodes): Add new instructions.
1408 (print_mve_unpredictable): Handle new reasons.
1409 (print_mve_register_blocks): New print function.
1410 (print_mve_size): Handle new instructions.
1411 (print_insn_mve): Likewise.
1413 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1414 Michael Collison <michael.collison@arm.com>
1416 * arm-dis.c (enum mve_instructions): Add new instructions.
1417 (enum mve_unpredictable): Add new reasons.
1418 (enum mve_undefined): Likewise.
1419 (is_mve_encoding_conflict): Handle new instructions.
1420 (is_mve_undefined): Likewise.
1421 (is_mve_unpredictable): Likewise.
1422 (coprocessor_opcodes): Move NEON VDUP from here...
1423 (neon_opcodes): ... to here.
1424 (mve_opcodes): Add new instructions.
1425 (print_mve_undefined): Handle new reasons.
1426 (print_mve_unpredictable): Likewise.
1427 (print_mve_size): Handle new instructions.
1428 (print_insn_neon): Handle vdup.
1429 (print_insn_mve): Handle new operands.
1431 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1432 Michael Collison <michael.collison@arm.com>
1434 * arm-dis.c (enum mve_instructions): Add new instructions.
1435 (enum mve_unpredictable): Add new values.
1436 (mve_opcodes): Add new instructions.
1437 (vec_condnames): New array with vector conditions.
1438 (mve_predicatenames): New array with predicate suffixes.
1439 (mve_vec_sizename): New array with vector sizes.
1440 (enum vpt_pred_state): New enum with vector predication states.
1441 (struct vpt_block): New struct type for vpt blocks.
1442 (vpt_block_state): Global struct to keep track of state.
1443 (mve_extract_pred_mask): New helper function.
1444 (num_instructions_vpt_block): Likewise.
1445 (mark_outside_vpt_block): Likewise.
1446 (mark_inside_vpt_block): Likewise.
1447 (invert_next_predicate_state): Likewise.
1448 (update_next_predicate_state): Likewise.
1449 (update_vpt_block_state): Likewise.
1450 (is_vpt_instruction): Likewise.
1451 (is_mve_encoding_conflict): Add entries for new instructions.
1452 (is_mve_unpredictable): Likewise.
1453 (print_mve_unpredictable): Handle new cases.
1454 (print_instruction_predicate): Likewise.
1455 (print_mve_size): New function.
1456 (print_vec_condition): New function.
1457 (print_insn_mve): Handle vpt blocks and new print operands.
1459 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1461 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1462 8, 14 and 15 for Armv8.1-M Mainline.
1464 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1465 Michael Collison <michael.collison@arm.com>
1467 * arm-dis.c (enum mve_instructions): New enum.
1468 (enum mve_unpredictable): Likewise.
1469 (enum mve_undefined): Likewise.
1470 (struct mopcode32): New struct.
1471 (is_mve_okay_in_it): New function.
1472 (is_mve_architecture): Likewise.
1473 (arm_decode_field): Likewise.
1474 (arm_decode_field_multiple): Likewise.
1475 (is_mve_encoding_conflict): Likewise.
1476 (is_mve_undefined): Likewise.
1477 (is_mve_unpredictable): Likewise.
1478 (print_mve_undefined): Likewise.
1479 (print_mve_unpredictable): Likewise.
1480 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1481 (print_insn_mve): New function.
1482 (print_insn_thumb32): Handle MVE architecture.
1483 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1485 2019-05-10 Nick Clifton <nickc@redhat.com>
1488 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1489 end of the table prematurely.
1491 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1493 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1496 2019-05-11 Alan Modra <amodra@gmail.com>
1498 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1499 when -Mraw is in effect.
1501 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1503 * aarch64-dis-2.c: Regenerate.
1504 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1505 (OP_SVE_BBB): New variant set.
1506 (OP_SVE_DDDD): New variant set.
1507 (OP_SVE_HHH): New variant set.
1508 (OP_SVE_HHHU): New variant set.
1509 (OP_SVE_SSS): New variant set.
1510 (OP_SVE_SSSU): New variant set.
1511 (OP_SVE_SHH): New variant set.
1512 (OP_SVE_SBBU): New variant set.
1513 (OP_SVE_DSS): New variant set.
1514 (OP_SVE_DHHU): New variant set.
1515 (OP_SVE_VMV_HSD_BHS): New variant set.
1516 (OP_SVE_VVU_HSD_BHS): New variant set.
1517 (OP_SVE_VVVU_SD_BH): New variant set.
1518 (OP_SVE_VVVU_BHSD): New variant set.
1519 (OP_SVE_VVV_QHD_DBS): New variant set.
1520 (OP_SVE_VVV_HSD_BHS): New variant set.
1521 (OP_SVE_VVV_HSD_BHS2): New variant set.
1522 (OP_SVE_VVV_BHS_HSD): New variant set.
1523 (OP_SVE_VV_BHS_HSD): New variant set.
1524 (OP_SVE_VVV_SD): New variant set.
1525 (OP_SVE_VVU_BHS_HSD): New variant set.
1526 (OP_SVE_VZVV_SD): New variant set.
1527 (OP_SVE_VZVV_BH): New variant set.
1528 (OP_SVE_VZV_SD): New variant set.
1529 (aarch64_opcode_table): Add sve2 instructions.
1531 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1533 * aarch64-asm-2.c: Regenerated.
1534 * aarch64-dis-2.c: Regenerated.
1535 * aarch64-opc-2.c: Regenerated.
1536 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1537 for SVE_SHLIMM_UNPRED_22.
1538 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1539 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1542 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1544 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1545 sve_size_tsz_bhs iclass encode.
1546 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1547 sve_size_tsz_bhs iclass decode.
1549 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1551 * aarch64-asm-2.c: Regenerated.
1552 * aarch64-dis-2.c: Regenerated.
1553 * aarch64-opc-2.c: Regenerated.
1554 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1555 for SVE_Zm4_11_INDEX.
1556 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1557 (fields): Handle SVE_i2h field.
1558 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1559 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1561 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1563 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1564 sve_shift_tsz_bhsd iclass encode.
1565 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1566 sve_shift_tsz_bhsd iclass decode.
1568 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1570 * aarch64-asm-2.c: Regenerated.
1571 * aarch64-dis-2.c: Regenerated.
1572 * aarch64-opc-2.c: Regenerated.
1573 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1574 (aarch64_encode_variant_using_iclass): Handle
1575 sve_shift_tsz_hsd iclass encode.
1576 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1577 sve_shift_tsz_hsd iclass decode.
1578 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1579 for SVE_SHRIMM_UNPRED_22.
1580 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1581 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1584 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1586 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1587 sve_size_013 iclass encode.
1588 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1589 sve_size_013 iclass decode.
1591 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1593 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1594 sve_size_bh iclass encode.
1595 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1596 sve_size_bh iclass decode.
1598 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1600 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1601 sve_size_sd2 iclass encode.
1602 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1603 sve_size_sd2 iclass decode.
1604 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1605 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1607 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1609 * aarch64-asm-2.c: Regenerated.
1610 * aarch64-dis-2.c: Regenerated.
1611 * aarch64-opc-2.c: Regenerated.
1612 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1614 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1615 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1617 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1619 * aarch64-asm-2.c: Regenerated.
1620 * aarch64-dis-2.c: Regenerated.
1621 * aarch64-opc-2.c: Regenerated.
1622 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1623 for SVE_Zm3_11_INDEX.
1624 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1625 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1626 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1628 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1630 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1632 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1633 sve_size_hsd2 iclass encode.
1634 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1635 sve_size_hsd2 iclass decode.
1636 * aarch64-opc.c (fields): Handle SVE_size field.
1637 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1639 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1641 * aarch64-asm-2.c: Regenerated.
1642 * aarch64-dis-2.c: Regenerated.
1643 * aarch64-opc-2.c: Regenerated.
1644 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1646 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1647 (fields): Handle SVE_rot3 field.
1648 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1649 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1651 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1653 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1656 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1659 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1660 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1661 aarch64_feature_sve2bitperm): New feature sets.
1662 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1663 for feature set addresses.
1664 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1665 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1667 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1668 Faraz Shahbazker <fshahbazker@wavecomp.com>
1670 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1671 argument and set ASE_EVA_R6 appropriately.
1672 (set_default_mips_dis_options): Pass ISA to above.
1673 (parse_mips_dis_option): Likewise.
1674 * mips-opc.c (EVAR6): New macro.
1675 (mips_builtin_opcodes): Add llwpe, scwpe.
1677 2019-05-01 Sudakshina Das <sudi.das@arm.com>
1679 * aarch64-asm-2.c: Regenerated.
1680 * aarch64-dis-2.c: Regenerated.
1681 * aarch64-opc-2.c: Regenerated.
1682 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1683 AARCH64_OPND_TME_UIMM16.
1684 (aarch64_print_operand): Likewise.
1685 * aarch64-tbl.h (QL_IMM_NIL): New.
1688 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1690 2019-04-29 John Darrington <john@darrington.wattle.id.au>
1692 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1694 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1695 Faraz Shahbazker <fshahbazker@wavecomp.com>
1697 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1699 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1701 * s12z-opc.h: Add extern "C" bracketing to help
1702 users who wish to use this interface in c++ code.
1704 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1706 * s12z-opc.c (bm_decode): Handle bit map operations with the
1709 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1711 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1712 specifier. Add entries for VLDR and VSTR of system registers.
1713 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1714 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1715 of %J and %K format specifier.
1717 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1719 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1720 Add new entries for VSCCLRM instruction.
1721 (print_insn_coprocessor): Handle new %C format control code.
1723 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1725 * arm-dis.c (enum isa): New enum.
1726 (struct sopcode32): New structure.
1727 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1728 set isa field of all current entries to ANY.
1729 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1730 Only match an entry if its isa field allows the current mode.
1732 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1734 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1736 (print_insn_thumb32): Add logic to print %n CLRM register list.
1738 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1740 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1743 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1745 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1746 (print_insn_thumb32): Edit the switch case for %Z.
1748 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1750 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1752 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1754 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1756 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1758 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1760 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1762 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1763 Arm register with r13 and r15 unpredictable.
1764 (thumb32_opcodes): New instructions for bfx and bflx.
1766 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1768 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1770 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1772 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1774 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1776 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1778 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1780 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1782 2019-04-12 John Darrington <john@darrington.wattle.id.au>
1784 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1785 "optr". ("operator" is a reserved word in c++).
1787 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1789 * aarch64-opc.c (aarch64_print_operand): Add case for
1791 (verify_constraints): Likewise.
1792 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1793 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1794 to accept Rt|SP as first operand.
1795 (AARCH64_OPERANDS): Add new Rt_SP.
1796 * aarch64-asm-2.c: Regenerated.
1797 * aarch64-dis-2.c: Regenerated.
1798 * aarch64-opc-2.c: Regenerated.
1800 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1802 * aarch64-asm-2.c: Regenerated.
1803 * aarch64-dis-2.c: Likewise.
1804 * aarch64-opc-2.c: Likewise.
1805 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1807 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1809 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1811 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1813 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1814 * i386-init.h: Regenerated.
1816 2019-04-07 Alan Modra <amodra@gmail.com>
1818 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1819 op_separator to control printing of spaces, comma and parens
1820 rather than need_comma, need_paren and spaces vars.
1822 2019-04-07 Alan Modra <amodra@gmail.com>
1825 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1826 (print_insn_neon, print_insn_arm): Likewise.
1828 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1830 * i386-dis-evex.h (evex_table): Updated to support BF16
1832 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1833 and EVEX_W_0F3872_P_3.
1834 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1835 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1836 * i386-opc.h (enum): Add CpuAVX512_BF16.
1837 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1838 * i386-opc.tbl: Add AVX512 BF16 instructions.
1839 * i386-init.h: Regenerated.
1840 * i386-tbl.h: Likewise.
1842 2019-04-05 Alan Modra <amodra@gmail.com>
1844 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1845 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1846 to favour printing of "-" branch hint when using the "y" bit.
1847 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1849 2019-04-05 Alan Modra <amodra@gmail.com>
1851 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1852 opcode until first operand is output.
1854 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1857 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1858 (valid_bo_post_v2): Add support for 'at' branch hints.
1859 (insert_bo): Only error on branch on ctr.
1860 (get_bo_hint_mask): New function.
1861 (insert_boe): Add new 'branch_taken' formal argument. Add support
1862 for inserting 'at' branch hints.
1863 (extract_boe): Add new 'branch_taken' formal argument. Add support
1864 for extracting 'at' branch hints.
1865 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1866 (BOE): Delete operand.
1867 (BOM, BOP): New operands.
1869 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1870 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1871 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1872 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1873 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1874 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1875 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1876 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1877 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1878 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1879 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1880 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1881 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1882 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1883 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1884 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1885 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1886 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1887 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1888 bttarl+>: New extended mnemonics.
1890 2019-03-28 Alan Modra <amodra@gmail.com>
1893 * ppc-opc.c (BTF): Define.
1894 (powerpc_opcodes): Use for mtfsb*.
1895 * ppc-dis.c (print_insn_powerpc): Print fields with both
1896 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1898 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1900 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1901 (mapping_symbol_for_insn): Implement new algorithm.
1902 (print_insn): Remove duplicate code.
1904 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1906 * aarch64-dis.c (print_insn_aarch64):
1909 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1911 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1914 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1916 * aarch64-dis.c (last_stop_offset): New.
1917 (print_insn_aarch64): Use stop_offset.
1919 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1922 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1924 * i386-init.h: Regenerated.
1926 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1929 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1930 vmovdqu16, vmovdqu32 and vmovdqu64.
1931 * i386-tbl.h: Regenerated.
1933 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1935 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1936 from vstrszb, vstrszh, and vstrszf.
1938 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1940 * s390-opc.txt: Add instruction descriptions.
1942 2019-02-08 Jim Wilson <jimw@sifive.com>
1944 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1947 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1949 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1951 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1954 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1955 * aarch64-opc.c (verify_elem_sd): New.
1956 (fields): Add FLD_sz entr.
1957 * aarch64-tbl.h (_SIMD_INSN): New.
1958 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1959 fmulx scalar and vector by element isns.
1961 2019-02-07 Nick Clifton <nickc@redhat.com>
1963 * po/sv.po: Updated Swedish translation.
1965 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1967 * s390-mkopc.c (main): Accept arch13 as cpu string.
1968 * s390-opc.c: Add new instruction formats and instruction opcode
1970 * s390-opc.txt: Add new arch13 instructions.
1972 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1974 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1975 (aarch64_opcode): Change encoding for stg, stzg
1977 * aarch64-asm-2.c: Regenerated.
1978 * aarch64-dis-2.c: Regenerated.
1979 * aarch64-opc-2.c: Regenerated.
1981 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1983 * aarch64-asm-2.c: Regenerated.
1984 * aarch64-dis-2.c: Likewise.
1985 * aarch64-opc-2.c: Likewise.
1986 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1988 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1989 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1991 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1992 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1993 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1994 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1995 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1996 case for ldstgv_indexed.
1997 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1998 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1999 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2000 * aarch64-asm-2.c: Regenerated.
2001 * aarch64-dis-2.c: Regenerated.
2002 * aarch64-opc-2.c: Regenerated.
2004 2019-01-23 Nick Clifton <nickc@redhat.com>
2006 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2008 2019-01-21 Nick Clifton <nickc@redhat.com>
2010 * po/de.po: Updated German translation.
2011 * po/uk.po: Updated Ukranian translation.
2013 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2014 * mips-dis.c (mips_arch_choices): Fix typo in
2015 gs464, gs464e and gs264e descriptors.
2017 2019-01-19 Nick Clifton <nickc@redhat.com>
2019 * configure: Regenerate.
2020 * po/opcodes.pot: Regenerate.
2022 2018-06-24 Nick Clifton <nickc@redhat.com>
2024 2.32 branch created.
2026 2019-01-09 John Darrington <john@darrington.wattle.id.au>
2028 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2030 -dis.c (opr_emit_disassembly): Do not omit an index if it is
2033 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2035 * configure: Regenerate.
2037 2019-01-07 Alan Modra <amodra@gmail.com>
2039 * configure: Regenerate.
2040 * po/POTFILES.in: Regenerate.
2042 2019-01-03 John Darrington <john@darrington.wattle.id.au>
2044 * s12z-opc.c: New file.
2045 * s12z-opc.h: New file.
2046 * s12z-dis.c: Removed all code not directly related to display
2047 of instructions. Used the interface provided by the new files
2049 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2050 * Makefile.in: Regenerate.
2051 * configure.ac (bfd_s12z_arch): Correct the dependencies.
2052 * configure: Regenerate.
2054 2019-01-01 Alan Modra <amodra@gmail.com>
2056 Update year range in copyright notice of all files.
2058 For older changes see ChangeLog-2018
2060 Copyright (C) 2019 Free Software Foundation, Inc.
2062 Copying and distribution of this file, with or without modification,
2063 are permitted in any medium without royalty provided the copyright
2064 notice and this notice are preserved.
2070 version-control: never