1 2019-12-08 Alan Modra <amodra@gmail.com>
3 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
6 2019-12-05 Jan Beulich <jbeulich@suse.com>
8 * aarch64-tbl.h (aarch64_feature_crypto,
9 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
10 CRYPTO_V8_2_INSN): Delete.
12 2019-12-05 Alan Modra <amodra@gmail.com>
15 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
16 (struct string_buf): New.
17 (strbuf): New function.
18 (get_field): Use strbuf rather than strdup of local temp.
19 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
20 (get_field_rfsl, get_field_imm15): Likewise.
21 (get_field_rd, get_field_r1, get_field_r2): Update macros.
22 (get_field_special): Likewise. Don't strcpy spr. Formatting.
23 (print_insn_microblaze): Formatting. Init and pass string_buf to
26 2019-12-04 Jan Beulich <jbeulich@suse.com>
28 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
29 * i386-tbl.h: Re-generate.
31 2019-12-04 Jan Beulich <jbeulich@suse.com>
33 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
35 2019-12-04 Jan Beulich <jbeulich@suse.com>
37 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
39 (xbegin): Drop DefaultSize.
40 * i386-tbl.h: Re-generate.
42 2019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
44 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
45 Change the coproc CRC conditions to use the extension
46 feature set, second word, base on ARM_EXT2_CRC.
48 2019-11-14 Jan Beulich <jbeulich@suse.com>
50 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
51 * i386-tbl.h: Re-generate.
53 2019-11-14 Jan Beulich <jbeulich@suse.com>
55 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
56 JumpInterSegment, and JumpAbsolute entries.
57 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
58 JUMP_ABSOLUTE): Define.
59 (struct i386_opcode_modifier): Extend jump field to 3 bits.
60 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
62 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
63 JumpInterSegment): Define.
64 * i386-tbl.h: Re-generate.
66 2019-11-14 Jan Beulich <jbeulich@suse.com>
68 * i386-gen.c (operand_type_init): Remove
69 OPERAND_TYPE_JUMPABSOLUTE entry.
70 (opcode_modifiers): Add JumpAbsolute entry.
71 (operand_types): Remove JumpAbsolute entry.
72 * i386-opc.h (JumpAbsolute): Move between enums.
73 (struct i386_opcode_modifier): Add jumpabsolute field.
74 (union i386_operand_type): Remove jumpabsolute field.
75 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
76 * i386-init.h, i386-tbl.h: Re-generate.
78 2019-11-14 Jan Beulich <jbeulich@suse.com>
80 * i386-gen.c (opcode_modifiers): Add AnySize entry.
81 (operand_types): Remove AnySize entry.
82 * i386-opc.h (AnySize): Move between enums.
83 (struct i386_opcode_modifier): Add anysize field.
84 (OTUnused): Un-comment.
85 (union i386_operand_type): Remove anysize field.
86 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
87 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
88 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
90 * i386-tbl.h: Re-generate.
92 2019-11-12 Nelson Chu <nelson.chu@sifive.com>
94 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
95 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
96 use the floating point register (FPR).
98 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
100 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
102 (is_mve_encoding_conflict): Update cmode conflict checks for
105 2019-11-12 Jan Beulich <jbeulich@suse.com>
107 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
109 (operand_types): Remove EsSeg entry.
110 (main): Replace stale use of OTMax.
111 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
112 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
114 (OTUnused): Comment out.
115 (union i386_operand_type): Remove esseg field.
116 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
117 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
118 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
119 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
120 * i386-init.h, i386-tbl.h: Re-generate.
122 2019-11-12 Jan Beulich <jbeulich@suse.com>
124 * i386-gen.c (operand_instances): Add RegB entry.
125 * i386-opc.h (enum operand_instance): Add RegB.
126 * i386-opc.tbl (RegC, RegD, RegB): Define.
127 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
128 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
129 monitorx, mwaitx): Drop ImmExt and convert encodings
131 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
132 (edx, rdx): Add Instance=RegD.
133 (ebx, rbx): Add Instance=RegB.
134 * i386-tbl.h: Re-generate.
136 2019-11-12 Jan Beulich <jbeulich@suse.com>
138 * i386-gen.c (operand_type_init): Adjust
139 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
140 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
141 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
142 (operand_instances): New.
143 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
144 (output_operand_type): New parameter "instance". Process it.
145 (process_i386_operand_type): New local variable "instance".
146 (main): Adjust static assertions.
147 * i386-opc.h (INSTANCE_WIDTH): Define.
148 (enum operand_instance): New.
149 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
150 (union i386_operand_type): Replace acc, inoutportreg, and
151 shiftcount by instance.
152 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
153 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
155 * i386-init.h, i386-tbl.h: Re-generate.
157 2019-11-11 Jan Beulich <jbeulich@suse.com>
159 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
160 smaxp/sminp entries' "tied_operand" field to 2.
162 2019-11-11 Jan Beulich <jbeulich@suse.com>
164 * aarch64-opc.c (operand_general_constraint_met_p): Replace
165 "index" local variable by that of the already existing "num".
167 2019-11-08 H.J. Lu <hongjiu.lu@intel.com>
170 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
171 * i386-tbl.h: Regenerated.
173 2019-11-08 Jan Beulich <jbeulich@suse.com>
175 * i386-gen.c (operand_type_init): Add Class= to
176 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
177 OPERAND_TYPE_REGBND entry.
178 (operand_classes): Add RegMask and RegBND entries.
179 (operand_types): Drop RegMask and RegBND entry.
180 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
181 (RegMask, RegBND): Delete.
182 (union i386_operand_type): Remove regmask and regbnd fields.
183 * i386-opc.tbl (RegMask, RegBND): Define.
184 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
186 * i386-init.h, i386-tbl.h: Re-generate.
188 2019-11-08 Jan Beulich <jbeulich@suse.com>
190 * i386-gen.c (operand_type_init): Add Class= to
191 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
192 OPERAND_TYPE_REGZMM entries.
193 (operand_classes): Add RegMMX and RegSIMD entries.
194 (operand_types): Drop RegMMX and RegSIMD entries.
195 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
196 (RegMMX, RegSIMD): Delete.
197 (union i386_operand_type): Remove regmmx and regsimd fields.
198 * i386-opc.tbl (RegMMX): Define.
199 (RegXMM, RegYMM, RegZMM): Add Class=.
200 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
202 * i386-init.h, i386-tbl.h: Re-generate.
204 2019-11-08 Jan Beulich <jbeulich@suse.com>
206 * i386-gen.c (operand_type_init): Add Class= to
207 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
209 (operand_classes): Add RegCR, RegDR, and RegTR entries.
210 (operand_types): Drop Control, Debug, and Test entries.
211 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
212 (Control, Debug, Test): Delete.
213 (union i386_operand_type): Remove control, debug, and test
215 * i386-opc.tbl (Control, Debug, Test): Define.
216 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
217 Class=RegDR, and Test by Class=RegTR.
218 * i386-init.h, i386-tbl.h: Re-generate.
220 2019-11-08 Jan Beulich <jbeulich@suse.com>
222 * i386-gen.c (operand_type_init): Add Class= to
223 OPERAND_TYPE_SREG entry.
224 (operand_classes): Add SReg entry.
225 (operand_types): Drop SReg entry.
226 * i386-opc.h (enum operand_class): Add SReg.
228 (union i386_operand_type): Remove sreg field.
229 * i386-opc.tbl (SReg): Define.
230 * i386-reg.tbl: Replace SReg by Class=SReg.
231 * i386-init.h, i386-tbl.h: Re-generate.
233 2019-11-08 Jan Beulich <jbeulich@suse.com>
235 * i386-gen.c (operand_type_init): Add Class=. New
236 OPERAND_TYPE_ANYIMM entry.
237 (operand_classes): New.
238 (operand_types): Drop Reg entry.
239 (output_operand_type): New parameter "class". Process it.
240 (process_i386_operand_type): New local variable "class".
241 (main): Adjust static assertions.
242 * i386-opc.h (CLASS_WIDTH): Define.
243 (enum operand_class): New.
244 (Reg): Replace by Class. Adjust comment.
245 (union i386_operand_type): Replace reg by class.
246 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
248 * i386-reg.tbl: Replace Reg by Class=Reg.
249 * i386-init.h: Re-generate.
251 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
253 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
254 (aarch64_opcode_table): Add data gathering hint mnemonic.
255 * opcodes/aarch64-dis-2.c: Account for new instruction.
257 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
259 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
262 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
264 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
265 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
266 aarch64_feature_f64mm): New feature sets.
267 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
268 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
270 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
272 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
273 (OP_SVE_QQQ): New qualifier.
274 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
275 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
276 the movprfx constraint.
277 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
278 (aarch64_opcode_table): Define new instructions smmla,
279 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
281 * aarch64-opc.c (operand_general_constraint_met_p): Handle
282 AARCH64_OPND_SVE_ADDR_RI_S4x32.
283 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
284 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
285 Account for new instructions.
286 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
288 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
290 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
291 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
293 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
295 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
296 (neon_opcodes): Add bfloat SIMD instructions.
297 (print_insn_coprocessor): Add new control character %b to print
298 condition code without checking cp_num.
299 (print_insn_neon): Account for BFloat16 instructions that have no
300 special top-byte handling.
302 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
303 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
305 * arm-dis.c (print_insn_coprocessor,
306 print_insn_generic_coprocessor): Create wrapper functions around
307 the implementation of the print_insn_coprocessor control codes.
308 (print_insn_coprocessor_1): Original print_insn_coprocessor
309 function that now takes which array to look at as an argument.
310 (print_insn_arm): Use both print_insn_coprocessor and
311 print_insn_generic_coprocessor.
312 (print_insn_thumb32): As above.
314 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
315 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
317 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
318 in reglane special case.
319 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
320 aarch64_find_next_opcode): Account for new instructions.
321 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
322 in reglane special case.
323 * aarch64-opc.c (struct operand_qualifier_data): Add data for
324 new AARCH64_OPND_QLF_S_2H qualifier.
325 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
326 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
327 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
329 (BFLOAT_SVE, BFLOAT): New feature set macros.
330 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
332 (aarch64_opcode_table): Define new instructions bfdot,
333 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
336 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
337 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
339 * aarch64-tbl.h (ARMV8_6): New macro.
341 2019-11-07 Jan Beulich <jbeulich@suse.com>
343 * i386-dis.c (prefix_table): Add mcommit.
344 (rm_table): Add rdpru.
345 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
346 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
347 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
348 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
349 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
350 * i386-opc.tbl (mcommit, rdpru): New.
351 * i386-init.h, i386-tbl.h: Re-generate.
353 2019-11-07 Jan Beulich <jbeulich@suse.com>
355 * i386-dis.c (OP_Mwait): Drop local variable "names", use
357 (OP_Monitor): Drop local variable "op1_names", re-purpose
358 "names" for it instead, and replace former "names" uses by
361 2019-11-07 Jan Beulich <jbeulich@suse.com>
364 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
366 * opcodes/i386-tbl.h: Re-generate.
368 2019-11-05 Jan Beulich <jbeulich@suse.com>
370 * i386-dis.c (OP_Mwaitx): Delete.
371 (prefix_table): Use OP_Mwait for mwaitx entry.
372 (OP_Mwait): Also handle mwaitx.
374 2019-11-05 Jan Beulich <jbeulich@suse.com>
376 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
377 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
378 (prefix_table): Add respective entries.
379 (rm_table): Link to those entries.
381 2019-11-05 Jan Beulich <jbeulich@suse.com>
383 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
384 (REG_0F1C_P_0_MOD_0): ... this.
385 (REG_0F1E_MOD_3): Rename to ...
386 (REG_0F1E_P_1_MOD_3): ... this.
387 (RM_0F01_REG_5): Rename to ...
388 (RM_0F01_REG_5_MOD_3): ... this.
389 (RM_0F01_REG_7): Rename to ...
390 (RM_0F01_REG_7_MOD_3): ... this.
391 (RM_0F1E_MOD_3_REG_7): Rename to ...
392 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
393 (RM_0FAE_REG_6): Rename to ...
394 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
395 (RM_0FAE_REG_7): Rename to ...
396 (RM_0FAE_REG_7_MOD_3): ... this.
397 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
398 (PREFIX_0F01_REG_5_MOD_0): ... this.
399 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
400 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
401 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
402 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
403 (PREFIX_0FAE_REG_0): Rename to ...
404 (PREFIX_0FAE_REG_0_MOD_3): ... this.
405 (PREFIX_0FAE_REG_1): Rename to ...
406 (PREFIX_0FAE_REG_1_MOD_3): ... this.
407 (PREFIX_0FAE_REG_2): Rename to ...
408 (PREFIX_0FAE_REG_2_MOD_3): ... this.
409 (PREFIX_0FAE_REG_3): Rename to ...
410 (PREFIX_0FAE_REG_3_MOD_3): ... this.
411 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
412 (PREFIX_0FAE_REG_4_MOD_0): ... this.
413 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
414 (PREFIX_0FAE_REG_4_MOD_3): ... this.
415 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
416 (PREFIX_0FAE_REG_5_MOD_0): ... this.
417 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
418 (PREFIX_0FAE_REG_5_MOD_3): ... this.
419 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
420 (PREFIX_0FAE_REG_6_MOD_0): ... this.
421 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
422 (PREFIX_0FAE_REG_6_MOD_3): ... this.
423 (PREFIX_0FAE_REG_7): Rename to ...
424 (PREFIX_0FAE_REG_7_MOD_0): ... this.
425 (PREFIX_MOD_0_0FC3): Rename to ...
426 (PREFIX_0FC3_MOD_0): ... this.
427 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
428 (PREFIX_0FC7_REG_6_MOD_0): ... this.
429 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
430 (PREFIX_0FC7_REG_6_MOD_3): ... this.
431 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
432 (PREFIX_0FC7_REG_7_MOD_3): ... this.
433 (reg_table, prefix_table, mod_table, rm_table): Adjust
436 2019-11-04 Nick Clifton <nickc@redhat.com>
438 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
439 of a v850 system register. Move the v850_sreg_names array into
441 (get_v850_reg_name): Likewise for ordinary register names.
442 (get_v850_vreg_name): Likewise for vector register names.
443 (get_v850_cc_name): Likewise for condition codes.
444 * get_v850_float_cc_name): Likewise for floating point condition
446 (get_v850_cacheop_name): Likewise for cache-ops.
447 (get_v850_prefop_name): Likewise for pref-ops.
448 (disassemble): Use the new accessor functions.
450 2019-10-30 Delia Burduv <delia.burduv@arm.com>
452 * aarch64-opc.c (print_immediate_offset_address): Don't print the
453 immediate for the writeback form of ldraa/ldrab if it is 0.
454 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
455 * aarch64-opc-2.c: Regenerated.
457 2019-10-30 Jan Beulich <jbeulich@suse.com>
459 * i386-gen.c (operand_type_shorthands): Delete.
460 (operand_type_init): Expand previous shorthands.
461 (set_bitfield_from_shorthand): Rename back to ...
462 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
463 of operand_type_init[].
464 (set_bitfield): Adjust call to the above function.
465 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
466 RegXMM, RegYMM, RegZMM): Define.
467 * i386-reg.tbl: Expand prior shorthands.
469 2019-10-30 Jan Beulich <jbeulich@suse.com>
471 * i386-gen.c (output_i386_opcode): Change order of fields
473 * i386-opc.h (struct insn_template): Move operands field.
474 Convert extension_opcode field to unsigned short.
475 * i386-tbl.h: Re-generate.
477 2019-10-30 Jan Beulich <jbeulich@suse.com>
479 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
481 * i386-opc.h (W): Extend comment.
482 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
483 general purpose variants not allowing for byte operands.
484 * i386-tbl.h: Re-generate.
486 2019-10-29 Nick Clifton <nickc@redhat.com>
488 * tic30-dis.c (print_branch): Correct size of operand array.
490 2019-10-29 Nick Clifton <nickc@redhat.com>
492 * d30v-dis.c (print_insn): Check that operand index is valid
493 before attempting to access the operands array.
495 2019-10-29 Nick Clifton <nickc@redhat.com>
497 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
498 locating the bit to be tested.
500 2019-10-29 Nick Clifton <nickc@redhat.com>
502 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
504 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
505 (print_insn_s12z): Check for illegal size values.
507 2019-10-28 Nick Clifton <nickc@redhat.com>
509 * csky-dis.c (csky_chars_to_number): Check for a negative
510 count. Use an unsigned integer to construct the return value.
512 2019-10-28 Nick Clifton <nickc@redhat.com>
514 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
515 operand buffer. Set value to 15 not 13.
516 (get_register_operand): Use OPERAND_BUFFER_LEN.
517 (get_indirect_operand): Likewise.
518 (print_two_operand): Likewise.
519 (print_three_operand): Likewise.
520 (print_oar_insn): Likewise.
522 2019-10-28 Nick Clifton <nickc@redhat.com>
524 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
525 (bit_extract_simple): Likewise.
526 (bit_copy): Likewise.
527 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
528 index_offset array are not accessed.
530 2019-10-28 Nick Clifton <nickc@redhat.com>
532 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
535 2019-10-25 Nick Clifton <nickc@redhat.com>
537 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
538 access to opcodes.op array element.
540 2019-10-23 Nick Clifton <nickc@redhat.com>
542 * rx-dis.c (get_register_name): Fix spelling typo in error
544 (get_condition_name, get_flag_name, get_double_register_name)
545 (get_double_register_high_name, get_double_register_low_name)
546 (get_double_control_register_name, get_double_condition_name)
547 (get_opsize_name, get_size_name): Likewise.
549 2019-10-22 Nick Clifton <nickc@redhat.com>
551 * rx-dis.c (get_size_name): New function. Provides safe
552 access to name array.
553 (get_opsize_name): Likewise.
554 (print_insn_rx): Use the accessor functions.
556 2019-10-16 Nick Clifton <nickc@redhat.com>
558 * rx-dis.c (get_register_name): New function. Provides safe
559 access to name array.
560 (get_condition_name, get_flag_name, get_double_register_name)
561 (get_double_register_high_name, get_double_register_low_name)
562 (get_double_control_register_name, get_double_condition_name):
564 (print_insn_rx): Use the accessor functions.
566 2019-10-09 Nick Clifton <nickc@redhat.com>
569 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
572 2019-10-07 Jan Beulich <jbeulich@suse.com>
574 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
575 (cmpsd): Likewise. Move EsSeg to other operand.
576 * opcodes/i386-tbl.h: Re-generate.
578 2019-09-23 Alan Modra <amodra@gmail.com>
580 * m68k-dis.c: Include cpu-m68k.h
582 2019-09-23 Alan Modra <amodra@gmail.com>
584 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
585 "elf/mips.h" earlier.
587 2018-09-20 Jan Beulich <jbeulich@suse.com>
590 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
592 * i386-tbl.h: Re-generate.
594 2019-09-18 Alan Modra <amodra@gmail.com>
596 * arc-ext.c: Update throughout for bfd section macro changes.
598 2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
600 * Makefile.in: Re-generate.
601 * configure: Re-generate.
603 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
605 * riscv-opc.c (riscv_opcodes): Change subset field
606 to insn_class field for all instructions.
607 (riscv_insn_types): Likewise.
609 2019-09-16 Phil Blundell <pb@pbcl.net>
611 * configure: Regenerated.
613 2019-09-10 Miod Vallat <miod@online.fr>
616 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
618 2019-09-09 Phil Blundell <pb@pbcl.net>
620 binutils 2.33 branch created.
622 2019-09-03 Nick Clifton <nickc@redhat.com>
625 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
626 greater than zero before indexing via (bufcnt -1).
628 2019-09-03 Nick Clifton <nickc@redhat.com>
631 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
632 (MAX_SPEC_REG_NAME_LEN): Define.
633 (struct mmix_dis_info): Use defined constants for array lengths.
634 (get_reg_name): New function.
635 (get_sprec_reg_name): New function.
636 (print_insn_mmix): Use new functions.
638 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
640 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
641 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
642 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
644 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
646 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
647 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
648 (aarch64_sys_reg_supported_p): Update checks for the above.
650 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
652 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
653 cases MVE_SQRSHRL and MVE_UQRSHLL.
654 (print_insn_mve): Add case for specifier 'k' to check
655 specific bit of the instruction.
657 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
660 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
661 encountering an unknown machine type.
662 (print_insn_arc): Handle arc_insn_length returning 0. In error
663 cases return -1 rather than calling abort.
665 2019-08-07 Jan Beulich <jbeulich@suse.com>
667 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
668 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
670 * i386-tbl.h: Re-generate.
672 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
674 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
677 2019-07-30 Mel Chen <mel.chen@sifive.com>
679 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
680 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
682 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
685 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
687 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
688 and MPY class instructions.
689 (parse_option): Add nps400 option.
690 (print_arc_disassembler_options): Add nps400 info.
692 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
694 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
697 * arc-opc.c (RAD_CHK): Add.
698 * arc-tbl.h: Regenerate.
700 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
702 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
703 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
705 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
707 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
708 instructions as UNPREDICTABLE.
710 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
712 * bpf-desc.c: Regenerated.
714 2019-07-17 Jan Beulich <jbeulich@suse.com>
716 * i386-gen.c (static_assert): Define.
718 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
719 (Opcode_Modifier_Num): ... this.
722 2019-07-16 Jan Beulich <jbeulich@suse.com>
724 * i386-gen.c (operand_types): Move RegMem ...
725 (opcode_modifiers): ... here.
726 * i386-opc.h (RegMem): Move to opcode modifer enum.
727 (union i386_operand_type): Move regmem field ...
728 (struct i386_opcode_modifier): ... here.
729 * i386-opc.tbl (RegMem): Define.
730 (mov, movq): Move RegMem on segment, control, debug, and test
732 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
733 to non-SSE2AVX flavor.
734 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
735 Move RegMem on register only flavors. Drop IgnoreSize from
736 legacy encoding flavors.
737 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
739 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
740 register only flavors.
741 (vmovd): Move RegMem and drop IgnoreSize on register only
742 flavor. Change opcode and operand order to store form.
743 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
745 2019-07-16 Jan Beulich <jbeulich@suse.com>
747 * i386-gen.c (operand_type_init, operand_types): Replace SReg
749 * i386-opc.h (SReg2, SReg3): Replace by ...
751 (union i386_operand_type): Replace sreg fields.
752 * i386-opc.tbl (mov, ): Use SReg.
753 (push, pop): Likewies. Drop i386 and x86-64 specific segment
755 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
756 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
758 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
760 * bpf-desc.c: Regenerate.
761 * bpf-opc.c: Likewise.
762 * bpf-opc.h: Likewise.
764 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
766 * bpf-desc.c: Regenerate.
767 * bpf-opc.c: Likewise.
769 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
771 * arm-dis.c (print_insn_coprocessor): Rename index to
774 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
776 * riscv-opc.c (riscv_insn_types): Add r4 type.
778 * riscv-opc.c (riscv_insn_types): Add b and j type.
780 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
781 format for sb type and correct s type.
783 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
785 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
786 SVE FMOV alias of FCPY.
788 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
790 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
791 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
793 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
795 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
796 registers in an instruction prefixed by MOVPRFX.
798 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
800 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
801 sve_size_13 icode to account for variant behaviour of
803 * aarch64-dis-2.c: Regenerate.
804 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
805 sve_size_13 icode to account for variant behaviour of
807 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
808 (OP_SVE_VVV_Q_D): Add new qualifier.
809 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
810 (struct aarch64_opcode): Split pmull{t,b} into those requiring
813 2019-07-01 Jan Beulich <jbeulich@suse.com>
815 * opcodes/i386-gen.c (operand_type_init): Remove
816 OPERAND_TYPE_VEC_IMM4 entry.
817 (operand_types): Remove Vec_Imm4.
818 * opcodes/i386-opc.h (Vec_Imm4): Delete.
819 (union i386_operand_type): Remove vec_imm4.
820 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
821 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
823 2019-07-01 Jan Beulich <jbeulich@suse.com>
825 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
826 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
827 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
828 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
829 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
830 monitorx, mwaitx): Drop ImmExt from operand-less forms.
831 * i386-tbl.h: Re-generate.
833 2019-07-01 Jan Beulich <jbeulich@suse.com>
835 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
837 * i386-tbl.h: Re-generate.
839 2019-07-01 Jan Beulich <jbeulich@suse.com>
841 * i386-opc.tbl (C): New.
842 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
843 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
844 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
845 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
846 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
847 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
848 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
849 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
850 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
851 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
852 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
853 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
854 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
855 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
856 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
857 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
858 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
859 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
860 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
861 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
862 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
863 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
864 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
865 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
866 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
867 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
869 * i386-tbl.h: Re-generate.
871 2019-07-01 Jan Beulich <jbeulich@suse.com>
873 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
875 * i386-tbl.h: Re-generate.
877 2019-07-01 Jan Beulich <jbeulich@suse.com>
879 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
880 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
881 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
882 * i386-tbl.h: Re-generate.
884 2019-07-01 Jan Beulich <jbeulich@suse.com>
886 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
887 Disp8MemShift from register only templates.
888 * i386-tbl.h: Re-generate.
890 2019-07-01 Jan Beulich <jbeulich@suse.com>
892 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
893 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
894 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
895 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
896 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
897 EVEX_W_0F11_P_3_M_1): Delete.
898 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
899 EVEX_W_0F11_P_3): New.
900 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
901 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
902 MOD_EVEX_0F11_PREFIX_3 table entries.
903 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
904 PREFIX_EVEX_0F11 table entries.
905 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
906 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
907 EVEX_W_0F11_P_3_M_{0,1} table entries.
909 2019-07-01 Jan Beulich <jbeulich@suse.com>
911 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
914 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
917 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
918 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
919 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
920 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
921 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
922 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
923 EVEX_LEN_0F38C7_R_6_P_2_W_1.
924 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
925 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
926 PREFIX_EVEX_0F38C6_REG_6 entries.
927 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
928 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
929 EVEX_W_0F38C7_R_6_P_2 entries.
930 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
931 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
932 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
933 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
934 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
935 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
936 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
938 2019-06-27 Jan Beulich <jbeulich@suse.com>
940 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
941 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
942 VEX_LEN_0F2D_P_3): Delete.
943 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
944 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
945 (prefix_table): ... here.
947 2019-06-27 Jan Beulich <jbeulich@suse.com>
949 * i386-dis.c (Iq): Delete.
951 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
953 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
954 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
955 (OP_E_memory): Also honor needindex when deciding whether an
956 address size prefix needs printing.
957 (OP_I): Remove handling of q_mode. Add handling of d_mode.
959 2019-06-26 Jim Wilson <jimw@sifive.com>
962 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
963 Set info->display_endian to info->endian_code.
965 2019-06-25 Jan Beulich <jbeulich@suse.com>
967 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
968 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
969 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
970 OPERAND_TYPE_ACC64 entries.
971 * i386-init.h: Re-generate.
973 2019-06-25 Jan Beulich <jbeulich@suse.com>
975 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
977 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
979 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
981 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
982 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
984 2019-06-25 Jan Beulich <jbeulich@suse.com>
986 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
989 2019-06-25 Jan Beulich <jbeulich@suse.com>
991 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
992 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
994 * i386-opc.tbl (movnti): Add IgnoreSize.
995 * i386-tbl.h: Re-generate.
997 2019-06-25 Jan Beulich <jbeulich@suse.com>
999 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1000 * i386-tbl.h: Re-generate.
1002 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1004 * i386-dis-evex.h: Break into ...
1005 * i386-dis-evex-len.h: New file.
1006 * i386-dis-evex-mod.h: Likewise.
1007 * i386-dis-evex-prefix.h: Likewise.
1008 * i386-dis-evex-reg.h: Likewise.
1009 * i386-dis-evex-w.h: Likewise.
1010 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1011 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1012 i386-dis-evex-mod.h.
1014 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1017 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1018 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1020 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1021 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1022 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1023 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1024 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1025 EVEX_LEN_0F385B_P_2_W_1.
1026 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1027 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1028 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1029 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1030 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1031 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1032 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1033 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1034 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1035 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1037 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1040 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1041 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1042 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1043 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1044 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1045 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1046 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1047 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1048 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1049 EVEX_LEN_0F3A43_P_2_W_1.
1050 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1051 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1052 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1053 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1054 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1055 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1056 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1057 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1058 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1059 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1060 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1061 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1063 2019-06-14 Nick Clifton <nickc@redhat.com>
1065 * po/fr.po; Updated French translation.
1067 2019-06-13 Stafford Horne <shorne@gmail.com>
1069 * or1k-asm.c: Regenerated.
1070 * or1k-desc.c: Regenerated.
1071 * or1k-desc.h: Regenerated.
1072 * or1k-dis.c: Regenerated.
1073 * or1k-ibld.c: Regenerated.
1074 * or1k-opc.c: Regenerated.
1075 * or1k-opc.h: Regenerated.
1076 * or1k-opinst.c: Regenerated.
1078 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
1080 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1082 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1085 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1086 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1087 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1088 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1089 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1090 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1091 EVEX_LEN_0F3A1B_P_2_W_1.
1092 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1093 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1094 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1095 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1096 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1097 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1098 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1099 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1101 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1104 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1105 EVEX.vvvv when disassembling VEX and EVEX instructions.
1106 (OP_VEX): Set vex.register_specifier to 0 after readding
1107 vex.register_specifier.
1108 (OP_Vex_2src_1): Likewise.
1109 (OP_Vex_2src_2): Likewise.
1110 (OP_LWP_E): Likewise.
1111 (OP_EX_Vex): Don't check vex.register_specifier.
1112 (OP_XMM_Vex): Likewise.
1114 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1115 Lili Cui <lili.cui@intel.com>
1117 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1118 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1120 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1121 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1122 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1123 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1124 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1125 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1126 * i386-init.h: Regenerated.
1127 * i386-tbl.h: Likewise.
1129 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1130 Lili Cui <lili.cui@intel.com>
1132 * doc/c-i386.texi: Document enqcmd.
1133 * testsuite/gas/i386/enqcmd-intel.d: New file.
1134 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1135 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1136 * testsuite/gas/i386/enqcmd.d: Likewise.
1137 * testsuite/gas/i386/enqcmd.s: Likewise.
1138 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1139 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1140 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1141 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1142 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1143 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1144 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1147 2019-06-04 Alan Hayward <alan.hayward@arm.com>
1149 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1151 2019-06-03 Alan Modra <amodra@gmail.com>
1153 * ppc-dis.c (prefix_opcd_indices): Correct size.
1155 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1158 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1160 * i386-tbl.h: Regenerated.
1162 2019-05-24 Alan Modra <amodra@gmail.com>
1164 * po/POTFILES.in: Regenerate.
1166 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1167 Alan Modra <amodra@gmail.com>
1169 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1170 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1171 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1172 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1173 XTOP>): Define and add entries.
1174 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1175 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1176 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1177 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1179 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1180 Alan Modra <amodra@gmail.com>
1182 * ppc-dis.c (ppc_opts): Add "future" entry.
1183 (PREFIX_OPCD_SEGS): Define.
1184 (prefix_opcd_indices): New array.
1185 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1186 (lookup_prefix): New function.
1187 (print_insn_powerpc): Handle 64-bit prefix instructions.
1188 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1189 (PMRR, POWERXX): Define.
1190 (prefix_opcodes): New instruction table.
1191 (prefix_num_opcodes): New constant.
1193 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1195 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1196 * configure: Regenerated.
1197 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1199 (HFILES): Add bpf-desc.h and bpf-opc.h.
1200 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1201 bpf-ibld.c and bpf-opc.c.
1203 * Makefile.in: Regenerated.
1204 * disassemble.c (ARCH_bpf): Define.
1205 (disassembler): Add case for bfd_arch_bpf.
1206 (disassemble_init_for_target): Likewise.
1207 (enum epbf_isa_attr): Define.
1208 * disassemble.h: extern print_insn_bpf.
1209 * bpf-asm.c: Generated.
1210 * bpf-opc.h: Likewise.
1211 * bpf-opc.c: Likewise.
1212 * bpf-ibld.c: Likewise.
1213 * bpf-dis.c: Likewise.
1214 * bpf-desc.h: Likewise.
1215 * bpf-desc.c: Likewise.
1217 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1219 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1220 and VMSR with the new operands.
1222 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1224 * arm-dis.c (enum mve_instructions): New enum
1225 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1227 (mve_opcodes): New instructions as above.
1228 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1230 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1232 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1234 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1235 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1236 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1237 uqshl, urshrl and urshr.
1238 (is_mve_okay_in_it): Add new instructions to TRUE list.
1239 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1240 (print_insn_mve): Updated to accept new %j,
1241 %<bitfield>m and %<bitfield>n patterns.
1243 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1245 * mips-opc.c (mips_builtin_opcodes): Change source register
1246 constraint for DAUI.
1248 2019-05-20 Nick Clifton <nickc@redhat.com>
1250 * po/fr.po: Updated French translation.
1252 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1253 Michael Collison <michael.collison@arm.com>
1255 * arm-dis.c (thumb32_opcodes): Add new instructions.
1256 (enum mve_instructions): Likewise.
1257 (enum mve_undefined): Add new reasons.
1258 (is_mve_encoding_conflict): Handle new instructions.
1259 (is_mve_undefined): Likewise.
1260 (is_mve_unpredictable): Likewise.
1261 (print_mve_undefined): Likewise.
1262 (print_mve_size): Likewise.
1264 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1265 Michael Collison <michael.collison@arm.com>
1267 * arm-dis.c (thumb32_opcodes): Add new instructions.
1268 (enum mve_instructions): Likewise.
1269 (is_mve_encoding_conflict): Handle new instructions.
1270 (is_mve_undefined): Likewise.
1271 (is_mve_unpredictable): Likewise.
1272 (print_mve_size): Likewise.
1274 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1275 Michael Collison <michael.collison@arm.com>
1277 * arm-dis.c (thumb32_opcodes): Add new instructions.
1278 (enum mve_instructions): Likewise.
1279 (is_mve_encoding_conflict): Likewise.
1280 (is_mve_unpredictable): Likewise.
1281 (print_mve_size): Likewise.
1283 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1284 Michael Collison <michael.collison@arm.com>
1286 * arm-dis.c (thumb32_opcodes): Add new instructions.
1287 (enum mve_instructions): Likewise.
1288 (is_mve_encoding_conflict): Handle new instructions.
1289 (is_mve_undefined): Likewise.
1290 (is_mve_unpredictable): Likewise.
1291 (print_mve_size): Likewise.
1293 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1294 Michael Collison <michael.collison@arm.com>
1296 * arm-dis.c (thumb32_opcodes): Add new instructions.
1297 (enum mve_instructions): Likewise.
1298 (is_mve_encoding_conflict): Handle new instructions.
1299 (is_mve_undefined): Likewise.
1300 (is_mve_unpredictable): Likewise.
1301 (print_mve_size): Likewise.
1302 (print_insn_mve): Likewise.
1304 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1305 Michael Collison <michael.collison@arm.com>
1307 * arm-dis.c (thumb32_opcodes): Add new instructions.
1308 (print_insn_thumb32): Handle new instructions.
1310 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1311 Michael Collison <michael.collison@arm.com>
1313 * arm-dis.c (enum mve_instructions): Add new instructions.
1314 (enum mve_undefined): Add new reasons.
1315 (is_mve_encoding_conflict): Handle new instructions.
1316 (is_mve_undefined): Likewise.
1317 (is_mve_unpredictable): Likewise.
1318 (print_mve_undefined): Likewise.
1319 (print_mve_size): Likewise.
1320 (print_mve_shift_n): Likewise.
1321 (print_insn_mve): Likewise.
1323 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1324 Michael Collison <michael.collison@arm.com>
1326 * arm-dis.c (enum mve_instructions): Add new instructions.
1327 (is_mve_encoding_conflict): Handle new instructions.
1328 (is_mve_unpredictable): Likewise.
1329 (print_mve_rotate): Likewise.
1330 (print_mve_size): Likewise.
1331 (print_insn_mve): Likewise.
1333 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1334 Michael Collison <michael.collison@arm.com>
1336 * arm-dis.c (enum mve_instructions): Add new instructions.
1337 (is_mve_encoding_conflict): Handle new instructions.
1338 (is_mve_unpredictable): Likewise.
1339 (print_mve_size): Likewise.
1340 (print_insn_mve): Likewise.
1342 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1343 Michael Collison <michael.collison@arm.com>
1345 * arm-dis.c (enum mve_instructions): Add new instructions.
1346 (enum mve_undefined): Add new reasons.
1347 (is_mve_encoding_conflict): Handle new instructions.
1348 (is_mve_undefined): Likewise.
1349 (is_mve_unpredictable): Likewise.
1350 (print_mve_undefined): Likewise.
1351 (print_mve_size): Likewise.
1352 (print_insn_mve): Likewise.
1354 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1355 Michael Collison <michael.collison@arm.com>
1357 * arm-dis.c (enum mve_instructions): Add new instructions.
1358 (is_mve_encoding_conflict): Handle new instructions.
1359 (is_mve_undefined): Likewise.
1360 (is_mve_unpredictable): Likewise.
1361 (print_mve_size): Likewise.
1362 (print_insn_mve): Likewise.
1364 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1365 Michael Collison <michael.collison@arm.com>
1367 * arm-dis.c (enum mve_instructions): Add new instructions.
1368 (enum mve_unpredictable): Add new reasons.
1369 (enum mve_undefined): Likewise.
1370 (is_mve_okay_in_it): Handle new isntructions.
1371 (is_mve_encoding_conflict): Likewise.
1372 (is_mve_undefined): Likewise.
1373 (is_mve_unpredictable): Likewise.
1374 (print_mve_vmov_index): Likewise.
1375 (print_simd_imm8): Likewise.
1376 (print_mve_undefined): Likewise.
1377 (print_mve_unpredictable): Likewise.
1378 (print_mve_size): Likewise.
1379 (print_insn_mve): Likewise.
1381 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1382 Michael Collison <michael.collison@arm.com>
1384 * arm-dis.c (enum mve_instructions): Add new instructions.
1385 (enum mve_unpredictable): Add new reasons.
1386 (enum mve_undefined): Likewise.
1387 (is_mve_encoding_conflict): Handle new instructions.
1388 (is_mve_undefined): Likewise.
1389 (is_mve_unpredictable): Likewise.
1390 (print_mve_undefined): Likewise.
1391 (print_mve_unpredictable): Likewise.
1392 (print_mve_rounding_mode): Likewise.
1393 (print_mve_vcvt_size): Likewise.
1394 (print_mve_size): Likewise.
1395 (print_insn_mve): Likewise.
1397 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1398 Michael Collison <michael.collison@arm.com>
1400 * arm-dis.c (enum mve_instructions): Add new instructions.
1401 (enum mve_unpredictable): Add new reasons.
1402 (enum mve_undefined): Likewise.
1403 (is_mve_undefined): Handle new instructions.
1404 (is_mve_unpredictable): Likewise.
1405 (print_mve_undefined): Likewise.
1406 (print_mve_unpredictable): Likewise.
1407 (print_mve_size): Likewise.
1408 (print_insn_mve): Likewise.
1410 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1411 Michael Collison <michael.collison@arm.com>
1413 * arm-dis.c (enum mve_instructions): Add new instructions.
1414 (enum mve_undefined): Add new reasons.
1415 (insns): Add new instructions.
1416 (is_mve_encoding_conflict):
1417 (print_mve_vld_str_addr): New print function.
1418 (is_mve_undefined): Handle new instructions.
1419 (is_mve_unpredictable): Likewise.
1420 (print_mve_undefined): Likewise.
1421 (print_mve_size): Likewise.
1422 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1423 (print_insn_mve): Handle new operands.
1425 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1426 Michael Collison <michael.collison@arm.com>
1428 * arm-dis.c (enum mve_instructions): Add new instructions.
1429 (enum mve_unpredictable): Add new reasons.
1430 (is_mve_encoding_conflict): Handle new instructions.
1431 (is_mve_unpredictable): Likewise.
1432 (mve_opcodes): Add new instructions.
1433 (print_mve_unpredictable): Handle new reasons.
1434 (print_mve_register_blocks): New print function.
1435 (print_mve_size): Handle new instructions.
1436 (print_insn_mve): Likewise.
1438 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1439 Michael Collison <michael.collison@arm.com>
1441 * arm-dis.c (enum mve_instructions): Add new instructions.
1442 (enum mve_unpredictable): Add new reasons.
1443 (enum mve_undefined): Likewise.
1444 (is_mve_encoding_conflict): Handle new instructions.
1445 (is_mve_undefined): Likewise.
1446 (is_mve_unpredictable): Likewise.
1447 (coprocessor_opcodes): Move NEON VDUP from here...
1448 (neon_opcodes): ... to here.
1449 (mve_opcodes): Add new instructions.
1450 (print_mve_undefined): Handle new reasons.
1451 (print_mve_unpredictable): Likewise.
1452 (print_mve_size): Handle new instructions.
1453 (print_insn_neon): Handle vdup.
1454 (print_insn_mve): Handle new operands.
1456 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1457 Michael Collison <michael.collison@arm.com>
1459 * arm-dis.c (enum mve_instructions): Add new instructions.
1460 (enum mve_unpredictable): Add new values.
1461 (mve_opcodes): Add new instructions.
1462 (vec_condnames): New array with vector conditions.
1463 (mve_predicatenames): New array with predicate suffixes.
1464 (mve_vec_sizename): New array with vector sizes.
1465 (enum vpt_pred_state): New enum with vector predication states.
1466 (struct vpt_block): New struct type for vpt blocks.
1467 (vpt_block_state): Global struct to keep track of state.
1468 (mve_extract_pred_mask): New helper function.
1469 (num_instructions_vpt_block): Likewise.
1470 (mark_outside_vpt_block): Likewise.
1471 (mark_inside_vpt_block): Likewise.
1472 (invert_next_predicate_state): Likewise.
1473 (update_next_predicate_state): Likewise.
1474 (update_vpt_block_state): Likewise.
1475 (is_vpt_instruction): Likewise.
1476 (is_mve_encoding_conflict): Add entries for new instructions.
1477 (is_mve_unpredictable): Likewise.
1478 (print_mve_unpredictable): Handle new cases.
1479 (print_instruction_predicate): Likewise.
1480 (print_mve_size): New function.
1481 (print_vec_condition): New function.
1482 (print_insn_mve): Handle vpt blocks and new print operands.
1484 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1486 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1487 8, 14 and 15 for Armv8.1-M Mainline.
1489 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1490 Michael Collison <michael.collison@arm.com>
1492 * arm-dis.c (enum mve_instructions): New enum.
1493 (enum mve_unpredictable): Likewise.
1494 (enum mve_undefined): Likewise.
1495 (struct mopcode32): New struct.
1496 (is_mve_okay_in_it): New function.
1497 (is_mve_architecture): Likewise.
1498 (arm_decode_field): Likewise.
1499 (arm_decode_field_multiple): Likewise.
1500 (is_mve_encoding_conflict): Likewise.
1501 (is_mve_undefined): Likewise.
1502 (is_mve_unpredictable): Likewise.
1503 (print_mve_undefined): Likewise.
1504 (print_mve_unpredictable): Likewise.
1505 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1506 (print_insn_mve): New function.
1507 (print_insn_thumb32): Handle MVE architecture.
1508 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1510 2019-05-10 Nick Clifton <nickc@redhat.com>
1513 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1514 end of the table prematurely.
1516 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1518 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1521 2019-05-11 Alan Modra <amodra@gmail.com>
1523 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1524 when -Mraw is in effect.
1526 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1528 * aarch64-dis-2.c: Regenerate.
1529 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1530 (OP_SVE_BBB): New variant set.
1531 (OP_SVE_DDDD): New variant set.
1532 (OP_SVE_HHH): New variant set.
1533 (OP_SVE_HHHU): New variant set.
1534 (OP_SVE_SSS): New variant set.
1535 (OP_SVE_SSSU): New variant set.
1536 (OP_SVE_SHH): New variant set.
1537 (OP_SVE_SBBU): New variant set.
1538 (OP_SVE_DSS): New variant set.
1539 (OP_SVE_DHHU): New variant set.
1540 (OP_SVE_VMV_HSD_BHS): New variant set.
1541 (OP_SVE_VVU_HSD_BHS): New variant set.
1542 (OP_SVE_VVVU_SD_BH): New variant set.
1543 (OP_SVE_VVVU_BHSD): New variant set.
1544 (OP_SVE_VVV_QHD_DBS): New variant set.
1545 (OP_SVE_VVV_HSD_BHS): New variant set.
1546 (OP_SVE_VVV_HSD_BHS2): New variant set.
1547 (OP_SVE_VVV_BHS_HSD): New variant set.
1548 (OP_SVE_VV_BHS_HSD): New variant set.
1549 (OP_SVE_VVV_SD): New variant set.
1550 (OP_SVE_VVU_BHS_HSD): New variant set.
1551 (OP_SVE_VZVV_SD): New variant set.
1552 (OP_SVE_VZVV_BH): New variant set.
1553 (OP_SVE_VZV_SD): New variant set.
1554 (aarch64_opcode_table): Add sve2 instructions.
1556 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1558 * aarch64-asm-2.c: Regenerated.
1559 * aarch64-dis-2.c: Regenerated.
1560 * aarch64-opc-2.c: Regenerated.
1561 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1562 for SVE_SHLIMM_UNPRED_22.
1563 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1564 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1567 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1569 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1570 sve_size_tsz_bhs iclass encode.
1571 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1572 sve_size_tsz_bhs iclass decode.
1574 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1576 * aarch64-asm-2.c: Regenerated.
1577 * aarch64-dis-2.c: Regenerated.
1578 * aarch64-opc-2.c: Regenerated.
1579 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1580 for SVE_Zm4_11_INDEX.
1581 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1582 (fields): Handle SVE_i2h field.
1583 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1584 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1586 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1588 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1589 sve_shift_tsz_bhsd iclass encode.
1590 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1591 sve_shift_tsz_bhsd iclass decode.
1593 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1595 * aarch64-asm-2.c: Regenerated.
1596 * aarch64-dis-2.c: Regenerated.
1597 * aarch64-opc-2.c: Regenerated.
1598 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1599 (aarch64_encode_variant_using_iclass): Handle
1600 sve_shift_tsz_hsd iclass encode.
1601 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1602 sve_shift_tsz_hsd iclass decode.
1603 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1604 for SVE_SHRIMM_UNPRED_22.
1605 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1606 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1609 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1611 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1612 sve_size_013 iclass encode.
1613 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1614 sve_size_013 iclass decode.
1616 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1618 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1619 sve_size_bh iclass encode.
1620 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1621 sve_size_bh iclass decode.
1623 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1625 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1626 sve_size_sd2 iclass encode.
1627 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1628 sve_size_sd2 iclass decode.
1629 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1630 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1632 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1634 * aarch64-asm-2.c: Regenerated.
1635 * aarch64-dis-2.c: Regenerated.
1636 * aarch64-opc-2.c: Regenerated.
1637 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1639 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1640 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1642 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1644 * aarch64-asm-2.c: Regenerated.
1645 * aarch64-dis-2.c: Regenerated.
1646 * aarch64-opc-2.c: Regenerated.
1647 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1648 for SVE_Zm3_11_INDEX.
1649 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1650 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1651 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1653 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1655 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1657 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1658 sve_size_hsd2 iclass encode.
1659 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1660 sve_size_hsd2 iclass decode.
1661 * aarch64-opc.c (fields): Handle SVE_size field.
1662 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1664 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1666 * aarch64-asm-2.c: Regenerated.
1667 * aarch64-dis-2.c: Regenerated.
1668 * aarch64-opc-2.c: Regenerated.
1669 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1671 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1672 (fields): Handle SVE_rot3 field.
1673 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1674 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1676 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1678 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1681 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1684 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1685 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1686 aarch64_feature_sve2bitperm): New feature sets.
1687 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1688 for feature set addresses.
1689 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1690 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1692 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1693 Faraz Shahbazker <fshahbazker@wavecomp.com>
1695 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1696 argument and set ASE_EVA_R6 appropriately.
1697 (set_default_mips_dis_options): Pass ISA to above.
1698 (parse_mips_dis_option): Likewise.
1699 * mips-opc.c (EVAR6): New macro.
1700 (mips_builtin_opcodes): Add llwpe, scwpe.
1702 2019-05-01 Sudakshina Das <sudi.das@arm.com>
1704 * aarch64-asm-2.c: Regenerated.
1705 * aarch64-dis-2.c: Regenerated.
1706 * aarch64-opc-2.c: Regenerated.
1707 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1708 AARCH64_OPND_TME_UIMM16.
1709 (aarch64_print_operand): Likewise.
1710 * aarch64-tbl.h (QL_IMM_NIL): New.
1713 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1715 2019-04-29 John Darrington <john@darrington.wattle.id.au>
1717 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1719 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1720 Faraz Shahbazker <fshahbazker@wavecomp.com>
1722 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1724 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1726 * s12z-opc.h: Add extern "C" bracketing to help
1727 users who wish to use this interface in c++ code.
1729 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1731 * s12z-opc.c (bm_decode): Handle bit map operations with the
1734 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1736 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1737 specifier. Add entries for VLDR and VSTR of system registers.
1738 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1739 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1740 of %J and %K format specifier.
1742 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1744 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1745 Add new entries for VSCCLRM instruction.
1746 (print_insn_coprocessor): Handle new %C format control code.
1748 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1750 * arm-dis.c (enum isa): New enum.
1751 (struct sopcode32): New structure.
1752 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1753 set isa field of all current entries to ANY.
1754 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1755 Only match an entry if its isa field allows the current mode.
1757 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1759 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1761 (print_insn_thumb32): Add logic to print %n CLRM register list.
1763 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1765 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1768 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1770 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1771 (print_insn_thumb32): Edit the switch case for %Z.
1773 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1775 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1777 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1779 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1781 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1783 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1785 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1787 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1788 Arm register with r13 and r15 unpredictable.
1789 (thumb32_opcodes): New instructions for bfx and bflx.
1791 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1793 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1795 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1797 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1799 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1801 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1803 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1805 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1807 2019-04-12 John Darrington <john@darrington.wattle.id.au>
1809 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1810 "optr". ("operator" is a reserved word in c++).
1812 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1814 * aarch64-opc.c (aarch64_print_operand): Add case for
1816 (verify_constraints): Likewise.
1817 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1818 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1819 to accept Rt|SP as first operand.
1820 (AARCH64_OPERANDS): Add new Rt_SP.
1821 * aarch64-asm-2.c: Regenerated.
1822 * aarch64-dis-2.c: Regenerated.
1823 * aarch64-opc-2.c: Regenerated.
1825 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1827 * aarch64-asm-2.c: Regenerated.
1828 * aarch64-dis-2.c: Likewise.
1829 * aarch64-opc-2.c: Likewise.
1830 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1832 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1834 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1836 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1838 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1839 * i386-init.h: Regenerated.
1841 2019-04-07 Alan Modra <amodra@gmail.com>
1843 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1844 op_separator to control printing of spaces, comma and parens
1845 rather than need_comma, need_paren and spaces vars.
1847 2019-04-07 Alan Modra <amodra@gmail.com>
1850 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1851 (print_insn_neon, print_insn_arm): Likewise.
1853 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1855 * i386-dis-evex.h (evex_table): Updated to support BF16
1857 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1858 and EVEX_W_0F3872_P_3.
1859 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1860 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1861 * i386-opc.h (enum): Add CpuAVX512_BF16.
1862 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1863 * i386-opc.tbl: Add AVX512 BF16 instructions.
1864 * i386-init.h: Regenerated.
1865 * i386-tbl.h: Likewise.
1867 2019-04-05 Alan Modra <amodra@gmail.com>
1869 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1870 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1871 to favour printing of "-" branch hint when using the "y" bit.
1872 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1874 2019-04-05 Alan Modra <amodra@gmail.com>
1876 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1877 opcode until first operand is output.
1879 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1882 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1883 (valid_bo_post_v2): Add support for 'at' branch hints.
1884 (insert_bo): Only error on branch on ctr.
1885 (get_bo_hint_mask): New function.
1886 (insert_boe): Add new 'branch_taken' formal argument. Add support
1887 for inserting 'at' branch hints.
1888 (extract_boe): Add new 'branch_taken' formal argument. Add support
1889 for extracting 'at' branch hints.
1890 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1891 (BOE): Delete operand.
1892 (BOM, BOP): New operands.
1894 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1895 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1896 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1897 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1898 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1899 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1900 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1901 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1902 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1903 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1904 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1905 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1906 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1907 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1908 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1909 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1910 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1911 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1912 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1913 bttarl+>: New extended mnemonics.
1915 2019-03-28 Alan Modra <amodra@gmail.com>
1918 * ppc-opc.c (BTF): Define.
1919 (powerpc_opcodes): Use for mtfsb*.
1920 * ppc-dis.c (print_insn_powerpc): Print fields with both
1921 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1923 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1925 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1926 (mapping_symbol_for_insn): Implement new algorithm.
1927 (print_insn): Remove duplicate code.
1929 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1931 * aarch64-dis.c (print_insn_aarch64):
1934 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1936 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1939 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1941 * aarch64-dis.c (last_stop_offset): New.
1942 (print_insn_aarch64): Use stop_offset.
1944 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1947 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1949 * i386-init.h: Regenerated.
1951 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1954 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1955 vmovdqu16, vmovdqu32 and vmovdqu64.
1956 * i386-tbl.h: Regenerated.
1958 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1960 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1961 from vstrszb, vstrszh, and vstrszf.
1963 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1965 * s390-opc.txt: Add instruction descriptions.
1967 2019-02-08 Jim Wilson <jimw@sifive.com>
1969 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1972 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1974 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1976 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1979 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1980 * aarch64-opc.c (verify_elem_sd): New.
1981 (fields): Add FLD_sz entr.
1982 * aarch64-tbl.h (_SIMD_INSN): New.
1983 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1984 fmulx scalar and vector by element isns.
1986 2019-02-07 Nick Clifton <nickc@redhat.com>
1988 * po/sv.po: Updated Swedish translation.
1990 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1992 * s390-mkopc.c (main): Accept arch13 as cpu string.
1993 * s390-opc.c: Add new instruction formats and instruction opcode
1995 * s390-opc.txt: Add new arch13 instructions.
1997 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1999 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2000 (aarch64_opcode): Change encoding for stg, stzg
2002 * aarch64-asm-2.c: Regenerated.
2003 * aarch64-dis-2.c: Regenerated.
2004 * aarch64-opc-2.c: Regenerated.
2006 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2008 * aarch64-asm-2.c: Regenerated.
2009 * aarch64-dis-2.c: Likewise.
2010 * aarch64-opc-2.c: Likewise.
2011 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2013 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2014 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2016 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2017 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2018 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2019 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2020 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2021 case for ldstgv_indexed.
2022 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2023 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2024 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2025 * aarch64-asm-2.c: Regenerated.
2026 * aarch64-dis-2.c: Regenerated.
2027 * aarch64-opc-2.c: Regenerated.
2029 2019-01-23 Nick Clifton <nickc@redhat.com>
2031 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2033 2019-01-21 Nick Clifton <nickc@redhat.com>
2035 * po/de.po: Updated German translation.
2036 * po/uk.po: Updated Ukranian translation.
2038 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2039 * mips-dis.c (mips_arch_choices): Fix typo in
2040 gs464, gs464e and gs264e descriptors.
2042 2019-01-19 Nick Clifton <nickc@redhat.com>
2044 * configure: Regenerate.
2045 * po/opcodes.pot: Regenerate.
2047 2018-06-24 Nick Clifton <nickc@redhat.com>
2049 2.32 branch created.
2051 2019-01-09 John Darrington <john@darrington.wattle.id.au>
2053 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2055 -dis.c (opr_emit_disassembly): Do not omit an index if it is
2058 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2060 * configure: Regenerate.
2062 2019-01-07 Alan Modra <amodra@gmail.com>
2064 * configure: Regenerate.
2065 * po/POTFILES.in: Regenerate.
2067 2019-01-03 John Darrington <john@darrington.wattle.id.au>
2069 * s12z-opc.c: New file.
2070 * s12z-opc.h: New file.
2071 * s12z-dis.c: Removed all code not directly related to display
2072 of instructions. Used the interface provided by the new files
2074 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2075 * Makefile.in: Regenerate.
2076 * configure.ac (bfd_s12z_arch): Correct the dependencies.
2077 * configure: Regenerate.
2079 2019-01-01 Alan Modra <amodra@gmail.com>
2081 Update year range in copyright notice of all files.
2083 For older changes see ChangeLog-2018
2085 Copyright (C) 2019 Free Software Foundation, Inc.
2087 Copying and distribution of this file, with or without modification,
2088 are permitted in any medium without royalty provided the copyright
2089 notice and this notice are preserved.
2095 version-control: never