opcodes/ChangeLog

   1 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
   2             Michael Collison <michael.collison@arm.com>
   3
   4         * arm-dis.c (enum mve_instructions): Add new instructions.
   5         (is_mve_encoding_conflict): Handle new instructions.
   6         (is_mve_unpredictable): Likewise.
   7         (print_mve_size): Likewise.
   8         (print_insn_mve): Likewise.
   9
  10 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  11             Michael Collison <michael.collison@arm.com>
  12
  13         * arm-dis.c (enum mve_instructions): Add new instructions.
  14         (enum mve_undefined): Add new reasons.
  15         (is_mve_encoding_conflict): Handle new instructions.
  16         (is_mve_undefined): Likewise.
  17         (is_mve_unpredictable): Likewise.
  18         (print_mve_undefined): Likewise.
  19         (print_mve_size): Likewise.
  20         (print_insn_mve): Likewise.
  21
  22 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  23             Michael Collison <michael.collison@arm.com>
  24
  25         * arm-dis.c (enum mve_instructions): Add new instructions.
  26         (is_mve_encoding_conflict): Handle new instructions.
  27         (is_mve_undefined): Likewise.
  28         (is_mve_unpredictable): Likewise.
  29         (print_mve_size): Likewise.
  30         (print_insn_mve): Likewise.
  31
  32 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  33             Michael Collison <michael.collison@arm.com>
  34
  35         * arm-dis.c (enum mve_instructions): Add new instructions.
  36         (enum mve_unpredictable): Add new reasons.
  37         (enum mve_undefined): Likewise.
  38         (is_mve_okay_in_it): Handle new isntructions.
  39         (is_mve_encoding_conflict): Likewise.
  40         (is_mve_undefined): Likewise.
  41         (is_mve_unpredictable): Likewise.
  42         (print_mve_vmov_index): Likewise.
  43         (print_simd_imm8): Likewise.
  44         (print_mve_undefined): Likewise.
  45         (print_mve_unpredictable): Likewise.
  46         (print_mve_size): Likewise.
  47         (print_insn_mve): Likewise.
  48
  49 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  50             Michael Collison <michael.collison@arm.com>
  51
  52         * arm-dis.c (enum mve_instructions): Add new instructions.
  53         (enum mve_unpredictable): Add new reasons.
  54         (enum mve_undefined): Likewise.
  55         (is_mve_encoding_conflict): Handle new instructions.
  56         (is_mve_undefined): Likewise.
  57         (is_mve_unpredictable): Likewise.
  58         (print_mve_undefined): Likewise.
  59         (print_mve_unpredictable): Likewise.
  60         (print_mve_rounding_mode): Likewise.
  61         (print_mve_vcvt_size): Likewise.
  62         (print_mve_size): Likewise.
  63         (print_insn_mve): Likewise.
  64
  65 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  66             Michael Collison <michael.collison@arm.com>
  67
  68         * arm-dis.c (enum mve_instructions): Add new instructions.
  69         (enum mve_unpredictable): Add new reasons.
  70         (enum mve_undefined): Likewise.
  71         (is_mve_undefined): Handle new instructions.
  72         (is_mve_unpredictable): Likewise.
  73         (print_mve_undefined): Likewise.
  74         (print_mve_unpredictable): Likewise.
  75         (print_mve_size): Likewise.
  76         (print_insn_mve): Likewise.
  77
  78 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  79             Michael Collison <michael.collison@arm.com>
  80
  81         * arm-dis.c (enum mve_instructions): Add new instructions.
  82         (enum mve_undefined): Add new reasons.
  83         (insns): Add new instructions.
  84         (is_mve_encoding_conflict):
  85         (print_mve_vld_str_addr): New print function.
  86         (is_mve_undefined): Handle new instructions.
  87         (is_mve_unpredictable): Likewise.
  88         (print_mve_undefined): Likewise.
  89         (print_mve_size): Likewise.
  90         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
  91         (print_insn_mve):  Handle new operands.
  92
  93 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  94             Michael Collison <michael.collison@arm.com>
  95
  96         * arm-dis.c (enum mve_instructions): Add new instructions.
  97         (enum mve_unpredictable): Add new reasons.
  98         (is_mve_encoding_conflict): Handle new instructions.
  99         (is_mve_unpredictable): Likewise.
 100         (mve_opcodes): Add new instructions.
 101         (print_mve_unpredictable): Handle new reasons.
 102         (print_mve_register_blocks): New print function.
 103         (print_mve_size): Handle new instructions.
 104         (print_insn_mve): Likewise.
 105
 106 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 107             Michael Collison <michael.collison@arm.com>
 108
 109         * arm-dis.c (enum mve_instructions): Add new instructions.
 110         (enum mve_unpredictable): Add new reasons.
 111         (enum mve_undefined): Likewise.
 112         (is_mve_encoding_conflict): Handle new instructions.
 113         (is_mve_undefined): Likewise.
 114         (is_mve_unpredictable): Likewise.
 115         (coprocessor_opcodes): Move NEON VDUP from here...
 116         (neon_opcodes): ... to here.
 117         (mve_opcodes): Add new instructions.
 118         (print_mve_undefined):  Handle new reasons.
 119         (print_mve_unpredictable): Likewise.
 120         (print_mve_size): Handle new instructions.
 121         (print_insn_neon): Handle vdup.
 122         (print_insn_mve): Handle new operands.
 123
 124 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 125             Michael Collison <michael.collison@arm.com>
 126
 127         * arm-dis.c (enum mve_instructions): Add new instructions.
 128         (enum mve_unpredictable): Add new values.
 129         (mve_opcodes): Add new instructions.
 130         (vec_condnames): New array with vector conditions.
 131         (mve_predicatenames): New array with predicate suffixes.
 132         (mve_vec_sizename): New array with vector sizes.
 133         (enum vpt_pred_state): New enum with vector predication states.
 134         (struct vpt_block): New struct type for vpt blocks.
 135         (vpt_block_state): Global struct to keep track of state.
 136         (mve_extract_pred_mask): New helper function.
 137         (num_instructions_vpt_block): Likewise.
 138         (mark_outside_vpt_block): Likewise.
 139         (mark_inside_vpt_block): Likewise.
 140         (invert_next_predicate_state): Likewise.
 141         (update_next_predicate_state): Likewise.
 142         (update_vpt_block_state): Likewise.
 143         (is_vpt_instruction): Likewise.
 144         (is_mve_encoding_conflict): Add entries for new instructions.
 145         (is_mve_unpredictable): Likewise.
 146         (print_mve_unpredictable): Handle new cases.
 147         (print_instruction_predicate): Likewise.
 148         (print_mve_size): New function.
 149         (print_vec_condition): New function.
 150         (print_insn_mve): Handle vpt blocks and new print operands.
 151
 152 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 153
 154         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 155         8, 14 and 15 for Armv8.1-M Mainline.
 156
 157 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 158             Michael Collison <michael.collison@arm.com>
 159
 160         * arm-dis.c (enum mve_instructions): New enum.
 161         (enum mve_unpredictable): Likewise.
 162         (enum mve_undefined): Likewise.
 163         (struct mopcode32): New struct.
 164         (is_mve_okay_in_it): New function.
 165         (is_mve_architecture): Likewise.
 166         (arm_decode_field): Likewise.
 167         (arm_decode_field_multiple): Likewise.
 168         (is_mve_encoding_conflict): Likewise.
 169         (is_mve_undefined): Likewise.
 170         (is_mve_unpredictable): Likewise.
 171         (print_mve_undefined): Likewise.
 172         (print_mve_unpredictable): Likewise.
 173         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 174         (print_insn_mve): New function.
 175         (print_insn_thumb32): Handle MVE architecture.
 176         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 177
 178 2019-05-10  Nick Clifton  <nickc@redhat.com>
 179
 180         PR 24538
 181         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 182         end of the table prematurely.
 183
 184 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 185
 186         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 187         macros for R6.
 188
 189 2019-05-11  Alan Modra  <amodra@gmail.com>
 190
 191         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 192         when -Mraw is in effect.
 193
 194 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 195
 196         * aarch64-dis-2.c: Regenerate.
 197         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 198         (OP_SVE_BBB): New variant set.
 199         (OP_SVE_DDDD): New variant set.
 200         (OP_SVE_HHH): New variant set.
 201         (OP_SVE_HHHU): New variant set.
 202         (OP_SVE_SSS): New variant set.
 203         (OP_SVE_SSSU): New variant set.
 204         (OP_SVE_SHH): New variant set.
 205         (OP_SVE_SBBU): New variant set.
 206         (OP_SVE_DSS): New variant set.
 207         (OP_SVE_DHHU): New variant set.
 208         (OP_SVE_VMV_HSD_BHS): New variant set.
 209         (OP_SVE_VVU_HSD_BHS): New variant set.
 210         (OP_SVE_VVVU_SD_BH): New variant set.
 211         (OP_SVE_VVVU_BHSD): New variant set.
 212         (OP_SVE_VVV_QHD_DBS): New variant set.
 213         (OP_SVE_VVV_HSD_BHS): New variant set.
 214         (OP_SVE_VVV_HSD_BHS2): New variant set.
 215         (OP_SVE_VVV_BHS_HSD): New variant set.
 216         (OP_SVE_VV_BHS_HSD): New variant set.
 217         (OP_SVE_VVV_SD): New variant set.
 218         (OP_SVE_VVU_BHS_HSD): New variant set.
 219         (OP_SVE_VZVV_SD): New variant set.
 220         (OP_SVE_VZVV_BH): New variant set.
 221         (OP_SVE_VZV_SD): New variant set.
 222         (aarch64_opcode_table): Add sve2 instructions.
 223
 224 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 225
 226         * aarch64-asm-2.c: Regenerated.
 227         * aarch64-dis-2.c: Regenerated.
 228         * aarch64-opc-2.c: Regenerated.
 229         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 230         for SVE_SHLIMM_UNPRED_22.
 231         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 232         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 233         operand.
 234
 235 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 236
 237         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 238         sve_size_tsz_bhs iclass encode.
 239         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 240         sve_size_tsz_bhs iclass decode.
 241
 242 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 243
 244         * aarch64-asm-2.c: Regenerated.
 245         * aarch64-dis-2.c: Regenerated.
 246         * aarch64-opc-2.c: Regenerated.
 247         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 248         for SVE_Zm4_11_INDEX.
 249         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 250         (fields): Handle SVE_i2h field.
 251         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 252         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 253
 254 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 255
 256         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 257         sve_shift_tsz_bhsd iclass encode.
 258         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 259         sve_shift_tsz_bhsd iclass decode.
 260
 261 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 262
 263         * aarch64-asm-2.c: Regenerated.
 264         * aarch64-dis-2.c: Regenerated.
 265         * aarch64-opc-2.c: Regenerated.
 266         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 267         (aarch64_encode_variant_using_iclass): Handle
 268         sve_shift_tsz_hsd iclass encode.
 269         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 270         sve_shift_tsz_hsd iclass decode.
 271         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 272         for SVE_SHRIMM_UNPRED_22.
 273         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 274         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 275         operand.
 276
 277 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 278
 279         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 280         sve_size_013 iclass encode.
 281         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 282         sve_size_013 iclass decode.
 283
 284 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 285
 286         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 287         sve_size_bh iclass encode.
 288         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 289         sve_size_bh iclass decode.
 290
 291 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 292
 293         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 294         sve_size_sd2 iclass encode.
 295         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 296         sve_size_sd2 iclass decode.
 297         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 298         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 299
 300 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 301
 302         * aarch64-asm-2.c: Regenerated.
 303         * aarch64-dis-2.c: Regenerated.
 304         * aarch64-opc-2.c: Regenerated.
 305         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 306         for SVE_ADDR_ZX.
 307         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 308         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 309
 310 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 311
 312         * aarch64-asm-2.c: Regenerated.
 313         * aarch64-dis-2.c: Regenerated.
 314         * aarch64-opc-2.c: Regenerated.
 315         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 316         for SVE_Zm3_11_INDEX.
 317         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 318         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 319         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 320         fields.
 321         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 322
 323 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 324
 325         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 326         sve_size_hsd2 iclass encode.
 327         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 328         sve_size_hsd2 iclass decode.
 329         * aarch64-opc.c (fields): Handle SVE_size field.
 330         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 331
 332 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 333
 334         * aarch64-asm-2.c: Regenerated.
 335         * aarch64-dis-2.c: Regenerated.
 336         * aarch64-opc-2.c: Regenerated.
 337         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 338         for SVE_IMM_ROT3.
 339         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 340         (fields): Handle SVE_rot3 field.
 341         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 342         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 343
 344 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 345
 346         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 347         instructions.
 348
 349 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 350
 351         * aarch64-tbl.h
 352         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 353         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 354         aarch64_feature_sve2bitperm): New feature sets.
 355         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 356         for feature set addresses.
 357         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 358         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 359
 360 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 361             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 362
 363         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 364         argument and set ASE_EVA_R6 appropriately.
 365         (set_default_mips_dis_options): Pass ISA to above.
 366         (parse_mips_dis_option): Likewise.
 367         * mips-opc.c (EVAR6): New macro.
 368         (mips_builtin_opcodes): Add llwpe, scwpe.
 369
 370 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 371
 372         * aarch64-asm-2.c: Regenerated.
 373         * aarch64-dis-2.c: Regenerated.
 374         * aarch64-opc-2.c: Regenerated.
 375         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 376         AARCH64_OPND_TME_UIMM16.
 377         (aarch64_print_operand): Likewise.
 378         * aarch64-tbl.h (QL_IMM_NIL): New.
 379         (TME): New.
 380         (_TME_INSN): New.
 381         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 382
 383 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 384
 385         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 386
 387 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 388             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 389
 390         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 391
 392 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 393
 394         * s12z-opc.h: Add extern "C" bracketing to help
 395         users who wish to use this interface in c++ code.
 396
 397 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 398
 399         * s12z-opc.c (bm_decode): Handle bit map operations with the
 400         "reserved0" mode.
 401
 402 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 403
 404         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 405         specifier.  Add entries for VLDR and VSTR of system registers.
 406         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 407         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 408         of %J and %K format specifier.
 409
 410 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 411
 412         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 413         Add new entries for VSCCLRM instruction.
 414         (print_insn_coprocessor): Handle new %C format control code.
 415
 416 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 417
 418         * arm-dis.c (enum isa): New enum.
 419         (struct sopcode32): New structure.
 420         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 421         set isa field of all current entries to ANY.
 422         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 423         Only match an entry if its isa field allows the current mode.
 424
 425 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 426
 427         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 428         CLRM.
 429         (print_insn_thumb32): Add logic to print %n CLRM register list.
 430
 431 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 432
 433         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 434         and %Q patterns.
 435
 436 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 437
 438         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 439         (print_insn_thumb32): Edit the switch case for %Z.
 440
 441 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 442
 443         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 444
 445 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 446
 447         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 448
 449 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 450
 451         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 452
 453 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 454
 455         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 456         Arm register with r13 and r15 unpredictable.
 457         (thumb32_opcodes): New instructions for bfx and bflx.
 458
 459 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 460
 461         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 462
 463 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 464
 465         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 466
 467 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 468
 469         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 470
 471 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 472
 473         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 474
 475 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 476
 477         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 478         "optr". ("operator" is a reserved word in c++).
 479
 480 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 481
 482         * aarch64-opc.c (aarch64_print_operand): Add case for
 483         AARCH64_OPND_Rt_SP.
 484         (verify_constraints): Likewise.
 485         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 486         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 487         to accept Rt|SP as first operand.
 488         (AARCH64_OPERANDS): Add new Rt_SP.
 489         * aarch64-asm-2.c: Regenerated.
 490         * aarch64-dis-2.c: Regenerated.
 491         * aarch64-opc-2.c: Regenerated.
 492
 493 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 494
 495         * aarch64-asm-2.c: Regenerated.
 496         * aarch64-dis-2.c: Likewise.
 497         * aarch64-opc-2.c: Likewise.
 498         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 499
 500 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 501
 502         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 503
 504 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 505
 506         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 507         * i386-init.h: Regenerated.
 508
 509 2019-04-07  Alan Modra  <amodra@gmail.com>
 510
 511         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 512         op_separator to control printing of spaces, comma and parens
 513         rather than need_comma, need_paren and spaces vars.
 514
 515 2019-04-07  Alan Modra  <amodra@gmail.com>
 516
 517         PR 24421
 518         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 519         (print_insn_neon, print_insn_arm): Likewise.
 520
 521 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 522
 523         * i386-dis-evex.h (evex_table): Updated to support BF16
 524         instructions.
 525         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 526         and EVEX_W_0F3872_P_3.
 527         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 528         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 529         * i386-opc.h (enum): Add CpuAVX512_BF16.
 530         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 531         * i386-opc.tbl: Add AVX512 BF16 instructions.
 532         * i386-init.h: Regenerated.
 533         * i386-tbl.h: Likewise.
 534
 535 2019-04-05  Alan Modra  <amodra@gmail.com>
 536
 537         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 538         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 539         to favour printing of "-" branch hint when using the "y" bit.
 540         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 541
 542 2019-04-05  Alan Modra  <amodra@gmail.com>
 543
 544         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 545         opcode until first operand is output.
 546
 547 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 548
 549         PR gas/24349
 550         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 551         (valid_bo_post_v2): Add support for 'at' branch hints.
 552         (insert_bo): Only error on branch on ctr.
 553         (get_bo_hint_mask): New function.
 554         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 555         for inserting 'at' branch hints.
 556         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 557         for extracting 'at' branch hints.
 558         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 559         (BOE): Delete operand.
 560         (BOM, BOP): New operands.
 561         (RM): Update value.
 562         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 563         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 564         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 565         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 566         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 567         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 568         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 569         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 570         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 571         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 572         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 573         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 574         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 575         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 576         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 577         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 578         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 579         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 580         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 581         bttarl+>: New extended mnemonics.
 582
 583 2019-03-28  Alan Modra  <amodra@gmail.com>
 584
 585         PR 24390
 586         * ppc-opc.c (BTF): Define.
 587         (powerpc_opcodes): Use for mtfsb*.
 588         * ppc-dis.c (print_insn_powerpc): Print fields with both
 589         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 590
 591 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 592
 593         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 594         (mapping_symbol_for_insn): Implement new algorithm.
 595         (print_insn): Remove duplicate code.
 596
 597 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 598
 599         * aarch64-dis.c (print_insn_aarch64):
 600         Implement override.
 601
 602 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 603
 604         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 605         order.
 606
 607 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 608
 609         * aarch64-dis.c (last_stop_offset): New.
 610         (print_insn_aarch64): Use stop_offset.
 611
 612 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 613
 614         PR gas/24359
 615         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 616         CPU_ANY_AVX2_FLAGS.
 617         * i386-init.h: Regenerated.
 618
 619 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 620
 621         PR gas/24348
 622         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 623         vmovdqu16, vmovdqu32 and vmovdqu64.
 624         * i386-tbl.h: Regenerated.
 625
 626 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 627
 628         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 629         from vstrszb, vstrszh, and vstrszf.
 630
 631 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 632
 633         * s390-opc.txt: Add instruction descriptions.
 634
 635 2019-02-08  Jim Wilson  <jimw@sifive.com>
 636
 637         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 638         <bne>: Likewise.
 639
 640 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 641
 642         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 643
 644 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 645
 646         PR binutils/23212
 647         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 648         * aarch64-opc.c (verify_elem_sd): New.
 649         (fields): Add FLD_sz entr.
 650         * aarch64-tbl.h (_SIMD_INSN): New.
 651         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 652         fmulx scalar and vector by element isns.
 653
 654 2019-02-07  Nick Clifton  <nickc@redhat.com>
 655
 656         * po/sv.po: Updated Swedish translation.
 657
 658 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 659
 660         * s390-mkopc.c (main): Accept arch13 as cpu string.
 661         * s390-opc.c: Add new instruction formats and instruction opcode
 662         masks.
 663         * s390-opc.txt: Add new arch13 instructions.
 664
 665 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 666
 667         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 668         (aarch64_opcode): Change encoding for stg, stzg
 669         st2g and st2zg.
 670         * aarch64-asm-2.c: Regenerated.
 671         * aarch64-dis-2.c: Regenerated.
 672         * aarch64-opc-2.c: Regenerated.
 673
 674 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 675
 676         * aarch64-asm-2.c: Regenerated.
 677         * aarch64-dis-2.c: Likewise.
 678         * aarch64-opc-2.c: Likewise.
 679         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 680
 681 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 682             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 683
 684         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 685         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 686         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 687         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 688         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 689         case for ldstgv_indexed.
 690         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 691         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 692         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 693         * aarch64-asm-2.c: Regenerated.
 694         * aarch64-dis-2.c: Regenerated.
 695         * aarch64-opc-2.c: Regenerated.
 696
 697 2019-01-23  Nick Clifton  <nickc@redhat.com>
 698
 699         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 700
 701 2019-01-21  Nick Clifton  <nickc@redhat.com>
 702
 703         * po/de.po: Updated German translation.
 704         * po/uk.po: Updated Ukranian translation.
 705
 706 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 707         * mips-dis.c (mips_arch_choices): Fix typo in
 708         gs464, gs464e and gs264e descriptors.
 709
 710 2019-01-19  Nick Clifton  <nickc@redhat.com>
 711
 712         * configure: Regenerate.
 713         * po/opcodes.pot: Regenerate.
 714
 715 2018-06-24  Nick Clifton  <nickc@redhat.com>
 716
 717         2.32 branch created.
 718
 719 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 720
 721         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 722         if it is null.
 723         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 724         zero.
 725
 726 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 727
 728         * configure: Regenerate.
 729
 730 2019-01-07  Alan Modra  <amodra@gmail.com>
 731
 732         * configure: Regenerate.
 733         * po/POTFILES.in: Regenerate.
 734
 735 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 736
 737         * s12z-opc.c: New file.
 738         * s12z-opc.h: New file.
 739         * s12z-dis.c: Removed all code not directly related to display
 740         of instructions.  Used the interface provided by the new files
 741         instead.
 742         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 743         * Makefile.in: Regenerate.
 744         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 745         * configure: Regenerate.
 746
 747 2019-01-01  Alan Modra  <amodra@gmail.com>
 748
 749         Update year range in copyright notice of all files.
 750
 751 For older changes see ChangeLog-2018
 752 \f
 753 Copyright (C) 2019 Free Software Foundation, Inc.
 754
 755 Copying and distribution of this file, with or without modification,
 756 are permitted in any medium without royalty provided the copyright
 757 notice and this notice are preserved.
 758
 759 Local Variables:
 760 mode: change-log
 761 left-margin: 8
 762 fill-column: 74
 763 version-control: never
 764 End: