opcodes/ChangeLog

   1 2015-12-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>
   2
   3         * arm-dis.c (arm_opcodes): Guard movw, movt cbz, cbnz, clrex, ldrex,
   4         ldrexb, ldrexh, strex, strexb, strexh shared by ARMv6T2 and ARMv8-M by
   5         ARM_EXT2_V6T2_V8M instead of ARM_EXT_V6T2.
   6
   7 2015-12-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>
   8
   9         * arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
  10         stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
  11         ARM_EXT_V8.
  12         (thumb32_opcodes): Add entries for wide ARMv8-M instructions.
  13
  14 2015-12-22  Yoshinori Sato <ysato@users.sourceforge.jp>
  15
  16 opcodes/
  17         * rx-decode.opc (movco): Use uniqe id.
  18         (movli): Likewise.
  19         (stnz): Condition fix.
  20         (mvtacgu): Destination fix.
  21         * rx-decode.c: Regenerate.
  22
  23 2015-12-14  Yoshinori Sato <ysato@users.sourceforge.jp>
  24
  25         * rx-deocde.opc: Add new instructions pattern.
  26         * rx-deocde.c: Regenerate.
  27         * rx-dis.c (register_name): Add new register.
  28
  29 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  30
  31         * aarch64-asm-2.c: Regenerate.
  32         * aarch64-dis-2.c: Regenerate.
  33         * aarch64-opc-2.c: Regenerate.
  34         * aarch64-tbl.h (QL_SSHIFT_H): New.
  35         (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
  36         and fcvtzu to the Adv.SIMD scalar shift by immediate group.
  37
  38 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  39
  40         * aarch64-asm-2.c: Regenerate.
  41         * aarch64-dis-2.c: Regenerate.
  42         * aarch64-opc-2.c: Regenerate.
  43         * aarch64-tbl.h (QL_VSHIFT_H): New.
  44         (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
  45         and fcvtzu to the Adv.SIMD shift by immediate group.
  46
  47 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  48
  49         * aarch64-asm-2.c: Regenerate.
  50         * aarch64-dis-2.c: Regenerate.
  51         * aarch64-opc-2.c: Regenerate.
  52         * aarch64-tbl.h (QL_SISD_PAIR_H): New.
  53         (aarch64_opcode_table): Add fp16 versions of fmaxnmp, faddp,
  54         fmaxp, fminnmp, fminp to the Adv.SIMD scalar pairwise group.
  55
  56 2015-12-14  Matthew Wahab  <matthew.wahab@arm.coM>
  57
  58         * aarch64-dis.c (get_vreg_qualifier_from_value): Update comment
  59         and adjust calculation to ignore qualifier for type 2H.
  60         * aarch64-opc.c (aarch64_opnd_qualifier): Add "2H".
  61
  62 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  63
  64         * aarch64-asm-2.c: Regenerate.
  65         * aarch64-dis-2.c: Regenerate.
  66         * aarch64-opc-2.c: Regenerate.
  67         * aarch64-tbl.h (QL_SIMD_IMM_H): New.
  68         (aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD
  69         modified immediate group.
  70
  71 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  72
  73         * aarch64-asm-2.c: Regenerate.
  74         * aarch64-dis-2.c: Regenerate.
  75         * aarch64-opc-2.c: Regenerate.
  76         * aarch64-tbl.h (QL_XLANES_FP_H): New.
  77         (aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv,
  78         fminnmv, fminv to the Adv.SIMD across lanes group.
  79
  80 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  81
  82         * aarch64-asm-2.c: Regenerate.
  83         * aarch64-dis-2.c: Regenerate.
  84         * aarch64-opc-2.c: Regenerate.
  85         * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla,
  86         fmls, fmul and fmulx to the scalar indexed element group.
  87
  88 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  89
  90         * aarch64-asm-2.c: Regenerate.
  91         * aarch64-dis-2.c: Regenerate.
  92         * aarch64-opc-2.c: Regenerate.
  93         * aarch64-tbl.h (QL_ELEMENT_FP_H): New.
  94         (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
  95         fmulx to the vector indexed element group.
  96
  97 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  98
  99         * aarch64-asm-2.c: Regenerate.
 100         * aarch64-dis-2.c: Regenerate.
 101         * aarch64-opc-2.c: Regenerate.
 102         * aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
 103         (QL_S_2SAMEH): New.
 104         (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
 105         fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
 106         frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
 107         fcvtzu and frsqrte to the scalar two register misc. group.
 108
 109 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
 110
 111         * aarch64-asm-2.c: Regenerate.
 112         * aarch64-dis-2.c: Regenerate.
 113         * aarch64-opc-2.c: Regenerate.
 114         * aarch64-tbl.h (QL_V2SAMEH): New.
 115         (aarch64_opcode_table): Add fp16 versions of frintn, frintm,
 116         fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
 117         frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
 118         fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
 119         and fsqrt to the vector register misc. group.
 120
 121 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
 122
 123         * aarch64-asm-2.c: Regenerate.
 124         * aarch64-dis-2.c: Regenerate.
 125         * aarch64-opc-2.c: Regenerate.
 126         * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
 127         fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and facgt
 128         to the scalar three same group.
 129
 130 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
 131
 132         * aarch64-asm-2.c: Regenerate.
 133         * aarch64-dis-2.c: Regenerate.
 134         * aarch64-opc-2.c: Regenerate.
 135         * aarch64-tbl.h (QL_V3SAMEH): New.
 136         (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
 137         fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
 138         fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
 139         fcmgt, facgt and fminp to the vector three same group.
 140
 141 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
 142
 143         * aarch64-tbl.h (aarch64_feature_simd_f16): New.
 144         (SIMD_F16): New.
 145
 146 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
 147
 148         * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
 149         removed statement.
 150         (aarch64_pstatefield_supported_p): Move feature checks for AT
 151         registers ..
 152         (aarch64_sys_ins_reg_supported_p): .. to here.
 153
 154 2015-12-12  Alan Modra  <amodra@gmail.com>
 155
 156         PR 19359
 157         * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
 158         (powerpc_opcodes): Remove single-operand mfcr.
 159
 160 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
 161
 162         * aarch64-asm.c (aarch64_ins_hint): New.
 163         * aarch64-asm.h (aarch64_ins_hint): Declare.
 164         * aarch64-dis.c (aarch64_ext_hint): New.
 165         * aarch64-dis.h (aarch64_ext_hint): Declare.
 166         * aarch64-opc-2.c: Regenerate.
 167         * aarch64-opc.c (aarch64_hint_options): New.
 168         * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
 169
 170 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
 171
 172         * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
 173
 174 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
 175
 176         * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
 177         pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
 178         pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
 179         pmscr_el2.
 180         (aarch64_sys_reg_supported_p): Add architecture feature tests for
 181         the new registers.
 182
 183 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 184
 185         * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
 186         (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
 187         feature test for "s1e1rp" and "s1e1wp".
 188
 189 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 190
 191         * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
 192         (aarch64_sys_ins_reg_supported_p): New.
 193
 194 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 195
 196         * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
 197         with aarch64_sys_ins_reg_has_xt.
 198         (aarch64_ext_sysins_op): Likewise.
 199         * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
 200         (F_HASXT): New.
 201         (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
 202         (aarch64_sys_regs_dc): Likewise.
 203         (aarch64_sys_regs_at): Likewise.
 204         (aarch64_sys_regs_tlbi): Likewise.
 205         (aarch64_sys_ins_reg_has_xt): New.
 206
 207 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 208
 209         * aarch64-opc.c (aarch64_sys_regs): Add "uao".
 210         (aarch64_sys_reg_supported_p): Add comment.  Add checks for "uao".
 211         (aarch64_pstatefields): Add "uao".
 212         (aarch64_pstatefield_supported_p): Add checks for "uao".
 213
 214 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 215
 216         * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
 217         "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
 218         "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
 219         (aarch64_sys_reg_supported_p): Add architecture feature tests for
 220         new registers.
 221
 222 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 223
 224         * aarch64-asm-2.c: Regenerate.
 225         * aarch64-dis-2.c: Regenerate.
 226         * aarch64-tbl.h (aarch64_feature_ras): New.
 227         (RAS): New.
 228         (aarch64_opcode_table): Add "esb".
 229
 230 2015-12-09  H.J. Lu  <hongjiu.lu@intel.com>
 231
 232         * i386-dis.c (MOD_0F01_REG_5): New.
 233         (RM_0F01_REG_5): Likewise.
 234         (reg_table): Use MOD_0F01_REG_5.
 235         (mod_table): Add MOD_0F01_REG_5.
 236         (rm_table): Add RM_0F01_REG_5.
 237         * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
 238         (cpu_flags): Add CpuOSPKE.
 239         * i386-opc.h (CpuOSPKE): New.
 240         (i386_cpu_flags): Add cpuospke.
 241         * i386-opc.tbl: Add rdpkru and wrpkru instructions.
 242         * i386-init.h: Regenerated.
 243         * i386-tbl.h: Likewise.
 244
 245 2015-12-07  DJ Delorie  <dj@redhat.com>
 246
 247         * rl78-decode.opc: Enable MULU for all ISAs.
 248         * rl78-decode.c: Regenerate.
 249
 250 2015-12-07  Alan Modra  <amodra@gmail.com>
 251
 252         * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
 253         major opcode/xop.
 254
 255 2015-12-04  Claudiu Zissulescu  <claziss@synopsys.com>
 256
 257         * arc-dis.c (special_flag_p): Match full mnemonic.
 258         * arc-opc.c (print_insn_arc): Check section size to read
 259         appropriate number of bytes. Fix printing.
 260         * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
 261         arguments.
 262
 263 2015-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 264
 265         * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
 266         <ldah>: ... to this.
 267
 268 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 269
 270         * aarch64-asm-2.c: Regenerate.
 271         * aarch64-dis-2.c: Regenerate.
 272         * aarch64-opc-2.c: Regenerate.
 273         * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
 274         (QL_INT2FP_H, QL_FP2INT_H): New.
 275         (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
 276         (QL_DST_H): New.
 277         (QL_FCCMP_H): New.
 278         (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
 279         fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
 280         fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
 281         fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
 282         frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
 283         fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
 284         fcsel.
 285
 286 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 287
 288         * aarch64-opc.c (half_conv_t): New.
 289         (expand_fp_imm): Replace is_dp flag with the parameter size to
 290         specify the number of bytes for the required expansion.  Treat
 291         a 16-bit expansion like a 32-bit expansion.  Add check for an
 292         unsupported size request.  Update comment.
 293         (aarch64_print_operand): Update to support 16-bit floating point
 294         values.  Update for changes to expand_fp_imm.
 295
 296 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 297
 298         * aarch64-tbl.h (aarch64_feature_fp_f16): New.
 299         (FP_F16): New.
 300
 301 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 302
 303         * aarch64-asm-2.c: Regenerate.
 304         * aarch64-dis-2.c: Regenerate.
 305         * aarch64-opc-2.c: Regenerate.
 306         * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
 307         "rev64".
 308
 309 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 310
 311         * aarch64-asm-2.c: Regenerate.
 312         * aarch64-asm.c (convert_bfc_to_bfm): New.
 313         (convert_to_real): Add case for OP_BFC.
 314         * aarch64-dis-2.c: Regenerate.
 315         * aarch64-dis.c: (convert_bfm_to_bfc): New.
 316         (convert_to_alias): Add case for OP_BFC.
 317         * aarch64-opc-2.c: Regenerate.
 318         * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
 319         to allow width operand in three-operand instructions.
 320         * aarch64-tbl.h (QL_BF1): New.
 321         (aarch64_feature_v8_2): New.
 322         (ARMV8_2): New.
 323         (aarch64_opcode_table): Add "bfc".
 324
 325 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 326
 327         * aarch64-asm-2.c: Regenerate.
 328         * aarch64-dis-2.c: Regenerate.
 329         * aarch64-dis.c: Weaken assert.
 330         * aarch64-gen.c: Include the instruction in the list of its
 331         possible aliases.
 332
 333 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 334
 335         * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
 336         (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
 337         feature test.
 338
 339 2015-11-23  Tristan Gingold  <gingold@adacore.com>
 340
 341         * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
 342
 343 2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>
 344
 345         * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
 346         sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
 347         tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
 348         amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
 349         cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
 350         cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
 351         cnthv_ctl_el2, cnthv_cval_el2.
 352         (aarch64_sys_reg_supported_p): Update for the new system
 353         registers.
 354
 355 2015-11-20  Nick Clifton  <nickc@redhat.com>
 356
 357         PR binutils/19224
 358         * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
 359
 360 2015-11-20  Nick Clifton  <nickc@redhat.com>
 361
 362         * po/zh_CN.po: Updated simplified Chinese translation.
 363
 364 2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>
 365
 366         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 367         of MSR PAN immediate operand.
 368
 369 2015-11-16  Nick Clifton  <nickc@redhat.com>
 370
 371         * rx-dis.c (condition_names): Replace always and never with
 372         invalid, since the always/never conditions can never be legal.
 373
 374 2015-11-13  Tristan Gingold  <gingold@adacore.com>
 375
 376         * configure: Regenerate.
 377
 378 2015-11-11  Alan Modra  <amodra@gmail.com>
 379             Peter Bergner <bergner@vnet.ibm.com>
 380
 381         * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
 382         Add PPC_OPCODE_VSX3 to the vsx entry.
 383         (powerpc_init_dialect): Set default dialect to power9.
 384         * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
 385         insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
 386         extract_l1 insert_xtq6, extract_xtq6): New static functions.
 387         (insert_esync): Test for illegal L operand value.
 388         (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
 389         XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
 390         XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
 391         XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
 392         PPCVSX3): New defines.
 393         (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
 394         fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
 395         <mcrxr>: Use XBFRARB_MASK.
 396         <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
 397         bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
 398         cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
 399         cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
 400         lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
 401         lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
 402         modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
 403         rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
 404         stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
 405         subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
 406         vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
 407         vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
 408         vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
 409         vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
 410         vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
 411         vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
 412         vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
 413         xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
 414         xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
 415         xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
 416         xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
 417         xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
 418         xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
 419         xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
 420         xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
 421         xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
 422         xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
 423         xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
 424         xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
 425         xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
 426         <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
 427         <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
 428
 429 2015-11-02  Nick Clifton  <nickc@redhat.com>
 430
 431         * rx-decode.opc (rx_decode_opcode): Decode extra NOP
 432         instructions.
 433         * rx-decode.c: Regenerate.
 434
 435 2015-11-02  Nick Clifton  <nickc@redhat.com>
 436
 437         * rx-decode.opc (rx_disp): If the displacement is zero, set the
 438         type to RX_Operand_Zero_Indirect.
 439         * rx-decode.c: Regenerate.
 440         * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
 441
 442 2015-10-28  Yao Qi  <yao.qi@linaro.org>
 443
 444         * aarch64-dis.c (aarch64_decode_insn): Add one argument
 445         noaliases_p.  Update comments.  Pass noaliases_p rather than
 446         no_aliases to aarch64_opcode_decode.
 447         (print_insn_aarch64_word): Pass no_aliases to
 448         aarch64_decode_insn.
 449
 450 2015-10-27  Vinay  <Vinay.G@kpit.com>
 451
 452         PR binutils/19159
 453         * rl78-decode.opc (MOV): Added offset to DE register in index
 454         addressing mode.
 455         * rl78-decode.c: Regenerate.
 456
 457 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 458
 459         PR binutils/19158
 460         * rl78-decode.opc: Add 's' print operator to instructions that
 461         access system registers.
 462         * rl78-decode.c: Regenerate.
 463         * rl78-dis.c (print_insn_rl78_common): Decode all system
 464         registers.
 465
 466 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 467
 468         PR binutils/19157
 469         * rl78-decode.opc: Add 'a' print operator to mov instructions
 470         using stack pointer plus index addressing.
 471         * rl78-decode.c: Regenerate.
 472
 473 2015-10-14  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 474
 475         * s390-opc.c: Fix comment.
 476         * s390-opc.txt: Change instruction type for troo, trot, trto, and
 477         trtt to RRF_U0RER since the second parameter does not need to be a
 478         register pair.
 479
 480 2015-10-08  Nick Clifton  <nickc@redhat.com>
 481
 482         * arc-dis.c (print_insn_arc): Initiallise insn array.
 483
 484 2015-10-07  Yao Qi  <yao.qi@linaro.org>
 485
 486         * aarch64-dis.c (aarch64_ext_sysins_op): Access field
 487         'name' rather than 'template'.
 488         * aarch64-opc.c (aarch64_print_operand): Likewise.
 489
 490 2015-10-07  Claudiu Zissulescu <claziss@synopsys.com>
 491
 492         * arc-dis.c: Revamped file for ARC support
 493         * arc-dis.h: Likewise.
 494         * arc-ext.c: Likewise.
 495         * arc-ext.h: Likewise.
 496         * arc-opc.c: Likewise.
 497         * arc-fxi.h: New file.
 498         * arc-regs.h: Likewise.
 499         * arc-tbl.h: Likewise.
 500
 501 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 502
 503         * aarch64-dis.c (disas_aarch64_insn): Remove static.  Change
 504         argument insn type to aarch64_insn.  Rename to ...
 505         (aarch64_decode_insn): ... it.
 506         (print_insn_aarch64_word): Caller updated.
 507
 508 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 509
 510         * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
 511         (print_insn_aarch64_word): Caller updated.
 512
 513 2015-09-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>
 514
 515         * s390-mkopc.c (main): Parse htm and vx flag.
 516         * s390-opc.txt: Mark instructions from the hardware transactional
 517         memory and vector facilities with the "htm"/"vx" flag.
 518
 519 2015-09-28  Nick Clifton  <nickc@redhat.com>
 520
 521         * po/de.po: Updated German translation.
 522
 523 2015-09-28  Tom Rix  <tom@bumblecow.com>
 524
 525         * ppc-opc.c (PPC500): Mark some opcodes as invalid
 526
 527 2015-09-23  Nick Clifton  <nickc@redhat.com>
 528
 529         * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
 530         function.
 531         * tic30-dis.c (print_branch): Likewise.
 532         * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
 533         value before left shifting.
 534         * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
 535         * hppa-dis.c (print_insn_hppa): Likewise.
 536         * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
 537         array.
 538         * msp430-dis.c (msp430_singleoperand): Likewise.
 539         (msp430_doubleoperand): Likewise.
 540         (print_insn_msp430): Likewise.
 541         * nds32-asm.c (parse_operand): Likewise.
 542         * sh-opc.h (MASK): Likewise.
 543         * v850-dis.c (get_operand_value): Likewise.
 544
 545 2015-09-22  Nick Clifton  <nickc@redhat.com>
 546
 547         * rx-decode.opc (bwl): Use RX_Bad_Size.
 548         (sbwl): Likewise.
 549         (ubwl): Likewise.  Rename to ubw.
 550         (uBWL): Rename to uBW.
 551         Replace all references to uBWL with uBW.
 552         * rx-decode.c: Regenerate.
 553         * rx-dis.c (size_names): Add entry for RX_Bad_Size.
 554         (opsize_names): Likewise.
 555         (print_insn_rx): Detect and report RX_Bad_Size.
 556
 557 2015-09-22  Anton Blanchard  <anton@samba.org>
 558
 559         * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
 560
 561 2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>
 562
 563         * sparc-dis.c (print_insn_sparc): Handle the privileged register
 564         %pmcdper.
 565
 566 2015-08-24  Jan Stancek  <jstancek@redhat.com>
 567
 568         * i386-dis.c (print_insn): Fix decoding of three byte operands.
 569
 570 2015-08-21  Alexander Fomin  <alexander.fomin@intel.com>
 571
 572         PR binutils/18257
 573         * i386-dis.c: Use MOD_TABLE for most of mask instructions.
 574         (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
 575         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 576         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 577         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 578         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 579         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 580         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 581         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 582         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 583         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 584         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 585         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 586         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 587         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 588         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 589         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 590         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 591         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 592         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 593         MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
 594         MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
 595         MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
 596         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 597         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 598         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 599         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 600         MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 601         MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 602         MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 603         MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
 604         (vex_w_table): Replace terminals with MOD_TABLE entries for
 605         most of mask instructions.
 606
 607 2015-08-17  Alan Modra  <amodra@gmail.com>
 608
 609         * cgen.sh: Trim trailing space from cgen output.
 610         * ia64-gen.c (print_dependency_table): Don't generate trailing space.
 611         (print_dis_table): Likewise.
 612         * opc2c.c (dump_lines): Likewise.
 613         (orig_filename): Warning fix.
 614         * ia64-asmtab.c: Regenerate.
 615
 616 2015-08-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 617
 618         * arm-dis.c (print_insn_arm): Disassembling for all targets V6
 619         and higher with ARM instruction set will now mark the 26-bit
 620         versions of teq,tst,cmn and cmp as UNPREDICTABLE.
 621         (arm_opcodes): Fix for unpredictable nop being recognized as a
 622         teq.
 623
 624 2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
 625
 626         * micromips-opc.c (micromips_opcodes): Re-order table so that move
 627         based on 'or' is first.
 628         * mips-opc.c (mips_builtin_opcodes): Ditto.
 629
 630 2015-08-11  Nick Clifton  <nickc@redhat.com>
 631
 632         PR 18800
 633         * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
 634         instruction.
 635
 636 2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
 637
 638         * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
 639
 640 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
 641
 642         * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
 643         * i386-init.h: Regenerated.
 644
 645 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 646
 647         PR binutils/13571
 648         * i386-dis.c (MOD_0FC3): New.
 649         (PREFIX_0FC3): Renamed to ...
 650         (PREFIX_MOD_0_0FC3): This.
 651         (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
 652         (prefix_table): Replace Ma with Ev on movntiS.
 653         (mod_table): Add MOD_0FC3.
 654
 655 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
 656
 657         * configure: Regenerated.
 658
 659 2015-07-23  Alan Modra  <amodra@gmail.com>
 660
 661         PR 18708
 662         * i386-dis.c (get64): Avoid signed integer overflow.
 663
 664 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
 665
 666         PR binutils/18631
 667         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
 668         "EXEvexHalfBcstXmmq" for the second operand.
 669         (EVEX_W_0F79_P_2): Likewise.
 670         (EVEX_W_0F7A_P_2): Likewise.
 671         (EVEX_W_0F7B_P_2): Likewise.
 672
 673 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
 674
 675         * arm-dis.c (print_insn_coprocessor): Added support for quarter
 676         float bitfield format.
 677         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
 678         quarter float bitfield format.
 679
 680 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 681
 682         * configure: Regenerated.
 683
 684 2015-07-03  Alan Modra  <amodra@gmail.com>
 685
 686         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
 687         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
 688         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
 689
 690 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
 691             Cesar Philippidis  <cesar@codesourcery.com>
 692
 693         * nios2-dis.c (nios2_extract_opcode): New.
 694         (nios2_disassembler_state): New.
 695         (nios2_find_opcode_hash): Use mach parameter to select correct
 696         disassembler state.
 697         (nios2_print_insn_arg): Extend to support new R2 argument letters
 698         and formats.
 699         (print_insn_nios2): Check for 16-bit instruction at end of memory.
 700         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
 701         (NIOS2_NUM_OPCODES): Rename to...
 702         (NIOS2_NUM_R1_OPCODES): This.
 703         (nios2_r2_opcodes): New.
 704         (NIOS2_NUM_R2_OPCODES): New.
 705         (nios2_num_r2_opcodes): New.
 706         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
 707         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
 708         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
 709         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
 710         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
 711
 712 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
 713
 714         * i386-dis.c (OP_Mwaitx): New.
 715         (rm_table): Add monitorx/mwaitx.
 716         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
 717         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
 718         (operand_type_init): Add CpuMWAITX.
 719         * i386-opc.h (CpuMWAITX): New.
 720         (i386_cpu_flags): Add cpumwaitx.
 721         * i386-opc.tbl: Add monitorx and mwaitx.
 722         * i386-init.h: Regenerated.
 723         * i386-tbl.h: Likewise.
 724
 725 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
 726
 727         * ppc-opc.c (insert_ls): Test for invalid LS operands.
 728         (insert_esync): New function.
 729         (LS, WC): Use insert_ls.
 730         (ESYNC): Use insert_esync.
 731
 732 2015-06-22  Nick Clifton  <nickc@redhat.com>
 733
 734         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
 735         requested region lies beyond it.
 736         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
 737         looking for 32-bit insns.
 738         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
 739         data.
 740         * sh-dis.c (print_insn_sh): Likewise.
 741         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
 742         blocks of instructions.
 743         * vax-dis.c (print_insn_vax): Check that the requested address
 744         does not clash with the stop_vma.
 745
 746 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
 747
 748         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
 749         * ppc-opc.c (FXM4): Add non-zero optional value.
 750         (TBR): Likewise.
 751         (SXL): Likewise.
 752         (insert_fxm): Handle new default operand value.
 753         (extract_fxm): Likewise.
 754         (insert_tbr): Likewise.
 755         (extract_tbr): Likewise.
 756
 757 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 758
 759         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 760
 761 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 762
 763         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 764
 765 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 766
 767         * ppc-opc.c: Add comment accidentally removed by old commit.
 768         (MTMSRD_L): Delete.
 769
 770 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 771
 772         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 773
 774 2015-06-04  Nick Clifton  <nickc@redhat.com>
 775
 776         PR 18474
 777         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 778
 779 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 780
 781         * arm-dis.c (arm_opcodes): Add "setpan".
 782         (thumb_opcodes): Add "setpan".
 783
 784 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 785
 786         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 787         macros.
 788
 789 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 790
 791         * aarch64-tbl.h (aarch64_feature_rdma): New.
 792         (RDMA): New.
 793         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 794         * aarch64-asm-2.c: Regenerate.
 795         * aarch64-dis-2.c: Regenerate.
 796         * aarch64-opc-2.c: Regenerate.
 797
 798 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 799
 800         * aarch64-tbl.h (aarch64_feature_lor): New.
 801         (LOR): New.
 802         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 803         "stllrb", "stllrh".
 804         * aarch64-asm-2.c: Regenerate.
 805         * aarch64-dis-2.c: Regenerate.
 806         * aarch64-opc-2.c: Regenerate.
 807
 808 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 809
 810         * aarch64-opc.c (F_ARCHEXT): New.
 811         (aarch64_sys_regs): Add "pan".
 812         (aarch64_sys_reg_supported_p): New.
 813         (aarch64_pstatefields): Add "pan".
 814         (aarch64_pstatefield_supported_p): New.
 815
 816 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 817
 818         * i386-tbl.h: Regenerate.
 819
 820 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 821
 822         * i386-dis.c (print_insn): Swap rounding mode specifier and
 823         general purpose register in Intel mode.
 824
 825 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 826
 827         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 828         * i386-tbl.h: Regenerate.
 829
 830 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 831
 832         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 833         * i386-init.h: Regenerated.
 834
 835 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 836
 837         PR binutis/18386
 838         * i386-dis.c: Add comments for '@'.
 839         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 840         (enum x86_64_isa): New.
 841         (isa64): Likewise.
 842         (print_i386_disassembler_options): Add amd64 and intel64.
 843         (print_insn): Handle amd64 and intel64.
 844         (putop): Handle '@'.
 845         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 846         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 847         * i386-opc.h (AMD64): New.
 848         (CpuIntel64): Likewise.
 849         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 850         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 851         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 852         * i386-init.h: Regenerated.
 853         * i386-tbl.h: Likewise.
 854
 855 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 856
 857         * ppc-opc.c (IH) New define.
 858         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 859         <tlbie>: Add RS operand for POWER7.
 860         <slbia>: Add IH operand for POWER6.
 861
 862 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 863
 864         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 865         direct branch.
 866         (jmp): Likewise.
 867         * i386-tbl.h: Regenerated.
 868
 869 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 870
 871         * configure.ac: Support bfd_iamcu_arch.
 872         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 873         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 874         CPU_IAMCU_COMPAT_FLAGS.
 875         (cpu_flags): Add CpuIAMCU.
 876         * i386-opc.h (CpuIAMCU): New.
 877         (i386_cpu_flags): Add cpuiamcu.
 878         * configure: Regenerated.
 879         * i386-init.h: Likewise.
 880         * i386-tbl.h: Likewise.
 881
 882 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 883
 884         PR binutis/18386
 885         * i386-dis.c (X86_64_E8): New.
 886         (X86_64_E9): Likewise.
 887         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 888         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 889         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 890         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 891         (putop): Handle '^'.
 892         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 893         REX_W.
 894
 895 2015-04-30  DJ Delorie  <dj@redhat.com>
 896
 897         * disassemble.c (disassembler): Choose suitable disassembler based
 898         on E_ABI.
 899         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 900         it to decode mul/div insns.
 901         * rl78-decode.c: Regenerate.
 902         * rl78-dis.c (print_insn_rl78): Rename to...
 903         (print_insn_rl78_common): ...this, take ISA parameter.
 904         (print_insn_rl78): New.
 905         (print_insn_rl78_g10): New.
 906         (print_insn_rl78_g13): New.
 907         (print_insn_rl78_g14): New.
 908         (rl78_get_disassembler): New.
 909
 910 2015-04-29  Nick Clifton  <nickc@redhat.com>
 911
 912         * po/fr.po: Updated French translation.
 913
 914 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 915
 916         * ppc-opc.c (DCBT_EO): New define.
 917         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 918         <lharx>: Likewise.
 919         <stbcx.>: Likewise.
 920         <sthcx.>: Likewise.
 921         <waitrsv>: Do not enable for POWER7 and later.
 922         <waitimpl>: Likewise.
 923         <dcbt>: Default to the two operand form of the instruction for all
 924         "old" cpus.  For "new" cpus, use the operand ordering that matches
 925         whether the cpu is server or embedded.
 926         <dcbtst>: Likewise.
 927
 928 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 929
 930         * s390-opc.c: New instruction type VV0UU2.
 931         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 932         and WFC.
 933
 934 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 935
 936         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 937         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 938         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 939         (vfpclasspd, vfpclassps): Add %XZ.
 940
 941 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 942
 943         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 944         (PREFIX_UD_REPZ): Likewise.
 945         (PREFIX_UD_REPNZ): Likewise.
 946         (PREFIX_UD_DATA): Likewise.
 947         (PREFIX_UD_ADDR): Likewise.
 948         (PREFIX_UD_LOCK): Likewise.
 949
 950 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 951
 952         * i386-dis.c (prefix_requirement): Removed.
 953         (print_insn): Don't set prefix_requirement.  Check
 954         dp->prefix_requirement instead of prefix_requirement.
 955
 956 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 957
 958         PR binutils/17898
 959         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 960         (PREFIX_MOD_0_0FC7_REG_6): This.
 961         (PREFIX_MOD_3_0FC7_REG_6): New.
 962         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 963         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 964         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 965         PREFIX_MOD_3_0FC7_REG_7.
 966         (mod_table): Replace PREFIX_0FC7_REG_6 with
 967         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 968         PREFIX_MOD_3_0FC7_REG_7.
 969
 970 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 971
 972         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 973         (PREFIX_MANDATORY_REPNZ): Likewise.
 974         (PREFIX_MANDATORY_DATA): Likewise.
 975         (PREFIX_MANDATORY_ADDR): Likewise.
 976         (PREFIX_MANDATORY_LOCK): Likewise.
 977         (PREFIX_MANDATORY): Likewise.
 978         (PREFIX_UD_SHIFT): Set to 8
 979         (PREFIX_UD_REPZ): Updated.
 980         (PREFIX_UD_REPNZ): Likewise.
 981         (PREFIX_UD_DATA): Likewise.
 982         (PREFIX_UD_ADDR): Likewise.
 983         (PREFIX_UD_LOCK): Likewise.
 984         (PREFIX_IGNORED_SHIFT): New.
 985         (PREFIX_IGNORED_REPZ): Likewise.
 986         (PREFIX_IGNORED_REPNZ): Likewise.
 987         (PREFIX_IGNORED_DATA): Likewise.
 988         (PREFIX_IGNORED_ADDR): Likewise.
 989         (PREFIX_IGNORED_LOCK): Likewise.
 990         (PREFIX_OPCODE): Likewise.
 991         (PREFIX_IGNORED): Likewise.
 992         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 993         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 994         (three_byte_table): Likewise.
 995         (mod_table): Likewise.
 996         (mandatory_prefix): Renamed to ...
 997         (prefix_requirement): This.
 998         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 999         Update PREFIX_90 entry.
1000         (get_valid_dis386): Check prefix_requirement to see if a prefix
1001         should be ignored.
1002         (print_insn): Replace mandatory_prefix with prefix_requirement.
1003
1004 2015-04-15  Renlin Li  <renlin.li@arm.com>
1005
1006         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
1007         use it for ssat and ssat16.
1008         (print_insn_thumb32): Add handle case for 'D' control code.
1009
1010 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
1011             H.J. Lu  <hongjiu.lu@intel.com>
1012
1013         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
1014         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
1015         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
1016         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
1017         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
1018         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
1019         Fill prefix_requirement field.
1020         (struct dis386): Add prefix_requirement field.
1021         (dis386): Fill prefix_requirement field.
1022         (dis386_twobyte): Ditto.
1023         (twobyte_has_mandatory_prefix_: Remove.
1024         (reg_table): Fill prefix_requirement field.
1025         (prefix_table): Ditto.
1026         (x86_64_table): Ditto.
1027         (three_byte_table): Ditto.
1028         (xop_table): Ditto.
1029         (vex_table): Ditto.
1030         (vex_len_table): Ditto.
1031         (vex_w_table): Ditto.
1032         (mod_table): Ditto.
1033         (bad_opcode): Ditto.
1034         (print_insn): Use prefix_requirement.
1035         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
1036         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
1037         (float_reg): Ditto.
1038
1039 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
1040
1041         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
1042
1043 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1044
1045         * Makefile.in: Regenerated.
1046
1047 2015-03-25  Anton Blanchard  <anton@samba.org>
1048
1049         * ppc-dis.c (disassemble_init_powerpc): Only initialise
1050         powerpc_opcd_indices and vle_opcd_indices once.
1051
1052 2015-03-25  Anton Blanchard  <anton@samba.org>
1053
1054         * ppc-opc.c (powerpc_opcodes): Add slbfee.
1055
1056 2015-03-24  Terry Guo  <terry.guo@arm.com>
1057
1058         * arm-dis.c (opcode32): Updated to use new arm feature struct.
1059         (opcode16): Likewise.
1060         (coprocessor_opcodes): Replace bit with feature struct.
1061         (neon_opcodes): Likewise.
1062         (arm_opcodes): Likewise.
1063         (thumb_opcodes): Likewise.
1064         (thumb32_opcodes): Likewise.
1065         (print_insn_coprocessor): Likewise.
1066         (print_insn_arm): Likewise.
1067         (select_arm_features): Follow new feature struct.
1068
1069 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
1070
1071         * i386-dis.c (rm_table): Add clzero.
1072         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
1073         Add CPU_CLZERO_FLAGS.
1074         (cpu_flags): Add CpuCLZERO.
1075         * i386-opc.h: Add CpuCLZERO.
1076         * i386-opc.tbl: Add clzero.
1077         * i386-init.h: Re-generated.
1078         * i386-tbl.h: Re-generated.
1079
1080 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
1081
1082         * mips-opc.c (decode_mips_operand): Fix constraint issues
1083         with u and y operands.
1084
1085 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
1086
1087         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
1088
1089 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1090
1091         * s390-opc.c: Add new IBM z13 instructions.
1092         * s390-opc.txt: Likewise.
1093
1094 2015-03-10  Renlin Li  <renlin.li@arm.com>
1095
1096         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
1097         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
1098         related alias.
1099         * aarch64-asm-2.c: Regenerate.
1100         * aarch64-dis-2.c: Likewise.
1101         * aarch64-opc-2.c: Likewise.
1102
1103 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
1104
1105         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
1106
1107 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
1108
1109         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
1110         arch_sh_up.
1111         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
1112         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
1113
1114 2015-02-23  Vinay  <Vinay.G@kpit.com>
1115
1116         * rl78-decode.opc (MOV): Added space between two operands for
1117         'mov' instruction in index addressing mode.
1118         * rl78-decode.c: Regenerate.
1119
1120 2015-02-19  Pedro Alves  <palves@redhat.com>
1121
1122         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
1123
1124 2015-02-10  Pedro Alves  <palves@redhat.com>
1125             Tom Tromey  <tromey@redhat.com>
1126
1127         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
1128         microblaze_and, microblaze_xor.
1129         * microblaze-opc.h (opcodes): Adjust.
1130
1131 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
1132
1133         * Makefile.am: Add FT32 files.
1134         * configure.ac: Handle FT32.
1135         * disassemble.c (disassembler): Call print_insn_ft32.
1136         * ft32-dis.c: New file.
1137         * ft32-opc.c: New file.
1138         * Makefile.in: Regenerate.
1139         * configure: Regenerate.
1140         * po/POTFILES.in: Regenerate.
1141
1142 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
1143
1144         * nds32-asm.c (keyword_sr): Add new system registers.
1145
1146 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1147
1148         * s390-dis.c (s390_extract_operand): Support vector register
1149         operands.
1150         (s390_print_insn_with_opcode): Support new operands types and add
1151         new handling of optional operands.
1152         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
1153         and include opcode/s390.h instead.
1154         (struct op_struct): New field `flags'.
1155         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
1156         (dumpTable): Dump flags.
1157         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
1158         string.
1159         * s390-opc.c: Add new operands types, instruction formats, and
1160         instruction masks.
1161         (s390_opformats): Add new formats for .insn.
1162         * s390-opc.txt: Add new instructions.
1163
1164 2015-01-01  Alan Modra  <amodra@gmail.com>
1165
1166         Update year range in copyright notice of all files.
1167
1168 For older changes see ChangeLog-2014
1169 \f
1170 Copyright (C) 2015 Free Software Foundation, Inc.
1171
1172 Copying and distribution of this file, with or without modification,
1173 are permitted in any medium without royalty provided the copyright
1174 notice and this notice are preserved.
1175
1176 Local Variables:
1177 mode: change-log
1178 left-margin: 8
1179 fill-column: 74
1180 version-control: never
1181 End: