1 2019-07-01 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl (C): New.
4 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
5 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
6 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
7 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
8 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
9 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
10 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
11 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
12 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
13 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
14 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
15 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
16 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
17 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
18 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
19 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
20 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
21 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
22 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
23 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
24 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
25 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
26 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
27 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
28 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
29 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
31 * i386-tbl.h: Re-generate.
33 2019-07-01 Jan Beulich <jbeulich@suse.com>
35 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
37 * i386-tbl.h: Re-generate.
39 2019-07-01 Jan Beulich <jbeulich@suse.com>
41 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
42 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
43 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
44 * i386-tbl.h: Re-generate.
46 2019-07-01 Jan Beulich <jbeulich@suse.com>
48 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
49 Disp8MemShift from register only templates.
50 * i386-tbl.h: Re-generate.
52 2019-07-01 Jan Beulich <jbeulich@suse.com>
54 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
55 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
56 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
57 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
58 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
59 EVEX_W_0F11_P_3_M_1): Delete.
60 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
61 EVEX_W_0F11_P_3): New.
62 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
63 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
64 MOD_EVEX_0F11_PREFIX_3 table entries.
65 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
66 PREFIX_EVEX_0F11 table entries.
67 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
68 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
69 EVEX_W_0F11_P_3_M_{0,1} table entries.
71 2019-07-01 Jan Beulich <jbeulich@suse.com>
73 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
76 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
79 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
80 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
81 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
82 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
83 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
84 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
85 EVEX_LEN_0F38C7_R_6_P_2_W_1.
86 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
87 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
88 PREFIX_EVEX_0F38C6_REG_6 entries.
89 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
90 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
91 EVEX_W_0F38C7_R_6_P_2 entries.
92 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
93 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
94 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
95 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
96 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
97 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
98 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
100 2019-06-27 Jan Beulich <jbeulich@suse.com>
102 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
103 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
104 VEX_LEN_0F2D_P_3): Delete.
105 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
106 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
107 (prefix_table): ... here.
109 2019-06-27 Jan Beulich <jbeulich@suse.com>
111 * i386-dis.c (Iq): Delete.
113 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
115 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
116 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
117 (OP_E_memory): Also honor needindex when deciding whether an
118 address size prefix needs printing.
119 (OP_I): Remove handling of q_mode. Add handling of d_mode.
121 2019-06-26 Jim Wilson <jimw@sifive.com>
124 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
125 Set info->display_endian to info->endian_code.
127 2019-06-25 Jan Beulich <jbeulich@suse.com>
129 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
130 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
131 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
132 OPERAND_TYPE_ACC64 entries.
133 * i386-init.h: Re-generate.
135 2019-06-25 Jan Beulich <jbeulich@suse.com>
137 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
139 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
141 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
143 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
144 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
146 2019-06-25 Jan Beulich <jbeulich@suse.com>
148 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
151 2019-06-25 Jan Beulich <jbeulich@suse.com>
153 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
154 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
156 * i386-opc.tbl (movnti): Add IgnoreSize.
157 * i386-tbl.h: Re-generate.
159 2019-06-25 Jan Beulich <jbeulich@suse.com>
161 * i386-opc.tbl (and): Mark Imm8S form for optimization.
162 * i386-tbl.h: Re-generate.
164 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
166 * i386-dis-evex.h: Break into ...
167 * i386-dis-evex-len.h: New file.
168 * i386-dis-evex-mod.h: Likewise.
169 * i386-dis-evex-prefix.h: Likewise.
170 * i386-dis-evex-reg.h: Likewise.
171 * i386-dis-evex-w.h: Likewise.
172 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
173 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
176 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
179 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
180 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
182 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
183 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
184 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
185 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
186 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
187 EVEX_LEN_0F385B_P_2_W_1.
188 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
189 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
190 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
191 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
192 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
193 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
194 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
195 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
196 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
197 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
199 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
202 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
203 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
204 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
205 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
206 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
207 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
208 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
209 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
210 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
211 EVEX_LEN_0F3A43_P_2_W_1.
212 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
213 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
214 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
215 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
216 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
217 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
218 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
219 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
220 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
221 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
222 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
223 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
225 2019-06-14 Nick Clifton <nickc@redhat.com>
227 * po/fr.po; Updated French translation.
229 2019-06-13 Stafford Horne <shorne@gmail.com>
231 * or1k-asm.c: Regenerated.
232 * or1k-desc.c: Regenerated.
233 * or1k-desc.h: Regenerated.
234 * or1k-dis.c: Regenerated.
235 * or1k-ibld.c: Regenerated.
236 * or1k-opc.c: Regenerated.
237 * or1k-opc.h: Regenerated.
238 * or1k-opinst.c: Regenerated.
240 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
242 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
244 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
247 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
248 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
249 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
250 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
251 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
252 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
253 EVEX_LEN_0F3A1B_P_2_W_1.
254 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
255 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
256 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
257 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
258 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
259 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
260 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
261 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
263 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
266 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
267 EVEX.vvvv when disassembling VEX and EVEX instructions.
268 (OP_VEX): Set vex.register_specifier to 0 after readding
269 vex.register_specifier.
270 (OP_Vex_2src_1): Likewise.
271 (OP_Vex_2src_2): Likewise.
272 (OP_LWP_E): Likewise.
273 (OP_EX_Vex): Don't check vex.register_specifier.
274 (OP_XMM_Vex): Likewise.
276 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
277 Lili Cui <lili.cui@intel.com>
279 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
280 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
282 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
283 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
284 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
285 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
286 (i386_cpu_flags): Add cpuavx512_vp2intersect.
287 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
288 * i386-init.h: Regenerated.
289 * i386-tbl.h: Likewise.
291 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
292 Lili Cui <lili.cui@intel.com>
294 * doc/c-i386.texi: Document enqcmd.
295 * testsuite/gas/i386/enqcmd-intel.d: New file.
296 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
297 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
298 * testsuite/gas/i386/enqcmd.d: Likewise.
299 * testsuite/gas/i386/enqcmd.s: Likewise.
300 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
301 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
302 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
303 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
304 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
305 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
306 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
309 2019-06-04 Alan Hayward <alan.hayward@arm.com>
311 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
313 2019-06-03 Alan Modra <amodra@gmail.com>
315 * ppc-dis.c (prefix_opcd_indices): Correct size.
317 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
320 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
322 * i386-tbl.h: Regenerated.
324 2019-05-24 Alan Modra <amodra@gmail.com>
326 * po/POTFILES.in: Regenerate.
328 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
329 Alan Modra <amodra@gmail.com>
331 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
332 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
333 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
334 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
335 XTOP>): Define and add entries.
336 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
337 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
338 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
339 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
341 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
342 Alan Modra <amodra@gmail.com>
344 * ppc-dis.c (ppc_opts): Add "future" entry.
345 (PREFIX_OPCD_SEGS): Define.
346 (prefix_opcd_indices): New array.
347 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
348 (lookup_prefix): New function.
349 (print_insn_powerpc): Handle 64-bit prefix instructions.
350 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
351 (PMRR, POWERXX): Define.
352 (prefix_opcodes): New instruction table.
353 (prefix_num_opcodes): New constant.
355 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
357 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
358 * configure: Regenerated.
359 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
361 (HFILES): Add bpf-desc.h and bpf-opc.h.
362 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
363 bpf-ibld.c and bpf-opc.c.
365 * Makefile.in: Regenerated.
366 * disassemble.c (ARCH_bpf): Define.
367 (disassembler): Add case for bfd_arch_bpf.
368 (disassemble_init_for_target): Likewise.
369 (enum epbf_isa_attr): Define.
370 * disassemble.h: extern print_insn_bpf.
371 * bpf-asm.c: Generated.
372 * bpf-opc.h: Likewise.
373 * bpf-opc.c: Likewise.
374 * bpf-ibld.c: Likewise.
375 * bpf-dis.c: Likewise.
376 * bpf-desc.h: Likewise.
377 * bpf-desc.c: Likewise.
379 2019-05-21 Sudakshina Das <sudi.das@arm.com>
381 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
382 and VMSR with the new operands.
384 2019-05-21 Sudakshina Das <sudi.das@arm.com>
386 * arm-dis.c (enum mve_instructions): New enum
387 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
389 (mve_opcodes): New instructions as above.
390 (is_mve_encoding_conflict): Add cases for csinc, csinv,
392 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
394 2019-05-21 Sudakshina Das <sudi.das@arm.com>
396 * arm-dis.c (emun mve_instructions): Updated for new instructions.
397 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
398 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
399 uqshl, urshrl and urshr.
400 (is_mve_okay_in_it): Add new instructions to TRUE list.
401 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
402 (print_insn_mve): Updated to accept new %j,
403 %<bitfield>m and %<bitfield>n patterns.
405 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
407 * mips-opc.c (mips_builtin_opcodes): Change source register
410 2019-05-20 Nick Clifton <nickc@redhat.com>
412 * po/fr.po: Updated French translation.
414 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
415 Michael Collison <michael.collison@arm.com>
417 * arm-dis.c (thumb32_opcodes): Add new instructions.
418 (enum mve_instructions): Likewise.
419 (enum mve_undefined): Add new reasons.
420 (is_mve_encoding_conflict): Handle new instructions.
421 (is_mve_undefined): Likewise.
422 (is_mve_unpredictable): Likewise.
423 (print_mve_undefined): Likewise.
424 (print_mve_size): Likewise.
426 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
427 Michael Collison <michael.collison@arm.com>
429 * arm-dis.c (thumb32_opcodes): Add new instructions.
430 (enum mve_instructions): Likewise.
431 (is_mve_encoding_conflict): Handle new instructions.
432 (is_mve_undefined): Likewise.
433 (is_mve_unpredictable): Likewise.
434 (print_mve_size): Likewise.
436 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
437 Michael Collison <michael.collison@arm.com>
439 * arm-dis.c (thumb32_opcodes): Add new instructions.
440 (enum mve_instructions): Likewise.
441 (is_mve_encoding_conflict): Likewise.
442 (is_mve_unpredictable): Likewise.
443 (print_mve_size): Likewise.
445 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
446 Michael Collison <michael.collison@arm.com>
448 * arm-dis.c (thumb32_opcodes): Add new instructions.
449 (enum mve_instructions): Likewise.
450 (is_mve_encoding_conflict): Handle new instructions.
451 (is_mve_undefined): Likewise.
452 (is_mve_unpredictable): Likewise.
453 (print_mve_size): Likewise.
455 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
456 Michael Collison <michael.collison@arm.com>
458 * arm-dis.c (thumb32_opcodes): Add new instructions.
459 (enum mve_instructions): Likewise.
460 (is_mve_encoding_conflict): Handle new instructions.
461 (is_mve_undefined): Likewise.
462 (is_mve_unpredictable): Likewise.
463 (print_mve_size): Likewise.
464 (print_insn_mve): Likewise.
466 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
467 Michael Collison <michael.collison@arm.com>
469 * arm-dis.c (thumb32_opcodes): Add new instructions.
470 (print_insn_thumb32): Handle new instructions.
472 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
473 Michael Collison <michael.collison@arm.com>
475 * arm-dis.c (enum mve_instructions): Add new instructions.
476 (enum mve_undefined): Add new reasons.
477 (is_mve_encoding_conflict): Handle new instructions.
478 (is_mve_undefined): Likewise.
479 (is_mve_unpredictable): Likewise.
480 (print_mve_undefined): Likewise.
481 (print_mve_size): Likewise.
482 (print_mve_shift_n): Likewise.
483 (print_insn_mve): Likewise.
485 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
486 Michael Collison <michael.collison@arm.com>
488 * arm-dis.c (enum mve_instructions): Add new instructions.
489 (is_mve_encoding_conflict): Handle new instructions.
490 (is_mve_unpredictable): Likewise.
491 (print_mve_rotate): Likewise.
492 (print_mve_size): Likewise.
493 (print_insn_mve): Likewise.
495 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
496 Michael Collison <michael.collison@arm.com>
498 * arm-dis.c (enum mve_instructions): Add new instructions.
499 (is_mve_encoding_conflict): Handle new instructions.
500 (is_mve_unpredictable): Likewise.
501 (print_mve_size): Likewise.
502 (print_insn_mve): Likewise.
504 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
505 Michael Collison <michael.collison@arm.com>
507 * arm-dis.c (enum mve_instructions): Add new instructions.
508 (enum mve_undefined): Add new reasons.
509 (is_mve_encoding_conflict): Handle new instructions.
510 (is_mve_undefined): Likewise.
511 (is_mve_unpredictable): Likewise.
512 (print_mve_undefined): Likewise.
513 (print_mve_size): Likewise.
514 (print_insn_mve): Likewise.
516 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
517 Michael Collison <michael.collison@arm.com>
519 * arm-dis.c (enum mve_instructions): Add new instructions.
520 (is_mve_encoding_conflict): Handle new instructions.
521 (is_mve_undefined): Likewise.
522 (is_mve_unpredictable): Likewise.
523 (print_mve_size): Likewise.
524 (print_insn_mve): Likewise.
526 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
527 Michael Collison <michael.collison@arm.com>
529 * arm-dis.c (enum mve_instructions): Add new instructions.
530 (enum mve_unpredictable): Add new reasons.
531 (enum mve_undefined): Likewise.
532 (is_mve_okay_in_it): Handle new isntructions.
533 (is_mve_encoding_conflict): Likewise.
534 (is_mve_undefined): Likewise.
535 (is_mve_unpredictable): Likewise.
536 (print_mve_vmov_index): Likewise.
537 (print_simd_imm8): Likewise.
538 (print_mve_undefined): Likewise.
539 (print_mve_unpredictable): Likewise.
540 (print_mve_size): Likewise.
541 (print_insn_mve): Likewise.
543 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
544 Michael Collison <michael.collison@arm.com>
546 * arm-dis.c (enum mve_instructions): Add new instructions.
547 (enum mve_unpredictable): Add new reasons.
548 (enum mve_undefined): Likewise.
549 (is_mve_encoding_conflict): Handle new instructions.
550 (is_mve_undefined): Likewise.
551 (is_mve_unpredictable): Likewise.
552 (print_mve_undefined): Likewise.
553 (print_mve_unpredictable): Likewise.
554 (print_mve_rounding_mode): Likewise.
555 (print_mve_vcvt_size): Likewise.
556 (print_mve_size): Likewise.
557 (print_insn_mve): Likewise.
559 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
560 Michael Collison <michael.collison@arm.com>
562 * arm-dis.c (enum mve_instructions): Add new instructions.
563 (enum mve_unpredictable): Add new reasons.
564 (enum mve_undefined): Likewise.
565 (is_mve_undefined): Handle new instructions.
566 (is_mve_unpredictable): Likewise.
567 (print_mve_undefined): Likewise.
568 (print_mve_unpredictable): Likewise.
569 (print_mve_size): Likewise.
570 (print_insn_mve): Likewise.
572 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
573 Michael Collison <michael.collison@arm.com>
575 * arm-dis.c (enum mve_instructions): Add new instructions.
576 (enum mve_undefined): Add new reasons.
577 (insns): Add new instructions.
578 (is_mve_encoding_conflict):
579 (print_mve_vld_str_addr): New print function.
580 (is_mve_undefined): Handle new instructions.
581 (is_mve_unpredictable): Likewise.
582 (print_mve_undefined): Likewise.
583 (print_mve_size): Likewise.
584 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
585 (print_insn_mve): Handle new operands.
587 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
588 Michael Collison <michael.collison@arm.com>
590 * arm-dis.c (enum mve_instructions): Add new instructions.
591 (enum mve_unpredictable): Add new reasons.
592 (is_mve_encoding_conflict): Handle new instructions.
593 (is_mve_unpredictable): Likewise.
594 (mve_opcodes): Add new instructions.
595 (print_mve_unpredictable): Handle new reasons.
596 (print_mve_register_blocks): New print function.
597 (print_mve_size): Handle new instructions.
598 (print_insn_mve): Likewise.
600 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
601 Michael Collison <michael.collison@arm.com>
603 * arm-dis.c (enum mve_instructions): Add new instructions.
604 (enum mve_unpredictable): Add new reasons.
605 (enum mve_undefined): Likewise.
606 (is_mve_encoding_conflict): Handle new instructions.
607 (is_mve_undefined): Likewise.
608 (is_mve_unpredictable): Likewise.
609 (coprocessor_opcodes): Move NEON VDUP from here...
610 (neon_opcodes): ... to here.
611 (mve_opcodes): Add new instructions.
612 (print_mve_undefined): Handle new reasons.
613 (print_mve_unpredictable): Likewise.
614 (print_mve_size): Handle new instructions.
615 (print_insn_neon): Handle vdup.
616 (print_insn_mve): Handle new operands.
618 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
619 Michael Collison <michael.collison@arm.com>
621 * arm-dis.c (enum mve_instructions): Add new instructions.
622 (enum mve_unpredictable): Add new values.
623 (mve_opcodes): Add new instructions.
624 (vec_condnames): New array with vector conditions.
625 (mve_predicatenames): New array with predicate suffixes.
626 (mve_vec_sizename): New array with vector sizes.
627 (enum vpt_pred_state): New enum with vector predication states.
628 (struct vpt_block): New struct type for vpt blocks.
629 (vpt_block_state): Global struct to keep track of state.
630 (mve_extract_pred_mask): New helper function.
631 (num_instructions_vpt_block): Likewise.
632 (mark_outside_vpt_block): Likewise.
633 (mark_inside_vpt_block): Likewise.
634 (invert_next_predicate_state): Likewise.
635 (update_next_predicate_state): Likewise.
636 (update_vpt_block_state): Likewise.
637 (is_vpt_instruction): Likewise.
638 (is_mve_encoding_conflict): Add entries for new instructions.
639 (is_mve_unpredictable): Likewise.
640 (print_mve_unpredictable): Handle new cases.
641 (print_instruction_predicate): Likewise.
642 (print_mve_size): New function.
643 (print_vec_condition): New function.
644 (print_insn_mve): Handle vpt blocks and new print operands.
646 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
648 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
649 8, 14 and 15 for Armv8.1-M Mainline.
651 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
652 Michael Collison <michael.collison@arm.com>
654 * arm-dis.c (enum mve_instructions): New enum.
655 (enum mve_unpredictable): Likewise.
656 (enum mve_undefined): Likewise.
657 (struct mopcode32): New struct.
658 (is_mve_okay_in_it): New function.
659 (is_mve_architecture): Likewise.
660 (arm_decode_field): Likewise.
661 (arm_decode_field_multiple): Likewise.
662 (is_mve_encoding_conflict): Likewise.
663 (is_mve_undefined): Likewise.
664 (is_mve_unpredictable): Likewise.
665 (print_mve_undefined): Likewise.
666 (print_mve_unpredictable): Likewise.
667 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
668 (print_insn_mve): New function.
669 (print_insn_thumb32): Handle MVE architecture.
670 (select_arm_features): Force thumb for Armv8.1-m Mainline.
672 2019-05-10 Nick Clifton <nickc@redhat.com>
675 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
676 end of the table prematurely.
678 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
680 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
683 2019-05-11 Alan Modra <amodra@gmail.com>
685 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
686 when -Mraw is in effect.
688 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
690 * aarch64-dis-2.c: Regenerate.
691 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
692 (OP_SVE_BBB): New variant set.
693 (OP_SVE_DDDD): New variant set.
694 (OP_SVE_HHH): New variant set.
695 (OP_SVE_HHHU): New variant set.
696 (OP_SVE_SSS): New variant set.
697 (OP_SVE_SSSU): New variant set.
698 (OP_SVE_SHH): New variant set.
699 (OP_SVE_SBBU): New variant set.
700 (OP_SVE_DSS): New variant set.
701 (OP_SVE_DHHU): New variant set.
702 (OP_SVE_VMV_HSD_BHS): New variant set.
703 (OP_SVE_VVU_HSD_BHS): New variant set.
704 (OP_SVE_VVVU_SD_BH): New variant set.
705 (OP_SVE_VVVU_BHSD): New variant set.
706 (OP_SVE_VVV_QHD_DBS): New variant set.
707 (OP_SVE_VVV_HSD_BHS): New variant set.
708 (OP_SVE_VVV_HSD_BHS2): New variant set.
709 (OP_SVE_VVV_BHS_HSD): New variant set.
710 (OP_SVE_VV_BHS_HSD): New variant set.
711 (OP_SVE_VVV_SD): New variant set.
712 (OP_SVE_VVU_BHS_HSD): New variant set.
713 (OP_SVE_VZVV_SD): New variant set.
714 (OP_SVE_VZVV_BH): New variant set.
715 (OP_SVE_VZV_SD): New variant set.
716 (aarch64_opcode_table): Add sve2 instructions.
718 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
720 * aarch64-asm-2.c: Regenerated.
721 * aarch64-dis-2.c: Regenerated.
722 * aarch64-opc-2.c: Regenerated.
723 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
724 for SVE_SHLIMM_UNPRED_22.
725 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
726 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
729 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
731 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
732 sve_size_tsz_bhs iclass encode.
733 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
734 sve_size_tsz_bhs iclass decode.
736 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
738 * aarch64-asm-2.c: Regenerated.
739 * aarch64-dis-2.c: Regenerated.
740 * aarch64-opc-2.c: Regenerated.
741 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
742 for SVE_Zm4_11_INDEX.
743 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
744 (fields): Handle SVE_i2h field.
745 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
746 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
748 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
750 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
751 sve_shift_tsz_bhsd iclass encode.
752 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
753 sve_shift_tsz_bhsd iclass decode.
755 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
757 * aarch64-asm-2.c: Regenerated.
758 * aarch64-dis-2.c: Regenerated.
759 * aarch64-opc-2.c: Regenerated.
760 * aarch64-asm.c (aarch64_ins_sve_shrimm):
761 (aarch64_encode_variant_using_iclass): Handle
762 sve_shift_tsz_hsd iclass encode.
763 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
764 sve_shift_tsz_hsd iclass decode.
765 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
766 for SVE_SHRIMM_UNPRED_22.
767 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
768 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
771 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
773 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
774 sve_size_013 iclass encode.
775 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
776 sve_size_013 iclass decode.
778 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
780 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
781 sve_size_bh iclass encode.
782 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
783 sve_size_bh iclass decode.
785 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
787 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
788 sve_size_sd2 iclass encode.
789 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
790 sve_size_sd2 iclass decode.
791 * aarch64-opc.c (fields): Handle SVE_sz2 field.
792 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
794 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
796 * aarch64-asm-2.c: Regenerated.
797 * aarch64-dis-2.c: Regenerated.
798 * aarch64-opc-2.c: Regenerated.
799 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
801 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
802 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
804 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
806 * aarch64-asm-2.c: Regenerated.
807 * aarch64-dis-2.c: Regenerated.
808 * aarch64-opc-2.c: Regenerated.
809 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
810 for SVE_Zm3_11_INDEX.
811 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
812 (fields): Handle SVE_i3l and SVE_i3h2 fields.
813 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
815 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
817 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
819 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
820 sve_size_hsd2 iclass encode.
821 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
822 sve_size_hsd2 iclass decode.
823 * aarch64-opc.c (fields): Handle SVE_size field.
824 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
826 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
828 * aarch64-asm-2.c: Regenerated.
829 * aarch64-dis-2.c: Regenerated.
830 * aarch64-opc-2.c: Regenerated.
831 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
833 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
834 (fields): Handle SVE_rot3 field.
835 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
836 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
838 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
840 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
843 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
846 (aarch64_feature_sve2, aarch64_feature_sve2aes,
847 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
848 aarch64_feature_sve2bitperm): New feature sets.
849 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
850 for feature set addresses.
851 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
852 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
854 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
855 Faraz Shahbazker <fshahbazker@wavecomp.com>
857 * mips-dis.c (mips_calculate_combination_ases): Add ISA
858 argument and set ASE_EVA_R6 appropriately.
859 (set_default_mips_dis_options): Pass ISA to above.
860 (parse_mips_dis_option): Likewise.
861 * mips-opc.c (EVAR6): New macro.
862 (mips_builtin_opcodes): Add llwpe, scwpe.
864 2019-05-01 Sudakshina Das <sudi.das@arm.com>
866 * aarch64-asm-2.c: Regenerated.
867 * aarch64-dis-2.c: Regenerated.
868 * aarch64-opc-2.c: Regenerated.
869 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
870 AARCH64_OPND_TME_UIMM16.
871 (aarch64_print_operand): Likewise.
872 * aarch64-tbl.h (QL_IMM_NIL): New.
875 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
877 2019-04-29 John Darrington <john@darrington.wattle.id.au>
879 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
881 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
882 Faraz Shahbazker <fshahbazker@wavecomp.com>
884 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
886 2019-04-24 John Darrington <john@darrington.wattle.id.au>
888 * s12z-opc.h: Add extern "C" bracketing to help
889 users who wish to use this interface in c++ code.
891 2019-04-24 John Darrington <john@darrington.wattle.id.au>
893 * s12z-opc.c (bm_decode): Handle bit map operations with the
896 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
898 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
899 specifier. Add entries for VLDR and VSTR of system registers.
900 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
901 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
902 of %J and %K format specifier.
904 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
906 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
907 Add new entries for VSCCLRM instruction.
908 (print_insn_coprocessor): Handle new %C format control code.
910 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
912 * arm-dis.c (enum isa): New enum.
913 (struct sopcode32): New structure.
914 (coprocessor_opcodes): change type of entries to struct sopcode32 and
915 set isa field of all current entries to ANY.
916 (print_insn_coprocessor): Change type of insn to struct sopcode32.
917 Only match an entry if its isa field allows the current mode.
919 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
921 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
923 (print_insn_thumb32): Add logic to print %n CLRM register list.
925 2019-04-15 Sudakshina Das <sudi.das@arm.com>
927 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
930 2019-04-15 Sudakshina Das <sudi.das@arm.com>
932 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
933 (print_insn_thumb32): Edit the switch case for %Z.
935 2019-04-15 Sudakshina Das <sudi.das@arm.com>
937 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
939 2019-04-15 Sudakshina Das <sudi.das@arm.com>
941 * arm-dis.c (thumb32_opcodes): New instruction bfl.
943 2019-04-15 Sudakshina Das <sudi.das@arm.com>
945 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
947 2019-04-15 Sudakshina Das <sudi.das@arm.com>
949 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
950 Arm register with r13 and r15 unpredictable.
951 (thumb32_opcodes): New instructions for bfx and bflx.
953 2019-04-15 Sudakshina Das <sudi.das@arm.com>
955 * arm-dis.c (thumb32_opcodes): New instructions for bf.
957 2019-04-15 Sudakshina Das <sudi.das@arm.com>
959 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
961 2019-04-15 Sudakshina Das <sudi.das@arm.com>
963 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
965 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
967 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
969 2019-04-12 John Darrington <john@darrington.wattle.id.au>
971 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
972 "optr". ("operator" is a reserved word in c++).
974 2019-04-11 Sudakshina Das <sudi.das@arm.com>
976 * aarch64-opc.c (aarch64_print_operand): Add case for
978 (verify_constraints): Likewise.
979 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
980 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
981 to accept Rt|SP as first operand.
982 (AARCH64_OPERANDS): Add new Rt_SP.
983 * aarch64-asm-2.c: Regenerated.
984 * aarch64-dis-2.c: Regenerated.
985 * aarch64-opc-2.c: Regenerated.
987 2019-04-11 Sudakshina Das <sudi.das@arm.com>
989 * aarch64-asm-2.c: Regenerated.
990 * aarch64-dis-2.c: Likewise.
991 * aarch64-opc-2.c: Likewise.
992 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
994 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
996 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
998 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1000 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1001 * i386-init.h: Regenerated.
1003 2019-04-07 Alan Modra <amodra@gmail.com>
1005 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1006 op_separator to control printing of spaces, comma and parens
1007 rather than need_comma, need_paren and spaces vars.
1009 2019-04-07 Alan Modra <amodra@gmail.com>
1012 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1013 (print_insn_neon, print_insn_arm): Likewise.
1015 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1017 * i386-dis-evex.h (evex_table): Updated to support BF16
1019 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1020 and EVEX_W_0F3872_P_3.
1021 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1022 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1023 * i386-opc.h (enum): Add CpuAVX512_BF16.
1024 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1025 * i386-opc.tbl: Add AVX512 BF16 instructions.
1026 * i386-init.h: Regenerated.
1027 * i386-tbl.h: Likewise.
1029 2019-04-05 Alan Modra <amodra@gmail.com>
1031 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1032 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1033 to favour printing of "-" branch hint when using the "y" bit.
1034 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1036 2019-04-05 Alan Modra <amodra@gmail.com>
1038 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1039 opcode until first operand is output.
1041 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1044 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1045 (valid_bo_post_v2): Add support for 'at' branch hints.
1046 (insert_bo): Only error on branch on ctr.
1047 (get_bo_hint_mask): New function.
1048 (insert_boe): Add new 'branch_taken' formal argument. Add support
1049 for inserting 'at' branch hints.
1050 (extract_boe): Add new 'branch_taken' formal argument. Add support
1051 for extracting 'at' branch hints.
1052 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1053 (BOE): Delete operand.
1054 (BOM, BOP): New operands.
1056 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1057 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1058 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1059 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1060 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1061 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1062 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1063 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1064 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1065 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1066 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1067 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1068 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1069 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1070 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1071 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1072 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1073 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1074 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1075 bttarl+>: New extended mnemonics.
1077 2019-03-28 Alan Modra <amodra@gmail.com>
1080 * ppc-opc.c (BTF): Define.
1081 (powerpc_opcodes): Use for mtfsb*.
1082 * ppc-dis.c (print_insn_powerpc): Print fields with both
1083 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1085 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1087 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1088 (mapping_symbol_for_insn): Implement new algorithm.
1089 (print_insn): Remove duplicate code.
1091 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1093 * aarch64-dis.c (print_insn_aarch64):
1096 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1098 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1101 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1103 * aarch64-dis.c (last_stop_offset): New.
1104 (print_insn_aarch64): Use stop_offset.
1106 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1109 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1111 * i386-init.h: Regenerated.
1113 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1116 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1117 vmovdqu16, vmovdqu32 and vmovdqu64.
1118 * i386-tbl.h: Regenerated.
1120 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1122 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1123 from vstrszb, vstrszh, and vstrszf.
1125 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1127 * s390-opc.txt: Add instruction descriptions.
1129 2019-02-08 Jim Wilson <jimw@sifive.com>
1131 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1134 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1136 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1138 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1141 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1142 * aarch64-opc.c (verify_elem_sd): New.
1143 (fields): Add FLD_sz entr.
1144 * aarch64-tbl.h (_SIMD_INSN): New.
1145 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1146 fmulx scalar and vector by element isns.
1148 2019-02-07 Nick Clifton <nickc@redhat.com>
1150 * po/sv.po: Updated Swedish translation.
1152 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1154 * s390-mkopc.c (main): Accept arch13 as cpu string.
1155 * s390-opc.c: Add new instruction formats and instruction opcode
1157 * s390-opc.txt: Add new arch13 instructions.
1159 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1161 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1162 (aarch64_opcode): Change encoding for stg, stzg
1164 * aarch64-asm-2.c: Regenerated.
1165 * aarch64-dis-2.c: Regenerated.
1166 * aarch64-opc-2.c: Regenerated.
1168 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1170 * aarch64-asm-2.c: Regenerated.
1171 * aarch64-dis-2.c: Likewise.
1172 * aarch64-opc-2.c: Likewise.
1173 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1175 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1176 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1178 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1179 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1180 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1181 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1182 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1183 case for ldstgv_indexed.
1184 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1185 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1186 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1187 * aarch64-asm-2.c: Regenerated.
1188 * aarch64-dis-2.c: Regenerated.
1189 * aarch64-opc-2.c: Regenerated.
1191 2019-01-23 Nick Clifton <nickc@redhat.com>
1193 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1195 2019-01-21 Nick Clifton <nickc@redhat.com>
1197 * po/de.po: Updated German translation.
1198 * po/uk.po: Updated Ukranian translation.
1200 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1201 * mips-dis.c (mips_arch_choices): Fix typo in
1202 gs464, gs464e and gs264e descriptors.
1204 2019-01-19 Nick Clifton <nickc@redhat.com>
1206 * configure: Regenerate.
1207 * po/opcodes.pot: Regenerate.
1209 2018-06-24 Nick Clifton <nickc@redhat.com>
1211 2.32 branch created.
1213 2019-01-09 John Darrington <john@darrington.wattle.id.au>
1215 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1217 -dis.c (opr_emit_disassembly): Do not omit an index if it is
1220 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1222 * configure: Regenerate.
1224 2019-01-07 Alan Modra <amodra@gmail.com>
1226 * configure: Regenerate.
1227 * po/POTFILES.in: Regenerate.
1229 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1231 * s12z-opc.c: New file.
1232 * s12z-opc.h: New file.
1233 * s12z-dis.c: Removed all code not directly related to display
1234 of instructions. Used the interface provided by the new files
1236 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1237 * Makefile.in: Regenerate.
1238 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1239 * configure: Regenerate.
1241 2019-01-01 Alan Modra <amodra@gmail.com>
1243 Update year range in copyright notice of all files.
1245 For older changes see ChangeLog-2018
1247 Copyright (C) 2019 Free Software Foundation, Inc.
1249 Copying and distribution of this file, with or without modification,
1250 are permitted in any medium without royalty provided the copyright
1251 notice and this notice are preserved.
1257 version-control: never