opcodes/ChangeLog

   1 2019-07-16  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-gen.c (operand_type_init, operand_types): Replace SReg
   4         entries.
   5         * i386-opc.h (SReg2, SReg3): Replace by ...
   6         (SReg): ... this.
   7         (union i386_operand_type): Replace sreg fields.
   8         * i386-opc.tbl (mov, ): Use SReg.
   9         (push, pop): Likewies. Drop i386 and x86-64 specific segment
  10         register flavors.
  11         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
  12         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
  13
  14 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
  15
  16         * bpf-desc.c: Regenerate.
  17         * bpf-opc.c: Likewise.
  18         * bpf-opc.h: Likewise.
  19
  20 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
  21
  22         * bpf-desc.c: Regenerate.
  23         * bpf-opc.c: Likewise.
  24
  25 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
  26
  27         * arm-dis.c (print_insn_coprocessor): Rename index to
  28         index_operand.
  29
  30 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
  31
  32         * riscv-opc.c (riscv_insn_types): Add r4 type.
  33
  34         * riscv-opc.c (riscv_insn_types): Add b and j type.
  35
  36         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
  37         format for sb type and correct s type.
  38
  39 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
  40
  41         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
  42         SVE FMOV alias of FCPY.
  43
  44 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
  45
  46         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
  47         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
  48
  49 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
  50
  51         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
  52         registers in an instruction prefixed by MOVPRFX.
  53
  54 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
  55
  56         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
  57         sve_size_13 icode to account for variant behaviour of
  58         pmull{t,b}.
  59         * aarch64-dis-2.c: Regenerate.
  60         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
  61         sve_size_13 icode to account for variant behaviour of
  62         pmull{t,b}.
  63         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
  64         (OP_SVE_VVV_Q_D): Add new qualifier.
  65         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
  66         (struct aarch64_opcode): Split pmull{t,b} into those requiring
  67         AES and those not.
  68
  69 2019-07-01  Jan Beulich  <jbeulich@suse.com>
  70
  71         * opcodes/i386-gen.c (operand_type_init): Remove
  72         OPERAND_TYPE_VEC_IMM4 entry.
  73         (operand_types): Remove Vec_Imm4.
  74         * opcodes/i386-opc.h (Vec_Imm4): Delete.
  75         (union i386_operand_type): Remove vec_imm4.
  76         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
  77         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
  78
  79 2019-07-01  Jan Beulich  <jbeulich@suse.com>
  80
  81         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
  82         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
  83         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
  84         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
  85         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
  86         monitorx, mwaitx): Drop ImmExt from operand-less forms.
  87         * i386-tbl.h: Re-generate.
  88
  89 2019-07-01  Jan Beulich  <jbeulich@suse.com>
  90
  91         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
  92         register operands.
  93         * i386-tbl.h: Re-generate.
  94
  95 2019-07-01  Jan Beulich  <jbeulich@suse.com>
  96
  97         * i386-opc.tbl (C): New.
  98         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
  99         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 100         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 101         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 102         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 103         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 104         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 105         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 106         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 107         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 108         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 109         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 110         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 111         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 112         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 113         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 114         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 115         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 116         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 117         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 118         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 119         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 120         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 121         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 122         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 123         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 124         flavors.
 125         * i386-tbl.h: Re-generate.
 126
 127 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 128
 129         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 130         register operands.
 131         * i386-tbl.h: Re-generate.
 132
 133 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 134
 135         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 136         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 137         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 138         * i386-tbl.h: Re-generate.
 139
 140 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 141
 142         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 143         Disp8MemShift from register only templates.
 144         * i386-tbl.h: Re-generate.
 145
 146 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 147
 148         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 149         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 150         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 151         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 152         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 153         EVEX_W_0F11_P_3_M_1): Delete.
 154         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 155         EVEX_W_0F11_P_3): New.
 156         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 157         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 158         MOD_EVEX_0F11_PREFIX_3 table entries.
 159         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 160         PREFIX_EVEX_0F11 table entries.
 161         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 162         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 163         EVEX_W_0F11_P_3_M_{0,1} table entries.
 164
 165 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 166
 167         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 168         Delete.
 169
 170 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 171
 172         PR binutils/24719
 173         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 174         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 175         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 176         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 177         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 178         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 179         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 180         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 181         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 182         PREFIX_EVEX_0F38C6_REG_6 entries.
 183         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 184         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 185         EVEX_W_0F38C7_R_6_P_2 entries.
 186         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 187         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 188         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 189         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 190         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 191         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 192         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 193
 194 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 195
 196         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 197         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 198         VEX_LEN_0F2D_P_3): Delete.
 199         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 200         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 201         (prefix_table): ... here.
 202
 203 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 204
 205         * i386-dis.c (Iq): Delete.
 206         (Id): New.
 207         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 208         TBM insns.
 209         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 210         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 211         (OP_E_memory): Also honor needindex when deciding whether an
 212         address size prefix needs printing.
 213         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 214
 215 2019-06-26  Jim Wilson  <jimw@sifive.com>
 216
 217         PR binutils/24739
 218         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 219         Set info->display_endian to info->endian_code.
 220
 221 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 222
 223         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 224         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 225         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 226         OPERAND_TYPE_ACC64 entries.
 227         * i386-init.h: Re-generate.
 228
 229 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 230
 231         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 232         Delete.
 233         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 234         of dqa_mode.
 235         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 236         entries here.
 237         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 238         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 239
 240 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 241
 242         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 243         variables.
 244
 245 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 246
 247         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 248         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 249         movnti.
 250         * i386-opc.tbl (movnti): Add IgnoreSize.
 251         * i386-tbl.h: Re-generate.
 252
 253 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 254
 255         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 256         * i386-tbl.h: Re-generate.
 257
 258 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 259
 260         * i386-dis-evex.h: Break into ...
 261         * i386-dis-evex-len.h: New file.
 262         * i386-dis-evex-mod.h: Likewise.
 263         * i386-dis-evex-prefix.h: Likewise.
 264         * i386-dis-evex-reg.h: Likewise.
 265         * i386-dis-evex-w.h: Likewise.
 266         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 267         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 268         i386-dis-evex-mod.h.
 269
 270 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 271
 272         PR binutils/24700
 273         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 274         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 275         EVEX_W_0F385B_P_2.
 276         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 277         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 278         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 279         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 280         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 281         EVEX_LEN_0F385B_P_2_W_1.
 282         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 283         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 284         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 285         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 286         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 287         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 288         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 289         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 290         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 291         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 292
 293 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 294
 295         PR binutils/24691
 296         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 297         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 298         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 299         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 300         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 301         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 302         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 303         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 304         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 305         EVEX_LEN_0F3A43_P_2_W_1.
 306         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 307         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 308         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 309         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 310         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 311         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 312         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 313         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 314         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 315         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 316         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 317         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 318
 319 2019-06-14  Nick Clifton  <nickc@redhat.com>
 320
 321         * po/fr.po; Updated French translation.
 322
 323 2019-06-13  Stafford Horne  <shorne@gmail.com>
 324
 325         * or1k-asm.c: Regenerated.
 326         * or1k-desc.c: Regenerated.
 327         * or1k-desc.h: Regenerated.
 328         * or1k-dis.c: Regenerated.
 329         * or1k-ibld.c: Regenerated.
 330         * or1k-opc.c: Regenerated.
 331         * or1k-opc.h: Regenerated.
 332         * or1k-opinst.c: Regenerated.
 333
 334 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 335
 336         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 337
 338 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 339
 340         PR binutils/24633
 341         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 342         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 343         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 344         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 345         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 346         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 347         EVEX_LEN_0F3A1B_P_2_W_1.
 348         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 349         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 350         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 351         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 352         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 353         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 354         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 355         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 356
 357 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 358
 359         PR binutils/24626
 360         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 361         EVEX.vvvv when disassembling VEX and EVEX instructions.
 362         (OP_VEX): Set vex.register_specifier to 0 after readding
 363         vex.register_specifier.
 364         (OP_Vex_2src_1): Likewise.
 365         (OP_Vex_2src_2): Likewise.
 366         (OP_LWP_E): Likewise.
 367         (OP_EX_Vex): Don't check vex.register_specifier.
 368         (OP_XMM_Vex): Likewise.
 369
 370 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 371             Lili Cui  <lili.cui@intel.com>
 372
 373         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 374         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 375         instructions.
 376         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 377         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 378         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 379         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 380         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 381         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 382         * i386-init.h: Regenerated.
 383         * i386-tbl.h: Likewise.
 384
 385 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 386             Lili Cui  <lili.cui@intel.com>
 387
 388         * doc/c-i386.texi: Document enqcmd.
 389         * testsuite/gas/i386/enqcmd-intel.d: New file.
 390         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 391         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 392         * testsuite/gas/i386/enqcmd.d: Likewise.
 393         * testsuite/gas/i386/enqcmd.s: Likewise.
 394         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 395         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 396         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 397         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 398         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 399         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 400         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 401         and x86-64-enqcmd.
 402
 403 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 404
 405         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 406
 407 2019-06-03  Alan Modra  <amodra@gmail.com>
 408
 409         * ppc-dis.c (prefix_opcd_indices): Correct size.
 410
 411 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 412
 413         PR gas/24625
 414         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 415         Disp8ShiftVL.
 416         * i386-tbl.h: Regenerated.
 417
 418 2019-05-24  Alan Modra  <amodra@gmail.com>
 419
 420         * po/POTFILES.in: Regenerate.
 421
 422 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 423             Alan Modra  <amodra@gmail.com>
 424
 425         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 426         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 427         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 428         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 429         XTOP>): Define and add entries.
 430         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 431         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 432         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 433         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 434
 435 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 436             Alan Modra  <amodra@gmail.com>
 437
 438         * ppc-dis.c (ppc_opts): Add "future" entry.
 439         (PREFIX_OPCD_SEGS): Define.
 440         (prefix_opcd_indices): New array.
 441         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 442         (lookup_prefix): New function.
 443         (print_insn_powerpc): Handle 64-bit prefix instructions.
 444         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 445         (PMRR, POWERXX): Define.
 446         (prefix_opcodes): New instruction table.
 447         (prefix_num_opcodes): New constant.
 448
 449 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 450
 451         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 452         * configure: Regenerated.
 453         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 454         and cpu/bpf.opc.
 455         (HFILES): Add bpf-desc.h and bpf-opc.h.
 456         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 457         bpf-ibld.c and bpf-opc.c.
 458         (BPF_DEPS): Define.
 459         * Makefile.in: Regenerated.
 460         * disassemble.c (ARCH_bpf): Define.
 461         (disassembler): Add case for bfd_arch_bpf.
 462         (disassemble_init_for_target): Likewise.
 463         (enum epbf_isa_attr): Define.
 464         * disassemble.h: extern print_insn_bpf.
 465         * bpf-asm.c: Generated.
 466         * bpf-opc.h: Likewise.
 467         * bpf-opc.c: Likewise.
 468         * bpf-ibld.c: Likewise.
 469         * bpf-dis.c: Likewise.
 470         * bpf-desc.h: Likewise.
 471         * bpf-desc.c: Likewise.
 472
 473 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 474
 475         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 476         and VMSR with the new operands.
 477
 478 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 479
 480         * arm-dis.c (enum mve_instructions): New enum
 481         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 482         and cneg.
 483         (mve_opcodes): New instructions as above.
 484         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 485         csneg and csel.
 486         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 487
 488 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 489
 490         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 491         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 492         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 493         uqshl, urshrl and urshr.
 494         (is_mve_okay_in_it): Add new instructions to TRUE list.
 495         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 496         (print_insn_mve): Updated to accept new %j,
 497         %<bitfield>m and %<bitfield>n patterns.
 498
 499 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 500
 501         * mips-opc.c (mips_builtin_opcodes): Change source register
 502         constraint for DAUI.
 503
 504 2019-05-20  Nick Clifton  <nickc@redhat.com>
 505
 506         * po/fr.po: Updated French translation.
 507
 508 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 509             Michael Collison <michael.collison@arm.com>
 510
 511         * arm-dis.c (thumb32_opcodes): Add new instructions.
 512         (enum mve_instructions): Likewise.
 513         (enum mve_undefined): Add new reasons.
 514         (is_mve_encoding_conflict): Handle new instructions.
 515         (is_mve_undefined): Likewise.
 516         (is_mve_unpredictable): Likewise.
 517         (print_mve_undefined): Likewise.
 518         (print_mve_size): Likewise.
 519
 520 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 521             Michael Collison <michael.collison@arm.com>
 522
 523         * arm-dis.c (thumb32_opcodes): Add new instructions.
 524         (enum mve_instructions): Likewise.
 525         (is_mve_encoding_conflict): Handle new instructions.
 526         (is_mve_undefined): Likewise.
 527         (is_mve_unpredictable): Likewise.
 528         (print_mve_size): Likewise.
 529
 530 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 531             Michael Collison <michael.collison@arm.com>
 532
 533         * arm-dis.c (thumb32_opcodes): Add new instructions.
 534         (enum mve_instructions): Likewise.
 535         (is_mve_encoding_conflict): Likewise.
 536         (is_mve_unpredictable): Likewise.
 537         (print_mve_size): Likewise.
 538
 539 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 540             Michael Collison <michael.collison@arm.com>
 541
 542         * arm-dis.c (thumb32_opcodes): Add new instructions.
 543         (enum mve_instructions): Likewise.
 544         (is_mve_encoding_conflict): Handle new instructions.
 545         (is_mve_undefined): Likewise.
 546         (is_mve_unpredictable): Likewise.
 547         (print_mve_size): Likewise.
 548
 549 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 550             Michael Collison <michael.collison@arm.com>
 551
 552         * arm-dis.c (thumb32_opcodes): Add new instructions.
 553         (enum mve_instructions): Likewise.
 554         (is_mve_encoding_conflict): Handle new instructions.
 555         (is_mve_undefined): Likewise.
 556         (is_mve_unpredictable): Likewise.
 557         (print_mve_size): Likewise.
 558         (print_insn_mve): Likewise.
 559
 560 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 561             Michael Collison <michael.collison@arm.com>
 562
 563         * arm-dis.c (thumb32_opcodes): Add new instructions.
 564         (print_insn_thumb32): Handle new instructions.
 565
 566 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 567             Michael Collison <michael.collison@arm.com>
 568
 569         * arm-dis.c (enum mve_instructions): Add new instructions.
 570         (enum mve_undefined): Add new reasons.
 571         (is_mve_encoding_conflict): Handle new instructions.
 572         (is_mve_undefined): Likewise.
 573         (is_mve_unpredictable): Likewise.
 574         (print_mve_undefined): Likewise.
 575         (print_mve_size): Likewise.
 576         (print_mve_shift_n): Likewise.
 577         (print_insn_mve): Likewise.
 578
 579 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 580             Michael Collison <michael.collison@arm.com>
 581
 582         * arm-dis.c (enum mve_instructions): Add new instructions.
 583         (is_mve_encoding_conflict): Handle new instructions.
 584         (is_mve_unpredictable): Likewise.
 585         (print_mve_rotate): Likewise.
 586         (print_mve_size): Likewise.
 587         (print_insn_mve): Likewise.
 588
 589 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 590             Michael Collison <michael.collison@arm.com>
 591
 592         * arm-dis.c (enum mve_instructions): Add new instructions.
 593         (is_mve_encoding_conflict): Handle new instructions.
 594         (is_mve_unpredictable): Likewise.
 595         (print_mve_size): Likewise.
 596         (print_insn_mve): Likewise.
 597
 598 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 599             Michael Collison <michael.collison@arm.com>
 600
 601         * arm-dis.c (enum mve_instructions): Add new instructions.
 602         (enum mve_undefined): Add new reasons.
 603         (is_mve_encoding_conflict): Handle new instructions.
 604         (is_mve_undefined): Likewise.
 605         (is_mve_unpredictable): Likewise.
 606         (print_mve_undefined): Likewise.
 607         (print_mve_size): Likewise.
 608         (print_insn_mve): Likewise.
 609
 610 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 611             Michael Collison <michael.collison@arm.com>
 612
 613         * arm-dis.c (enum mve_instructions): Add new instructions.
 614         (is_mve_encoding_conflict): Handle new instructions.
 615         (is_mve_undefined): Likewise.
 616         (is_mve_unpredictable): Likewise.
 617         (print_mve_size): Likewise.
 618         (print_insn_mve): Likewise.
 619
 620 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 621             Michael Collison <michael.collison@arm.com>
 622
 623         * arm-dis.c (enum mve_instructions): Add new instructions.
 624         (enum mve_unpredictable): Add new reasons.
 625         (enum mve_undefined): Likewise.
 626         (is_mve_okay_in_it): Handle new isntructions.
 627         (is_mve_encoding_conflict): Likewise.
 628         (is_mve_undefined): Likewise.
 629         (is_mve_unpredictable): Likewise.
 630         (print_mve_vmov_index): Likewise.
 631         (print_simd_imm8): Likewise.
 632         (print_mve_undefined): Likewise.
 633         (print_mve_unpredictable): Likewise.
 634         (print_mve_size): Likewise.
 635         (print_insn_mve): Likewise.
 636
 637 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 638             Michael Collison <michael.collison@arm.com>
 639
 640         * arm-dis.c (enum mve_instructions): Add new instructions.
 641         (enum mve_unpredictable): Add new reasons.
 642         (enum mve_undefined): Likewise.
 643         (is_mve_encoding_conflict): Handle new instructions.
 644         (is_mve_undefined): Likewise.
 645         (is_mve_unpredictable): Likewise.
 646         (print_mve_undefined): Likewise.
 647         (print_mve_unpredictable): Likewise.
 648         (print_mve_rounding_mode): Likewise.
 649         (print_mve_vcvt_size): Likewise.
 650         (print_mve_size): Likewise.
 651         (print_insn_mve): Likewise.
 652
 653 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 654             Michael Collison <michael.collison@arm.com>
 655
 656         * arm-dis.c (enum mve_instructions): Add new instructions.
 657         (enum mve_unpredictable): Add new reasons.
 658         (enum mve_undefined): Likewise.
 659         (is_mve_undefined): Handle new instructions.
 660         (is_mve_unpredictable): Likewise.
 661         (print_mve_undefined): Likewise.
 662         (print_mve_unpredictable): Likewise.
 663         (print_mve_size): Likewise.
 664         (print_insn_mve): Likewise.
 665
 666 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 667             Michael Collison <michael.collison@arm.com>
 668
 669         * arm-dis.c (enum mve_instructions): Add new instructions.
 670         (enum mve_undefined): Add new reasons.
 671         (insns): Add new instructions.
 672         (is_mve_encoding_conflict):
 673         (print_mve_vld_str_addr): New print function.
 674         (is_mve_undefined): Handle new instructions.
 675         (is_mve_unpredictable): Likewise.
 676         (print_mve_undefined): Likewise.
 677         (print_mve_size): Likewise.
 678         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 679         (print_insn_mve):  Handle new operands.
 680
 681 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 682             Michael Collison <michael.collison@arm.com>
 683
 684         * arm-dis.c (enum mve_instructions): Add new instructions.
 685         (enum mve_unpredictable): Add new reasons.
 686         (is_mve_encoding_conflict): Handle new instructions.
 687         (is_mve_unpredictable): Likewise.
 688         (mve_opcodes): Add new instructions.
 689         (print_mve_unpredictable): Handle new reasons.
 690         (print_mve_register_blocks): New print function.
 691         (print_mve_size): Handle new instructions.
 692         (print_insn_mve): Likewise.
 693
 694 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 695             Michael Collison <michael.collison@arm.com>
 696
 697         * arm-dis.c (enum mve_instructions): Add new instructions.
 698         (enum mve_unpredictable): Add new reasons.
 699         (enum mve_undefined): Likewise.
 700         (is_mve_encoding_conflict): Handle new instructions.
 701         (is_mve_undefined): Likewise.
 702         (is_mve_unpredictable): Likewise.
 703         (coprocessor_opcodes): Move NEON VDUP from here...
 704         (neon_opcodes): ... to here.
 705         (mve_opcodes): Add new instructions.
 706         (print_mve_undefined):  Handle new reasons.
 707         (print_mve_unpredictable): Likewise.
 708         (print_mve_size): Handle new instructions.
 709         (print_insn_neon): Handle vdup.
 710         (print_insn_mve): Handle new operands.
 711
 712 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 713             Michael Collison <michael.collison@arm.com>
 714
 715         * arm-dis.c (enum mve_instructions): Add new instructions.
 716         (enum mve_unpredictable): Add new values.
 717         (mve_opcodes): Add new instructions.
 718         (vec_condnames): New array with vector conditions.
 719         (mve_predicatenames): New array with predicate suffixes.
 720         (mve_vec_sizename): New array with vector sizes.
 721         (enum vpt_pred_state): New enum with vector predication states.
 722         (struct vpt_block): New struct type for vpt blocks.
 723         (vpt_block_state): Global struct to keep track of state.
 724         (mve_extract_pred_mask): New helper function.
 725         (num_instructions_vpt_block): Likewise.
 726         (mark_outside_vpt_block): Likewise.
 727         (mark_inside_vpt_block): Likewise.
 728         (invert_next_predicate_state): Likewise.
 729         (update_next_predicate_state): Likewise.
 730         (update_vpt_block_state): Likewise.
 731         (is_vpt_instruction): Likewise.
 732         (is_mve_encoding_conflict): Add entries for new instructions.
 733         (is_mve_unpredictable): Likewise.
 734         (print_mve_unpredictable): Handle new cases.
 735         (print_instruction_predicate): Likewise.
 736         (print_mve_size): New function.
 737         (print_vec_condition): New function.
 738         (print_insn_mve): Handle vpt blocks and new print operands.
 739
 740 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 741
 742         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 743         8, 14 and 15 for Armv8.1-M Mainline.
 744
 745 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 746             Michael Collison <michael.collison@arm.com>
 747
 748         * arm-dis.c (enum mve_instructions): New enum.
 749         (enum mve_unpredictable): Likewise.
 750         (enum mve_undefined): Likewise.
 751         (struct mopcode32): New struct.
 752         (is_mve_okay_in_it): New function.
 753         (is_mve_architecture): Likewise.
 754         (arm_decode_field): Likewise.
 755         (arm_decode_field_multiple): Likewise.
 756         (is_mve_encoding_conflict): Likewise.
 757         (is_mve_undefined): Likewise.
 758         (is_mve_unpredictable): Likewise.
 759         (print_mve_undefined): Likewise.
 760         (print_mve_unpredictable): Likewise.
 761         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 762         (print_insn_mve): New function.
 763         (print_insn_thumb32): Handle MVE architecture.
 764         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 765
 766 2019-05-10  Nick Clifton  <nickc@redhat.com>
 767
 768         PR 24538
 769         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 770         end of the table prematurely.
 771
 772 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 773
 774         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 775         macros for R6.
 776
 777 2019-05-11  Alan Modra  <amodra@gmail.com>
 778
 779         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 780         when -Mraw is in effect.
 781
 782 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 783
 784         * aarch64-dis-2.c: Regenerate.
 785         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 786         (OP_SVE_BBB): New variant set.
 787         (OP_SVE_DDDD): New variant set.
 788         (OP_SVE_HHH): New variant set.
 789         (OP_SVE_HHHU): New variant set.
 790         (OP_SVE_SSS): New variant set.
 791         (OP_SVE_SSSU): New variant set.
 792         (OP_SVE_SHH): New variant set.
 793         (OP_SVE_SBBU): New variant set.
 794         (OP_SVE_DSS): New variant set.
 795         (OP_SVE_DHHU): New variant set.
 796         (OP_SVE_VMV_HSD_BHS): New variant set.
 797         (OP_SVE_VVU_HSD_BHS): New variant set.
 798         (OP_SVE_VVVU_SD_BH): New variant set.
 799         (OP_SVE_VVVU_BHSD): New variant set.
 800         (OP_SVE_VVV_QHD_DBS): New variant set.
 801         (OP_SVE_VVV_HSD_BHS): New variant set.
 802         (OP_SVE_VVV_HSD_BHS2): New variant set.
 803         (OP_SVE_VVV_BHS_HSD): New variant set.
 804         (OP_SVE_VV_BHS_HSD): New variant set.
 805         (OP_SVE_VVV_SD): New variant set.
 806         (OP_SVE_VVU_BHS_HSD): New variant set.
 807         (OP_SVE_VZVV_SD): New variant set.
 808         (OP_SVE_VZVV_BH): New variant set.
 809         (OP_SVE_VZV_SD): New variant set.
 810         (aarch64_opcode_table): Add sve2 instructions.
 811
 812 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 813
 814         * aarch64-asm-2.c: Regenerated.
 815         * aarch64-dis-2.c: Regenerated.
 816         * aarch64-opc-2.c: Regenerated.
 817         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 818         for SVE_SHLIMM_UNPRED_22.
 819         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 820         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 821         operand.
 822
 823 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 824
 825         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 826         sve_size_tsz_bhs iclass encode.
 827         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 828         sve_size_tsz_bhs iclass decode.
 829
 830 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 831
 832         * aarch64-asm-2.c: Regenerated.
 833         * aarch64-dis-2.c: Regenerated.
 834         * aarch64-opc-2.c: Regenerated.
 835         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 836         for SVE_Zm4_11_INDEX.
 837         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 838         (fields): Handle SVE_i2h field.
 839         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 840         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 841
 842 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 843
 844         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 845         sve_shift_tsz_bhsd iclass encode.
 846         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 847         sve_shift_tsz_bhsd iclass decode.
 848
 849 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 850
 851         * aarch64-asm-2.c: Regenerated.
 852         * aarch64-dis-2.c: Regenerated.
 853         * aarch64-opc-2.c: Regenerated.
 854         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 855         (aarch64_encode_variant_using_iclass): Handle
 856         sve_shift_tsz_hsd iclass encode.
 857         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 858         sve_shift_tsz_hsd iclass decode.
 859         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 860         for SVE_SHRIMM_UNPRED_22.
 861         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 862         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 863         operand.
 864
 865 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 866
 867         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 868         sve_size_013 iclass encode.
 869         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 870         sve_size_013 iclass decode.
 871
 872 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 873
 874         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 875         sve_size_bh iclass encode.
 876         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 877         sve_size_bh iclass decode.
 878
 879 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 880
 881         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 882         sve_size_sd2 iclass encode.
 883         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 884         sve_size_sd2 iclass decode.
 885         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 886         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 887
 888 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 889
 890         * aarch64-asm-2.c: Regenerated.
 891         * aarch64-dis-2.c: Regenerated.
 892         * aarch64-opc-2.c: Regenerated.
 893         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 894         for SVE_ADDR_ZX.
 895         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 896         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 897
 898 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 899
 900         * aarch64-asm-2.c: Regenerated.
 901         * aarch64-dis-2.c: Regenerated.
 902         * aarch64-opc-2.c: Regenerated.
 903         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 904         for SVE_Zm3_11_INDEX.
 905         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 906         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 907         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 908         fields.
 909         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 910
 911 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 912
 913         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 914         sve_size_hsd2 iclass encode.
 915         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 916         sve_size_hsd2 iclass decode.
 917         * aarch64-opc.c (fields): Handle SVE_size field.
 918         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 919
 920 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 921
 922         * aarch64-asm-2.c: Regenerated.
 923         * aarch64-dis-2.c: Regenerated.
 924         * aarch64-opc-2.c: Regenerated.
 925         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 926         for SVE_IMM_ROT3.
 927         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 928         (fields): Handle SVE_rot3 field.
 929         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 930         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 931
 932 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 933
 934         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 935         instructions.
 936
 937 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 938
 939         * aarch64-tbl.h
 940         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 941         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 942         aarch64_feature_sve2bitperm): New feature sets.
 943         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 944         for feature set addresses.
 945         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 946         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 947
 948 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 949             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 950
 951         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 952         argument and set ASE_EVA_R6 appropriately.
 953         (set_default_mips_dis_options): Pass ISA to above.
 954         (parse_mips_dis_option): Likewise.
 955         * mips-opc.c (EVAR6): New macro.
 956         (mips_builtin_opcodes): Add llwpe, scwpe.
 957
 958 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 959
 960         * aarch64-asm-2.c: Regenerated.
 961         * aarch64-dis-2.c: Regenerated.
 962         * aarch64-opc-2.c: Regenerated.
 963         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 964         AARCH64_OPND_TME_UIMM16.
 965         (aarch64_print_operand): Likewise.
 966         * aarch64-tbl.h (QL_IMM_NIL): New.
 967         (TME): New.
 968         (_TME_INSN): New.
 969         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 970
 971 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 972
 973         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 974
 975 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 976             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 977
 978         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 979
 980 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 981
 982         * s12z-opc.h: Add extern "C" bracketing to help
 983         users who wish to use this interface in c++ code.
 984
 985 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 986
 987         * s12z-opc.c (bm_decode): Handle bit map operations with the
 988         "reserved0" mode.
 989
 990 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 991
 992         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 993         specifier.  Add entries for VLDR and VSTR of system registers.
 994         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 995         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 996         of %J and %K format specifier.
 997
 998 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 999
1000         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1001         Add new entries for VSCCLRM instruction.
1002         (print_insn_coprocessor): Handle new %C format control code.
1003
1004 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1005
1006         * arm-dis.c (enum isa): New enum.
1007         (struct sopcode32): New structure.
1008         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1009         set isa field of all current entries to ANY.
1010         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1011         Only match an entry if its isa field allows the current mode.
1012
1013 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1014
1015         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1016         CLRM.
1017         (print_insn_thumb32): Add logic to print %n CLRM register list.
1018
1019 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1020
1021         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1022         and %Q patterns.
1023
1024 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1025
1026         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1027         (print_insn_thumb32): Edit the switch case for %Z.
1028
1029 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1030
1031         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1032
1033 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1034
1035         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1036
1037 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1038
1039         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1040
1041 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1042
1043         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1044         Arm register with r13 and r15 unpredictable.
1045         (thumb32_opcodes): New instructions for bfx and bflx.
1046
1047 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1048
1049         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1050
1051 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1052
1053         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1054
1055 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1056
1057         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1058
1059 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1060
1061         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1062
1063 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1064
1065         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1066         "optr". ("operator" is a reserved word in c++).
1067
1068 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1069
1070         * aarch64-opc.c (aarch64_print_operand): Add case for
1071         AARCH64_OPND_Rt_SP.
1072         (verify_constraints): Likewise.
1073         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1074         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1075         to accept Rt|SP as first operand.
1076         (AARCH64_OPERANDS): Add new Rt_SP.
1077         * aarch64-asm-2.c: Regenerated.
1078         * aarch64-dis-2.c: Regenerated.
1079         * aarch64-opc-2.c: Regenerated.
1080
1081 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1082
1083         * aarch64-asm-2.c: Regenerated.
1084         * aarch64-dis-2.c: Likewise.
1085         * aarch64-opc-2.c: Likewise.
1086         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1087
1088 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1089
1090         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1091
1092 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1093
1094         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1095         * i386-init.h: Regenerated.
1096
1097 2019-04-07  Alan Modra  <amodra@gmail.com>
1098
1099         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1100         op_separator to control printing of spaces, comma and parens
1101         rather than need_comma, need_paren and spaces vars.
1102
1103 2019-04-07  Alan Modra  <amodra@gmail.com>
1104
1105         PR 24421
1106         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1107         (print_insn_neon, print_insn_arm): Likewise.
1108
1109 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1110
1111         * i386-dis-evex.h (evex_table): Updated to support BF16
1112         instructions.
1113         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1114         and EVEX_W_0F3872_P_3.
1115         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1116         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1117         * i386-opc.h (enum): Add CpuAVX512_BF16.
1118         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1119         * i386-opc.tbl: Add AVX512 BF16 instructions.
1120         * i386-init.h: Regenerated.
1121         * i386-tbl.h: Likewise.
1122
1123 2019-04-05  Alan Modra  <amodra@gmail.com>
1124
1125         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1126         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1127         to favour printing of "-" branch hint when using the "y" bit.
1128         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1129
1130 2019-04-05  Alan Modra  <amodra@gmail.com>
1131
1132         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1133         opcode until first operand is output.
1134
1135 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1136
1137         PR gas/24349
1138         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1139         (valid_bo_post_v2): Add support for 'at' branch hints.
1140         (insert_bo): Only error on branch on ctr.
1141         (get_bo_hint_mask): New function.
1142         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1143         for inserting 'at' branch hints.
1144         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1145         for extracting 'at' branch hints.
1146         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1147         (BOE): Delete operand.
1148         (BOM, BOP): New operands.
1149         (RM): Update value.
1150         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1151         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1152         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1153         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1154         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1155         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1156         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1157         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1158         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1159         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1160         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1161         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1162         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1163         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1164         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1165         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1166         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1167         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1168         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1169         bttarl+>: New extended mnemonics.
1170
1171 2019-03-28  Alan Modra  <amodra@gmail.com>
1172
1173         PR 24390
1174         * ppc-opc.c (BTF): Define.
1175         (powerpc_opcodes): Use for mtfsb*.
1176         * ppc-dis.c (print_insn_powerpc): Print fields with both
1177         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1178
1179 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1180
1181         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1182         (mapping_symbol_for_insn): Implement new algorithm.
1183         (print_insn): Remove duplicate code.
1184
1185 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1186
1187         * aarch64-dis.c (print_insn_aarch64):
1188         Implement override.
1189
1190 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1191
1192         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1193         order.
1194
1195 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1196
1197         * aarch64-dis.c (last_stop_offset): New.
1198         (print_insn_aarch64): Use stop_offset.
1199
1200 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1201
1202         PR gas/24359
1203         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1204         CPU_ANY_AVX2_FLAGS.
1205         * i386-init.h: Regenerated.
1206
1207 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1208
1209         PR gas/24348
1210         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1211         vmovdqu16, vmovdqu32 and vmovdqu64.
1212         * i386-tbl.h: Regenerated.
1213
1214 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1215
1216         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1217         from vstrszb, vstrszh, and vstrszf.
1218
1219 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1220
1221         * s390-opc.txt: Add instruction descriptions.
1222
1223 2019-02-08  Jim Wilson  <jimw@sifive.com>
1224
1225         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1226         <bne>: Likewise.
1227
1228 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1229
1230         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1231
1232 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1233
1234         PR binutils/23212
1235         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1236         * aarch64-opc.c (verify_elem_sd): New.
1237         (fields): Add FLD_sz entr.
1238         * aarch64-tbl.h (_SIMD_INSN): New.
1239         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1240         fmulx scalar and vector by element isns.
1241
1242 2019-02-07  Nick Clifton  <nickc@redhat.com>
1243
1244         * po/sv.po: Updated Swedish translation.
1245
1246 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1247
1248         * s390-mkopc.c (main): Accept arch13 as cpu string.
1249         * s390-opc.c: Add new instruction formats and instruction opcode
1250         masks.
1251         * s390-opc.txt: Add new arch13 instructions.
1252
1253 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1254
1255         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1256         (aarch64_opcode): Change encoding for stg, stzg
1257         st2g and st2zg.
1258         * aarch64-asm-2.c: Regenerated.
1259         * aarch64-dis-2.c: Regenerated.
1260         * aarch64-opc-2.c: Regenerated.
1261
1262 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1263
1264         * aarch64-asm-2.c: Regenerated.
1265         * aarch64-dis-2.c: Likewise.
1266         * aarch64-opc-2.c: Likewise.
1267         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1268
1269 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1270             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1271
1272         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1273         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1274         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1275         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1276         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1277         case for ldstgv_indexed.
1278         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1279         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1280         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1281         * aarch64-asm-2.c: Regenerated.
1282         * aarch64-dis-2.c: Regenerated.
1283         * aarch64-opc-2.c: Regenerated.
1284
1285 2019-01-23  Nick Clifton  <nickc@redhat.com>
1286
1287         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1288
1289 2019-01-21  Nick Clifton  <nickc@redhat.com>
1290
1291         * po/de.po: Updated German translation.
1292         * po/uk.po: Updated Ukranian translation.
1293
1294 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1295         * mips-dis.c (mips_arch_choices): Fix typo in
1296         gs464, gs464e and gs264e descriptors.
1297
1298 2019-01-19  Nick Clifton  <nickc@redhat.com>
1299
1300         * configure: Regenerate.
1301         * po/opcodes.pot: Regenerate.
1302
1303 2018-06-24  Nick Clifton  <nickc@redhat.com>
1304
1305         2.32 branch created.
1306
1307 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1308
1309         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1310         if it is null.
1311         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1312         zero.
1313
1314 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1315
1316         * configure: Regenerate.
1317
1318 2019-01-07  Alan Modra  <amodra@gmail.com>
1319
1320         * configure: Regenerate.
1321         * po/POTFILES.in: Regenerate.
1322
1323 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1324
1325         * s12z-opc.c: New file.
1326         * s12z-opc.h: New file.
1327         * s12z-dis.c: Removed all code not directly related to display
1328         of instructions.  Used the interface provided by the new files
1329         instead.
1330         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1331         * Makefile.in: Regenerate.
1332         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1333         * configure: Regenerate.
1334
1335 2019-01-01  Alan Modra  <amodra@gmail.com>
1336
1337         Update year range in copyright notice of all files.
1338
1339 For older changes see ChangeLog-2018
1340 \f
1341 Copyright (C) 2019 Free Software Foundation, Inc.
1342
1343 Copying and distribution of this file, with or without modification,
1344 are permitted in any medium without royalty provided the copyright
1345 notice and this notice are preserved.
1346
1347 Local Variables:
1348 mode: change-log
1349 left-margin: 8
1350 fill-column: 74
1351 version-control: never
1352 End: