opcodes/ChangeLog

   1 2020-03-20  Alan Modra  <amodra@gmail.com>
   2
   3         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
   4         Initialize parts of buffer not written when handling a possible
   5         2-byte insn at end of section.  Don't attempt decoding of such
   6         an insn by the 4-byte machinery.
   7
   8 2020-03-20  Alan Modra  <amodra@gmail.com>
   9
  10         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
  11         partially filled buffer.  Prevent lookup of 4-byte insns when
  12         only VLE 2-byte insns are possible due to section size.  Print
  13         ".word" rather than ".long" for 2-byte leftovers.
  14
  15 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
  16
  17         PR 25641
  18         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
  19
  20 2020-03-13  Jan Beulich  <jbeulich@suse.com>
  21
  22         * i386-dis.c (X86_64_0D): Rename to ...
  23         (X86_64_0E): ... this.
  24
  25 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
  26
  27         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
  28         * Makefile.in: Regenerated.
  29
  30 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  31
  32         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
  33         3-operand pseudos.
  34         * i386-tbl.h: Re-generate.
  35
  36 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  37
  38         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
  39         vprot*, vpsha*, and vpshl*.
  40         * i386-tbl.h: Re-generate.
  41
  42 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  43
  44         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
  45         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
  46         * i386-tbl.h: Re-generate.
  47
  48 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  49
  50         * i386-gen.c (set_bitfield): Ignore zero-length field names.
  51         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
  52         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
  53         * i386-tbl.h: Re-generate.
  54
  55 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  56
  57         * i386-gen.c (struct template_arg, struct template_instance,
  58         struct template_param, struct template, templates,
  59         parse_template, expand_templates): New.
  60         (process_i386_opcodes): Various local variables moved to
  61         expand_templates. Call parse_template and expand_templates.
  62         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
  63         * i386-tbl.h: Re-generate.
  64
  65 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  66
  67         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
  68         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
  69         register and memory source templates. Replace VexW= by VexW*
  70         where applicable.
  71         * i386-tbl.h: Re-generate.
  72
  73 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  74
  75         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
  76         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
  77         * i386-tbl.h: Re-generate.
  78
  79 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  80
  81         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
  82         * i386-tbl.h: Re-generate.
  83
  84 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  85
  86         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
  87         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
  88         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
  89         VexW0 on SSE2AVX variants.
  90         (vmovq): Drop NoRex64 from XMM/XMM variants.
  91         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
  92         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
  93         applicable use VexW0.
  94         * i386-tbl.h: Re-generate.
  95
  96 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  97
  98         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
  99         * i386-opc.h (Rex64): Delete.
 100         (struct i386_opcode_modifier): Remove rex64 field.
 101         * i386-opc.tbl (crc32): Drop Rex64.
 102         Replace Rex64 with Size64 everywhere else.
 103         * i386-tbl.h: Re-generate.
 104
 105 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 106
 107         * i386-dis.c (OP_E_memory): Exclude recording of used address
 108         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 109         addressed memory operands for MPX insns.
 110
 111 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 112
 113         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 114         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 115         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 116         (ptwrite): Split into non-64-bit and 64-bit forms.
 117         * i386-tbl.h: Re-generate.
 118
 119 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 120
 121         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 122         template.
 123         * i386-tbl.h: Re-generate.
 124
 125 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 126
 127         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 128         (prefix_table): Move vmmcall here. Add vmgexit.
 129         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 130         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 131         (cpu_flags): Add CpuSEV_ES entry.
 132         * i386-opc.h (CpuSEV_ES): New.
 133         (union i386_cpu_flags): Add cpusev_es field.
 134         * i386-opc.tbl (vmgexit): New.
 135         * i386-init.h, i386-tbl.h: Re-generate.
 136
 137 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 138
 139         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 140         with MnemonicSize.
 141         * i386-opc.h (IGNORESIZE): New.
 142         (DEFAULTSIZE): Likewise.
 143         (IgnoreSize): Removed.
 144         (DefaultSize): Likewise.
 145         (MnemonicSize): New.
 146         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 147         mnemonicsize.
 148         * i386-opc.tbl (IgnoreSize): New.
 149         (DefaultSize): Likewise.
 150         * i386-tbl.h: Regenerated.
 151
 152 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 153
 154         PR 25627
 155         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 156         instructions.
 157
 158 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 159
 160         PR gas/25622
 161         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 162         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 163         * i386-tbl.h: Regenerated.
 164
 165 2020-02-26  Alan Modra  <amodra@gmail.com>
 166
 167         * aarch64-asm.c: Indent labels correctly.
 168         * aarch64-dis.c: Likewise.
 169         * aarch64-gen.c: Likewise.
 170         * aarch64-opc.c: Likewise.
 171         * alpha-dis.c: Likewise.
 172         * i386-dis.c: Likewise.
 173         * nds32-asm.c: Likewise.
 174         * nfp-dis.c: Likewise.
 175         * visium-dis.c: Likewise.
 176
 177 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 178
 179         * arc-regs.h (int_vector_base): Make it available for all ARC
 180         CPUs.
 181
 182 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 183
 184         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 185         changed.
 186
 187 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 188
 189         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 190         c.mv/c.li if rs1 is zero.
 191
 192 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 193
 194         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 195         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 196         CPU_POPCNT_FLAGS.
 197         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 198         * i386-opc.h (CpuABM): Removed.
 199         (CpuPOPCNT): New.
 200         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 201         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 202         popcnt.  Remove CpuABM from lzcnt.
 203         * i386-init.h: Regenerated.
 204         * i386-tbl.h: Likewise.
 205
 206 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 207
 208         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 209         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 210         VexW1 instead of open-coding them.
 211         * i386-tbl.h: Re-generate.
 212
 213 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 214
 215         * i386-opc.tbl (AddrPrefixOpReg): Define.
 216         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 217         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 218         templates. Drop NoRex64.
 219         * i386-tbl.h: Re-generate.
 220
 221 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 222
 223         PR gas/6518
 224         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 225         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 226         into Intel syntax instance (with Unpsecified) and AT&T one
 227         (without).
 228         (vcvtneps2bf16): Likewise, along with folding the two so far
 229         separate ones.
 230         * i386-tbl.h: Re-generate.
 231
 232 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 233
 234         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 235         CPU_ANY_SSE4A_FLAGS.
 236
 237 2020-02-17  Alan Modra  <amodra@gmail.com>
 238
 239         * i386-gen.c (cpu_flag_init): Correct last change.
 240
 241 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 242
 243         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 244         CPU_ANY_SSE4_FLAGS.
 245
 246 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 247
 248         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 249         (movzx): Likewise.
 250
 251 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 252
 253         PR gas/25438
 254         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 255         destination for Cpu64-only variant.
 256         (movzx): Fold patterns.
 257         * i386-tbl.h: Re-generate.
 258
 259 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 260
 261         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 262         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 263         CPU_ANY_SSE4_FLAGS entry.
 264         * i386-init.h: Re-generate.
 265
 266 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 267
 268         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 269         with Unspecified, making the present one AT&T syntax only.
 270         * i386-tbl.h: Re-generate.
 271
 272 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 273
 274         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 275         * i386-tbl.h: Re-generate.
 276
 277 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 278
 279         PR gas/24546
 280         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 281         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 282         Amd64 and Intel64 templates.
 283         (call, jmp): Likewise for far indirect variants. Dro
 284         Unspecified.
 285         * i386-tbl.h: Re-generate.
 286
 287 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 288
 289         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 290         * i386-opc.h (ShortForm): Delete.
 291         (struct i386_opcode_modifier): Remove shortform field.
 292         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 293         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 294         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 295         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 296         Drop ShortForm.
 297         * i386-tbl.h: Re-generate.
 298
 299 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 300
 301         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 302         fucompi): Drop ShortForm from operand-less templates.
 303         * i386-tbl.h: Re-generate.
 304
 305 2020-02-11  Alan Modra  <amodra@gmail.com>
 306
 307         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 308         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 309         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 310         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 311         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 312
 313 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 314
 315         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 316         (cde_opcodes): Add VCX* instructions.
 317
 318 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 319             Matthew Malcomson  <matthew.malcomson@arm.com>
 320
 321         * arm-dis.c (struct cdeopcode32): New.
 322         (CDE_OPCODE): New macro.
 323         (cde_opcodes): New disassembly table.
 324         (regnames): New option to table.
 325         (cde_coprocs): New global variable.
 326         (print_insn_cde): New
 327         (print_insn_thumb32): Use print_insn_cde.
 328         (parse_arm_disassembler_options): Parse coprocN args.
 329
 330 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 331
 332         PR gas/25516
 333         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 334         with ISA64.
 335         * i386-opc.h (AMD64): Removed.
 336         (Intel64): Likewose.
 337         (AMD64): New.
 338         (INTEL64): Likewise.
 339         (INTEL64ONLY): Likewise.
 340         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 341         * i386-opc.tbl (Amd64): New.
 342         (Intel64): Likewise.
 343         (Intel64Only): Likewise.
 344         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 345         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 346         * i386-tbl.h: Regenerated.
 347
 348 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 349
 350         PR 25469
 351         * z80-dis.c: Add support for GBZ80 opcodes.
 352
 353 2020-02-04  Alan Modra  <amodra@gmail.com>
 354
 355         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 356
 357 2020-02-03  Alan Modra  <amodra@gmail.com>
 358
 359         * m32c-ibld.c: Regenerate.
 360
 361 2020-02-01  Alan Modra  <amodra@gmail.com>
 362
 363         * frv-ibld.c: Regenerate.
 364
 365 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 366
 367         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 368         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 369         (OP_E_memory): Replace xmm_mdq_mode case label by
 370         vex_scalar_w_dq_mode one.
 371         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 372
 373 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 374
 375         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 376         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 377         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 378         (intel_operand_size): Drop vex_w_dq_mode case label.
 379
 380 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 381
 382         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 383         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 384
 385 2020-01-30  Alan Modra  <amodra@gmail.com>
 386
 387         * m32c-ibld.c: Regenerate.
 388
 389 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 390
 391         * bpf-opc.c: Regenerate.
 392
 393 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 394
 395         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 396         (dis386): Use them to replace C2/C3 table entries.
 397         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 398         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 399         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 400         * i386-tbl.h: Re-generate.
 401
 402 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 403
 404         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 405         forms.
 406         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 407         DefaultSize.
 408         * i386-tbl.h: Re-generate.
 409
 410 2020-01-30  Alan Modra  <amodra@gmail.com>
 411
 412         * tic4x-dis.c (tic4x_dp): Make unsigned.
 413
 414 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 415             Jan Beulich  <jbeulich@suse.com>
 416
 417         PR binutils/25445
 418         * i386-dis.c (MOVSXD_Fixup): New function.
 419         (movsxd_mode): New enum.
 420         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 421         (intel_operand_size): Handle movsxd_mode.
 422         (OP_E_register): Likewise.
 423         (OP_G): Likewise.
 424         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 425         register on movsxd.  Add movsxd with 16-bit destination register
 426         for AMD64 and Intel64 ISAs.
 427         * i386-tbl.h: Regenerated.
 428
 429 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 430
 431         PR 25403
 432         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 433         * aarch64-asm-2.c: Regenerate
 434         * aarch64-dis-2.c: Likewise.
 435         * aarch64-opc-2.c: Likewise.
 436
 437 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 438
 439         * i386-opc.tbl (sysret): Drop DefaultSize.
 440         * i386-tbl.h: Re-generate.
 441
 442 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 443
 444         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 445         Dword.
 446         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 447         * i386-tbl.h: Re-generate.
 448
 449 2020-01-20  Nick Clifton  <nickc@redhat.com>
 450
 451         * po/de.po: Updated German translation.
 452         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 453         * po/uk.po: Updated Ukranian translation.
 454
 455 2020-01-20  Alan Modra  <amodra@gmail.com>
 456
 457         * hppa-dis.c (fput_const): Remove useless cast.
 458
 459 2020-01-20  Alan Modra  <amodra@gmail.com>
 460
 461         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 462
 463 2020-01-18  Nick Clifton  <nickc@redhat.com>
 464
 465         * configure: Regenerate.
 466         * po/opcodes.pot: Regenerate.
 467
 468 2020-01-18  Nick Clifton  <nickc@redhat.com>
 469
 470         Binutils 2.34 branch created.
 471
 472 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 473
 474         * opintl.h: Fix spelling error (seperate).
 475
 476 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 477
 478         * i386-opc.tbl: Add {vex} pseudo prefix.
 479         * i386-tbl.h: Regenerated.
 480
 481 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 482
 483         PR 25376
 484         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 485         (neon_opcodes): Likewise.
 486         (select_arm_features): Make sure we enable MVE bits when selecting
 487         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 488         any architecture.
 489
 490 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 491
 492         * i386-opc.tbl: Drop stale comment from XOP section.
 493
 494 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 495
 496         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 497         (extractps): Add VexWIG to SSE2AVX forms.
 498         * i386-tbl.h: Re-generate.
 499
 500 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 501
 502         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 503         Size64 from and use VexW1 on SSE2AVX forms.
 504         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 505         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 506         * i386-tbl.h: Re-generate.
 507
 508 2020-01-15  Alan Modra  <amodra@gmail.com>
 509
 510         * tic4x-dis.c (tic4x_version): Make unsigned long.
 511         (optab, optab_special, registernames): New file scope vars.
 512         (tic4x_print_register): Set up registernames rather than
 513         malloc'd registertable.
 514         (tic4x_disassemble): Delete optable and optable_special.  Use
 515         optab and optab_special instead.  Throw away old optab,
 516         optab_special and registernames when info->mach changes.
 517
 518 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 519
 520         PR 25377
 521         * z80-dis.c (suffix): Use .db instruction to generate double
 522         prefix.
 523
 524 2020-01-14  Alan Modra  <amodra@gmail.com>
 525
 526         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 527         values to unsigned before shifting.
 528
 529 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 530
 531         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 532         flow instructions.
 533         (print_insn_thumb16, print_insn_thumb32): Likewise.
 534         (print_insn): Initialize the insn info.
 535         * i386-dis.c (print_insn): Initialize the insn info fields, and
 536         detect jumps.
 537
 538 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 539
 540         * arc-opc.c (C_NE): Make it required.
 541
 542 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 543
 544         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 545         reserved register name.
 546
 547 2020-01-13  Alan Modra  <amodra@gmail.com>
 548
 549         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 550         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 551
 552 2020-01-13  Alan Modra  <amodra@gmail.com>
 553
 554         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 555         result of wasm_read_leb128 in a uint64_t and check that bits
 556         are not lost when copying to other locals.  Use uint32_t for
 557         most locals.  Use PRId64 when printing int64_t.
 558
 559 2020-01-13  Alan Modra  <amodra@gmail.com>
 560
 561         * score-dis.c: Formatting.
 562         * score7-dis.c: Formatting.
 563
 564 2020-01-13  Alan Modra  <amodra@gmail.com>
 565
 566         * score-dis.c (print_insn_score48): Use unsigned variables for
 567         unsigned values.  Don't left shift negative values.
 568         (print_insn_score32): Likewise.
 569         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 570
 571 2020-01-13  Alan Modra  <amodra@gmail.com>
 572
 573         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 574
 575 2020-01-13  Alan Modra  <amodra@gmail.com>
 576
 577         * fr30-ibld.c: Regenerate.
 578
 579 2020-01-13  Alan Modra  <amodra@gmail.com>
 580
 581         * xgate-dis.c (print_insn): Don't left shift signed value.
 582         (ripBits): Formatting, use 1u.
 583
 584 2020-01-10  Alan Modra  <amodra@gmail.com>
 585
 586         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 587         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 588
 589 2020-01-10  Alan Modra  <amodra@gmail.com>
 590
 591         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 592         and XRREG value earlier to avoid a shift with negative exponent.
 593         * m10200-dis.c (disassemble): Similarly.
 594
 595 2020-01-09  Nick Clifton  <nickc@redhat.com>
 596
 597         PR 25224
 598         * z80-dis.c (ld_ii_ii): Use correct cast.
 599
 600 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 601
 602         PR 25224
 603         * z80-dis.c (ld_ii_ii): Use character constant when checking
 604         opcode byte value.
 605
 606 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 607
 608         * i386-dis.c (SEP_Fixup): New.
 609         (SEP): Define.
 610         (dis386_twobyte): Use it for sysenter/sysexit.
 611         (enum x86_64_isa): Change amd64 enumerator to value 1.
 612         (OP_J): Compare isa64 against intel64 instead of amd64.
 613         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 614         forms.
 615         * i386-tbl.h: Re-generate.
 616
 617 2020-01-08  Alan Modra  <amodra@gmail.com>
 618
 619         * z8k-dis.c: Include libiberty.h
 620         (instr_data_s): Make max_fetched unsigned.
 621         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 622         Don't exceed byte_info bounds.
 623         (output_instr): Make num_bytes unsigned.
 624         (unpack_instr): Likewise for nibl_count and loop.
 625         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 626         idx unsigned.
 627         * z8k-opc.h: Regenerate.
 628
 629 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 630
 631         * arc-tbl.h (llock): Use 'LLOCK' as class.
 632         (llockd): Likewise.
 633         (scond): Use 'SCOND' as class.
 634         (scondd): Likewise.
 635         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 636         (scondd): Likewise.
 637
 638 2020-01-06  Alan Modra  <amodra@gmail.com>
 639
 640         * m32c-ibld.c: Regenerate.
 641
 642 2020-01-06  Alan Modra  <amodra@gmail.com>
 643
 644         PR 25344
 645         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 646         Peek at next byte to prevent recursion on repeated prefix bytes.
 647         Ensure uninitialised "mybuf" is not accessed.
 648         (print_insn_z80): Don't zero n_fetch and n_used here,..
 649         (print_insn_z80_buf): ..do it here instead.
 650
 651 2020-01-04  Alan Modra  <amodra@gmail.com>
 652
 653         * m32r-ibld.c: Regenerate.
 654
 655 2020-01-04  Alan Modra  <amodra@gmail.com>
 656
 657         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 658
 659 2020-01-04  Alan Modra  <amodra@gmail.com>
 660
 661         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 662
 663 2020-01-04  Alan Modra  <amodra@gmail.com>
 664
 665         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 666
 667 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 668
 669         * aarch64-tbl.h (aarch64_opcode_table): Use
 670         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 671
 672 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 673
 674         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 675         forms of SUDOT and USDOT.
 676
 677 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 678
 679         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 680         uzip{1,2}.
 681         * opcodes/aarch64-dis-2.c: Re-generate.
 682
 683 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 684
 685         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 686         FMMLA encoding.
 687         * opcodes/aarch64-dis-2.c: Re-generate.
 688
 689 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 690
 691         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 692
 693 2020-01-01  Alan Modra  <amodra@gmail.com>
 694
 695         Update year range in copyright notice of all files.
 696
 697 For older changes see ChangeLog-2019
 698 \f
 699 Copyright (C) 2020 Free Software Foundation, Inc.
 700
 701 Copying and distribution of this file, with or without modification,
 702 are permitted in any medium without royalty provided the copyright
 703 notice and this notice are preserved.
 704
 705 Local Variables:
 706 mode: change-log
 707 left-margin: 8
 708 fill-column: 74
 709 version-control: never
 710 End: