opcodes/ChangeLog

   1 2005-01-10  Andreas Schwab  <schwab@suse.de>
   2
   3         * disassemble.c (disassemble_init_for_target) <case
   4         bfd_arch_ia64>: Set skip_zeroes to 16.
   5         <case bfd_arch_tic4x>: Set skip_zeroes to 32.
   6
   7 2004-12-23  Tomer Levi  <Tomer.Levi@nsc.com>
   8
   9         * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
  10
  11 2004-12-14  Svein E. Seldal  <Svein.Seldal@solidas.com>
  12
  13         * avr-dis.c: Prettyprint. Added printing of symbol names in all
  14         memory references. Convert avr_operand() to C90 formatting.
  15
  16 2004-12-05  Tomer Levi  <Tomer.Levi@nsc.com>
  17
  18         * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
  19
  20 2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
  21
  22         * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
  23         (no_op_insn): Initialize array with instructions that have no
  24         operands.
  25         * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
  26
  27 2004-11-29  Richard Earnshaw  <rearnsha@arm.com>
  28
  29         * arm-dis.c: Correct top-level comment.
  30
  31 2004-11-27  Richard Earnshaw  <rearnsha@arm.com>
  32
  33         * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
  34         architecuture defining the insn.
  35         (arm_opcodes, thumb_opcodes): Delete.  Move to ...
  36         * arm-dis.c (arm_opcodes, thumb_opcodes): Here.  Add architecutre
  37         field.
  38         Also include opcode/arm.h.
  39         * Makefile.am (arm-dis.lo): Update dependency list.
  40         * Makefile.in: Regenerate.
  41
  42 2004-11-22  Ravi Ramaseshan  <ravi.ramaseshan@codito.com>
  43
  44         * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
  45         reflect the change to the short immediate syntax.
  46
  47 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
  48
  49         * or32-opc.c (debug): Warning fix.
  50         * po/POTFILES.in: Regenerate.
  51
  52         * maxq-dis.c: Formatting.
  53         (print_insn): Warning fix.
  54
  55 2004-11-17  Daniel Jacobowitz  <dan@codesourcery.com>
  56
  57         * arm-dis.c (WORD_ADDRESS): Define.
  58         (print_insn): Use it.  Correct big-endian end-of-section handling.
  59
  60 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
  61             Vineet Sharma      <vineets@noida.hcltech.com>
  62
  63         * maxq-dis.c: New file.
  64         * disassemble.c (ARCH_maxq): Define.
  65         (disassembler): Add 'print_insn_maxq_little' for handling maxq
  66         instructions..
  67         * configure.in: Add case for bfd_maxq_arch.
  68         * configure: Regenerate.
  69         * Makefile.am: Add support for maxq-dis.c
  70         * Makefile.in: Regenerate.
  71         * aclocal.m4: Regenerate.
  72
  73 2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
  74
  75         * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
  76         mode.
  77         * crx-dis.c: Likewise.
  78
  79 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
  80
  81         Generally, handle CRISv32.
  82         * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
  83         (struct cris_disasm_data): New type.
  84         (format_reg, format_hex, cris_constraint, print_flags)
  85         (get_opcode_entry): Add struct cris_disasm_data * parameter.  All
  86         callers changed.
  87         (format_sup_reg, print_insn_crisv32_with_register_prefix)
  88         (print_insn_crisv32_without_register_prefix)
  89         (print_insn_crisv10_v32_with_register_prefix)
  90         (print_insn_crisv10_v32_without_register_prefix)
  91         (cris_parse_disassembler_options): New functions.
  92         (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
  93         parameter.  All callers changed.
  94         (get_opcode_entry): Call malloc, not xmalloc.  Return NULL on
  95         failure.
  96         (cris_constraint) <case 'Y', 'U'>: New cases.
  97         (bytes_to_skip): Handle 'Y' and 'N' as 's'.  Skip size is 4 bytes
  98         for constraint 'n'.
  99         (print_with_operands) <case 'Y'>: New case.
 100         (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
 101         <case 'N', 'Y', 'Q'>: New cases.
 102         (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
 103         (print_insn_cris_with_register_prefix)
 104         (print_insn_cris_without_register_prefix): Call
 105         cris_parse_disassembler_options.
 106         * cris-opc.c (cris_spec_regs): Mention that this table isn't used
 107         for CRISv32 and the size of immediate operands.  New v32-only
 108         entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
 109         spc.  Add v32-only 4-byte entries for p2, p3, p5 and p6.  Change
 110         ccr, ibr, irp to be v0..v10.  Change bar, dccr to be v8..v10.
 111         Change brp to be v3..v10.
 112         (cris_support_regs): New vector.
 113         (cris_opcodes): Update head comment.  New format characters '[',
 114         ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
 115         Add new opcodes for v32 and adjust existing opcodes to accommodate
 116         differences to earlier variants.
 117         (cris_cond15s): New vector.
 118
 119 2004-11-04 Jan Beulich <jbeulich@novell.com>
 120
 121         * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
 122         (indirEb): Remove.
 123         (Mp): Use f_mode rather than none at all.
 124         (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
 125         replaces what previously was x_mode; x_mode now means 128-bit SSE
 126         operands.
 127         (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
 128         mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
 129         pinsrw's second operand is Edqw.
 130         (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
 131         operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
 132         fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
 133         mode when an operand size override is present or always suffixing.
 134         More instructions will need to be added to this group.
 135         (putop): Handle new macro chars 'C' (short/long suffix selector),
 136         'I' (Intel mode override for following macro char), and 'J' (for
 137         adding the 'l' prefix to far branches in AT&T mode). When an
 138         alternative was specified in the template, honor macro character when
 139         specified for Intel mode.
 140         (OP_E): Handle new *_mode values. Correct pointer specifications for
 141         memory operands. Consolidate output of index register.
 142         (OP_G): Handle new *_mode values.
 143         (OP_I): Handle const_1_mode.
 144         (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
 145         respective opcode prefix bits have been consumed.
 146         (OP_EM, OP_EX): Provide some default handling for generating pointer
 147         specifications.
 148
 149 2004-10-28  Tomer Levi  <Tomer.Levi@nsc.com>
 150
 151         * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
 152         COP_INST macro.
 153
 154 2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 155
 156         * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
 157         (getregliststring): Support HI/LO and user registers.
 158         * crx-opc.c (crx_instruction): Update data structure according to the
 159         rearrangement done in CRX opcode header file.
 160         (crx_regtab):  Likewise.
 161         (crx_optab):  Likewise.
 162         (crx_instruction): Reorder load/stor instructions, remove unsupported
 163         formats.
 164         support new Co-Processor instruction 'cpi'.
 165
 166 2004-10-27  Nick Clifton  <nickc@redhat.com>
 167
 168         * opcodes/iq2000-asm.c: Regenerate.
 169         * opcodes/iq2000-desc.c: Regenerate.
 170         * opcodes/iq2000-desc.h: Regenerate.
 171         * opcodes/iq2000-dis.c: Regenerate.
 172         * opcodes/iq2000-ibld.c: Regenerate.
 173         * opcodes/iq2000-opc.c: Regenerate.
 174         * opcodes/iq2000-opc.h: Regenerate.
 175
 176 2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 177
 178         * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
 179         us4, us5 (respectively).
 180         Remove unsupported 'popa' instruction.
 181         Reverse operands order in store co-processor instructions.
 182
 183 2004-10-15  Alan Modra  <amodra@bigpond.net.au>
 184
 185         * Makefile.am: Run "make dep-am"
 186         * Makefile.in: Regenerate.
 187
 188 2004-10-12  Bob Wilson  <bob.wilson@acm.org>
 189
 190         * xtensa-dis.c: Use ISO C90 formatting.
 191
 192 2004-10-09  Alan Modra  <amodra@bigpond.net.au>
 193
 194         * ppc-opc.c: Revert 2004-09-09 change.
 195
 196 2004-10-07  Bob Wilson  <bob.wilson@acm.org>
 197
 198         * xtensa-dis.c (state_names): Delete.
 199         (fetch_data): Use xtensa_isa_maxlength.
 200         (print_xtensa_operand): Replace operand parameter with opcode/operand
 201         pair.  Remove print_sr_name parameter.  Use new xtensa-isa.h functions.
 202         (print_insn_xtensa): Use new xtensa-isa.h functions.  Handle multislot
 203         instruction bundles.  Use xmalloc instead of malloc.
 204
 205 2004-10-07  David Gibson  <david@gibson.dropbear.id.au>
 206
 207         * ppc-opc.c: Replace literal "0"s with NULLs in pointer
 208         initializers.
 209
 210 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 211
 212         * crx-opc.c (crx_instruction): Support Co-processor insns.
 213         * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
 214         (getregliststring): Change function to use the above enum.
 215         (print_arg): Handle CO-Processor insns.
 216         (crx_cinvs): Add 'b' option to invalidate the branch-target
 217         cache.
 218
 219 2004-10-06  Aldy Hernandez  <aldyh@redhat.com>
 220
 221         * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
 222         efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
 223         efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
 224         efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
 225         efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
 226
 227 2004-10-01  Bill Farmer  <Bill@the-farmers.freeserve.co.uk>
 228
 229         * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
 230         rather than add it.
 231
 232 2004-09-30  Paul Brook  <paul@codesourcery.com>
 233
 234         * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
 235         * arm-opc.h: Document %e.  Add ARMv6ZK instructions.
 236
 237 2004-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 238
 239         * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
 240         (CONFIG_STATUS_DEPENDENCIES): New.
 241         (Makefile): Removed.
 242         (config.status): Likewise.
 243         * Makefile.in: Regenerated.
 244
 245 2004-09-17  Alan Modra  <amodra@bigpond.net.au>
 246
 247         * Makefile.am: Run "make dep-am".
 248         * Makefile.in: Regenerate.
 249         * aclocal.m4: Regenerate.
 250         * configure: Regenerate.
 251         * po/POTFILES.in: Regenerate.
 252         * po/opcodes.pot: Regenerate.
 253
 254 2004-09-11  Andreas Schwab  <schwab@suse.de>
 255
 256         * configure: Rebuild.
 257
 258 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 259
 260         * ppc-opc.c (L): Make this field not optional.
 261
 262 2004-09-03  Tomer Levi  <Tomer.Levi@nsc.com>
 263
 264         * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
 265         Fix parameter to 'm[t|f]csr' insns.
 266
 267 2004-08-30  Nathanael Nerode  <neroden@gcc.gnu.org>
 268
 269         * configure.in: Autoupdate to autoconf 2.59.
 270         * aclocal.m4: Rebuild with aclocal 1.4p6.
 271         * configure: Rebuild with autoconf 2.59.
 272         * Makefile.in: Rebuild with automake 1.4p6 (picking up
 273         bfd changes for autoconf 2.59 on the way).
 274         * config.in: Rebuild with autoheader 2.59.
 275
 276 2004-08-27  Richard Sandiford  <rsandifo@redhat.com>
 277
 278         * frv-desc.[ch], frv-opc.[ch]: Regenerated.
 279
 280 2004-07-30  Michal Ludvig  <mludvig@suse.cz>
 281
 282         * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
 283         (GRPPADLCK2): New define.
 284         (twobyte_has_modrm): True for 0xA6.
 285         (grps): GRPPADLCK2 for opcode 0xA6.
 286
 287 2004-07-29  Alexandre Oliva  <aoliva@redhat.com>
 288
 289         Introduce SH2a support.
 290         * sh-opc.h (arch_sh2a_base): Renumber.
 291         (arch_sh2a_nofpu_base): Remove.
 292         (arch_sh_base_mask): Adjust.
 293         (arch_opann_mask): New.
 294         (arch_sh2a, arch_sh2a_nofpu): Adjust.
 295         (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
 296         (sh_table): Adjust whitespace.
 297         2004-02-24  Corinna Vinschen  <vinschen@redhat.com>
 298         * sh-opc.h (arch_sh2a_nofpu_up): New.  Use instead of arch_sh2a_up in
 299         instruction list throughout.
 300         (arch_sh2a_up): Redefine to include fpu instruction set.  Use instead
 301         of arch_sh2a in instruction list throughout.
 302         (arch_sh2e_up): Accomodate above changes.
 303         (arch_sh2_up): Ditto.
 304         2004-02-20  Corinna Vinschen  <vinschen@redhat.com>
 305         * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
 306         2004-02-18  Corinna Vinschen  <vinschen@redhat.com>
 307         * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
 308         * sh-opc.h (arch_sh2a_nofpu): New.
 309         (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
 310         (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
 311         instruction.
 312         2004-01-20  DJ Delorie  <dj@redhat.com>
 313         * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
 314         2003-12-29  DJ Delorie  <dj@redhat.com>
 315         * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
 316         sh_opcode_info, sh_table): Add sh2a support.
 317         (arch_op32): New, to tag 32-bit opcodes.
 318         * sh-dis.c (print_insn_sh): Support sh2a opcodes.
 319         2003-12-02  Michael Snyder  <msnyder@redhat.com>
 320         * sh-opc.h (arch_sh2a): Add.
 321         * sh-dis.c (arch_sh2a): Handle.
 322         * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
 323
 324 2004-07-27  Tomer Levi  <Tomer.Levi@nsc.com>
 325
 326         * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
 327
 328 2004-07-22  Nick Clifton  <nickc@redhat.com>
 329
 330         PR/280
 331         * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
 332         insns - this is done by objdump itself.
 333         * h8500-dis.c (print_insn_h8500): Likewise.
 334
 335 2004-07-21  Jan Beulich <jbeulich@novell.com>
 336
 337         * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
 338         regardless of address size prefix in effect.
 339         (ptr_reg): Size or address registers does not depend on rex64, but
 340         on the presence of an address size override.
 341         (OP_MMX): Use rex.x only for xmm registers.
 342         (OP_EM): Use rex.z only for xmm registers.
 343
 344 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 345
 346         * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
 347         move/branch operations to the bottom so that VR5400 multimedia
 348         instructions take precedence in disassembly.
 349
 350 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 351
 352         * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
 353         ISA-specific "break" encoding.
 354
 355 2004-07-13  Elvis Chiang  <elvisfb@gmail.com>
 356
 357         * arm-opc.h: Fix typo in comment.
 358
 359 2004-07-11  Andreas Schwab  <schwab@suse.de>
 360
 361         * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
 362
 363 2004-07-09  Andreas Schwab  <schwab@suse.de>
 364
 365         * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
 366
 367 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 368
 369         * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
 370         (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
 371         (crx-dis.lo): New target.
 372         (crx-opc.lo): Likewise.
 373         * Makefile.in: Regenerate.
 374         * configure.in: Handle bfd_crx_arch.
 375         * configure: Regenerate.
 376         * crx-dis.c: New file.
 377         * crx-opc.c: New file.
 378         * disassemble.c (ARCH_crx): Define.
 379         (disassembler): Handle ARCH_crx.
 380
 381 2004-06-29  James E Wilson  <wilson@specifixinc.com>
 382
 383         * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
 384         * ia64-asmtab.c: Regnerate.
 385
 386 2004-06-28  Alan Modra  <amodra@bigpond.net.au>
 387
 388         * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
 389         (extract_fxm): Don't test dialect.
 390         (XFXFXM_MASK): Include the power4 bit.
 391         (XFXM): Add p4 param.
 392         (powerpc_opcodes): Add mfocrf and mtocrf.  Adjust mtcr.
 393
 394 2004-06-27  Alexandre Oliva  <aoliva@redhat.com>
 395
 396         2003-07-21  Richard Sandiford  <rsandifo@redhat.com>
 397         * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
 398
 399 2004-06-26  Alan Modra  <amodra@bigpond.net.au>
 400
 401         * ppc-opc.c (BH, XLBH_MASK): Define.
 402         (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
 403
 404 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 405
 406         * i386-dis.c (x_mode): Comment.
 407         (two_source_ops): File scope.
 408         (float_mem): Correct fisttpll and fistpll.
 409         (float_mem_mode): New table.
 410         (dofloat): Use it.
 411         (OP_E): Correct intel mode PTR output.
 412         (ptr_reg): Use open_char and close_char.
 413         (PNI_Fixup): Handle possible suffix on sidt.  Use op1out etc. for
 414         operands.  Set two_source_ops.
 415
 416 2004-06-15  Alan Modra  <amodra@bigpond.net.au>
 417
 418         * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
 419         instead of _raw_size.
 420
 421 2004-06-08  Jakub Jelinek  <jakub@redhat.com>
 422
 423         * ia64-gen.c (in_iclass): Handle more postinc st
 424         and ld variants.
 425         * ia64-asmtab.c: Rebuilt.
 426
 427 2004-06-01  Martin Schwidefsky  <schwidefsky@de.ibm.com>
 428
 429         * s390-opc.txt: Correct architecture mask for some opcodes.
 430         lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
 431         in the esa mode as well.
 432
 433 2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
 434
 435         * sh-dis.c (target_arch): Make unsigned.
 436         (print_insn_sh): Replace (most of) switch with a call to
 437         sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
 438         * sh-opc.h: Redefine architecture flags values.
 439         Add sh3-nommu architecture.
 440         Reorganise <arch>_up macros so they make more visual sense.
 441         (SH_MERGE_ARCH_SET): Define new macro.
 442         (SH_VALID_BASE_ARCH_SET): Likewise.
 443         (SH_VALID_MMU_ARCH_SET): Likewise.
 444         (SH_VALID_CO_ARCH_SET): Likewise.
 445         (SH_VALID_ARCH_SET): Likewise.
 446         (SH_MERGE_ARCH_SET_VALID): Likewise.
 447         (SH_ARCH_SET_HAS_FPU): Likewise.
 448         (SH_ARCH_SET_HAS_DSP): Likewise.
 449         (SH_ARCH_UNKNOWN_ARCH): Likewise.
 450         (sh_get_arch_from_bfd_mach): Add prototype.
 451         (sh_get_arch_up_from_bfd_mach): Likewise.
 452         (sh_get_bfd_mach_from_arch_set): Likewise.
 453         (sh_merge_bfd_arc): Likewise.
 454
 455 2004-05-24  Peter Barada  <peter@the-baradas.com>
 456
 457         * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
 458         into new match_insn_m68k function.  Loop over canidate
 459         matches and select first that completely matches.
 460         * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
 461         * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
 462         to verify addressing for MAC/EMAC.
 463         * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
 464         reigster halves since 'fpu' and 'spl' look misleading.
 465         * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
 466         * m68k-opc.c: Rearragne mac/emac cases to use longest for
 467         first, tighten up match masks.
 468         * m68k-opc.c: Add 'size' field to struct m68k_opcode.  Produce
 469         'size' from special case code in print_insn_m68k to
 470         determine decode size of insns.
 471
 472 2004-05-19  Alan Modra  <amodra@bigpond.net.au>
 473
 474         * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
 475         well as when -mpower4.
 476
 477 2004-05-13  Nick Clifton  <nickc@redhat.com>
 478
 479         * po/fr.po: Updated French translation.
 480
 481 2004-05-05  Peter Barada  <peter@the-baradas.com>
 482
 483         * m68k-dis.c(print_insn_m68k): Add new chips, use core
 484         variants in arch_mask.  Only set m68881/68851 for 68k chips.
 485         * m68k-op.c: Switch from ColdFire chips to core variants.
 486
 487 2004-05-05  Alan Modra  <amodra@bigpond.net.au>
 488
 489         PR 147.
 490         * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
 491
 492 2004-04-29  Ben Elliston  <bje@au.ibm.com>
 493
 494         * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
 495         (powerpc_opcodes): Add "dbczl" instruction for PPC970.
 496
 497 2004-04-22  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
 498
 499         * sh-dis.c (print_insn_sh): Print the value in constant pool
 500         as a symbol if it looks like a symbol.
 501
 502 2004-04-22  Peter Barada <peter@the-baradas.com>
 503
 504         * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
 505         appropriate ColdFire architectures.
 506         (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
 507         mask addressing.
 508         Add EMAC instructions, fix MAC instructions. Remove
 509         macmw/macml/msacmw/msacml instructions since mask addressing now
 510         supported.
 511
 512 2004-04-20  Jakub Jelinek  <jakub@redhat.com>
 513
 514         * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
 515         (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
 516         suffix.  Use fmov*x macros, create all 3 fpsize variants in one
 517         macro.  Adjust all users.
 518
 519 2004-04-15  Anil Paranjpe  <anilp1@kpitcummins.com>
 520
 521         * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
 522         separately.
 523
 524 2004-03-30  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 525
 526         * m32r-asm.c: Regenerate.
 527
 528 2004-03-29  Stan Shebs  <shebs@apple.com>
 529
 530         * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
 531         used.
 532
 533 2004-03-19  Alan Modra  <amodra@bigpond.net.au>
 534
 535         * aclocal.m4: Regenerate.
 536         * config.in: Regenerate.
 537         * configure: Regenerate.
 538         * po/POTFILES.in: Regenerate.
 539         * po/opcodes.pot: Regenerate.
 540
 541 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 542
 543         * ppc-dis.c (print_insn_powerpc): Don't print tabs.  Handle
 544         PPC_OPERANDS_GPR_0.
 545         * ppc-opc.c (RA0): Define.
 546         (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
 547         (RAOPT): Rename from RAO.  Update all uses.
 548         (powerpc_opcodes): Use RA0 as appropriate.
 549
 550 2004-03-15  Aldy Hernandez  <aldyh@redhat.com>
 551
 552         * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
 553
 554 2004-03-15  Alan Modra  <amodra@bigpond.net.au>
 555
 556         * sparc-dis.c (print_insn_sparc): Update getword prototype.
 557
 558 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 559
 560         * i386-dis.c (GRPPLOCK): Delete.
 561         (grps): Delete GRPPLOCK entry.
 562
 563 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 564
 565         * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
 566         (M, Mp): Use OP_M.
 567         (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
 568         (GRPPADLCK): Define.
 569         (dis386): Use NOP_Fixup on "nop".
 570         (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
 571         (twobyte_has_modrm): Set for 0xa7.
 572         (padlock_table): Delete.  Move to..
 573         (grps): ..here, using OP_0f07.  Use OP_Ofae on lfence, mfence
 574         and clflush.
 575         (print_insn): Revert PADLOCK_SPECIAL code.
 576         (OP_E): Delete sfence, lfence, mfence checks.
 577
 578 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 579
 580         * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
 581         (INVLPG_Fixup): New function.
 582         (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
 583
 584 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 585
 586         * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
 587         (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
 588         (padlock_table): New struct with PadLock instructions.
 589         (print_insn): Handle PADLOCK_SPECIAL.
 590
 591 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 592
 593         * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
 594         (OP_E): Twiddle clflush to sfence here.
 595
 596 2004-03-08  Nick Clifton  <nickc@redhat.com>
 597
 598         * po/de.po: Updated German translation.
 599
 600 2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
 601
 602         * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
 603         nofpu mode.  Add BFD type bfd_mach_sh4_nommu_nofpu.
 604         * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
 605         accordingly.
 606
 607 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 608
 609         * frv-asm.c: Regenerate.
 610         * frv-desc.c: Regenerate.
 611         * frv-desc.h: Regenerate.
 612         * frv-dis.c: Regenerate.
 613         * frv-ibld.c: Regenerate.
 614         * frv-opc.c: Regenerate.
 615         * frv-opc.h: Regenerate.
 616
 617 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 618
 619         * frv-desc.c, frv-opc.c: Regenerate.
 620
 621 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 622
 623         * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
 624
 625 2004-02-26  Andrew Stubbs  <andrew.stubbs@superh.com>
 626
 627         * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
 628         Also correct mistake in the comment.
 629
 630 2004-02-26  Andrew Stubbs <andrew.stubbs@superh.com>
 631
 632         * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
 633         ensure that double registers have even numbers.
 634         Add REG_N_B01 for nn01 (binary 01) nibble to ensure
 635         that reserved instruction 0xfffd does not decode the same
 636         as 0xfdfd (ftrv).
 637         * sh-opc.h: Add REG_N_D nibble type and use it whereever
 638         REG_N refers to a double register.
 639         Add REG_N_B01 nibble type and use it instead of REG_NM
 640         in ftrv.
 641         Adjust the bit patterns in a few comments.
 642
 643 2004-02-25  Aldy Hernandez  <aldyh@redhat.com>
 644
 645         * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
 646
 647 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 648
 649         * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
 650
 651 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 652
 653         * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
 654
 655 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 656
 657         * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
 658         mtivor32, mtivor33, mtivor34.
 659
 660 2004-02-19  Aldy Hernandez  <aldyh@redhat.com>
 661
 662         * ppc-opc.c (powerpc_opcodes): Add mfmcar.
 663
 664 2004-02-10  Petko Manolov  <petkan@nucleusys.com>
 665
 666         * arm-opc.h Maverick accumulator register opcode fixes.
 667
 668 2004-02-13  Ben Elliston  <bje@wasabisystems.com>
 669
 670         * m32r-dis.c: Regenerate.
 671
 672 2004-01-27  Michael Snyder  <msnyder@redhat.com>
 673
 674         * sh-opc.h (sh_table): "fsrra", not "fssra".
 675
 676 2004-01-23  Andrew Over <andrew.over@cs.anu.edu.au>
 677
 678         * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
 679         contraints.
 680
 681 2004-01-19  Andrew Over  <andrew.over@cs.anu.edu.au>
 682
 683         * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
 684
 685 2004-01-19  Alan Modra  <amodra@bigpond.net.au>
 686
 687         * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
 688         1.  Don't print scale factor on AT&T mode when index missing.
 689
 690 2004-01-16  Alexandre Oliva  <aoliva@redhat.com>
 691
 692         * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
 693         when loaded into XR registers.
 694
 695 2004-01-14  Richard Sandiford  <rsandifo@redhat.com>
 696
 697         * frv-desc.h: Regenerate.
 698         * frv-desc.c: Regenerate.
 699         * frv-opc.c: Regenerate.
 700
 701 2004-01-13  Michael Snyder  <msnyder@redhat.com>
 702
 703         * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
 704
 705 2004-01-09  Paul Brook  <paul@codesourcery.com>
 706
 707         * arm-opc.h (arm_opcodes): Move generic mcrr after known
 708         specific opcodes.
 709
 710 2004-01-07  Daniel Jacobowitz  <drow@mvista.com>
 711
 712         * Makefile.am (libopcodes_la_DEPENDENCIES)
 713         (libopcodes_la_LIBADD): Revert 2003-05-17 change.  Add explanatory
 714         comment about the problem.
 715         * Makefile.in: Regenerate.
 716
 717 2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
 718
 719         2003-12-19  Alexandre Oliva  <aoliva@redhat.com>
 720         * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
 721         cut&paste errors in shifting/truncating numerical operands.
 722         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 723         * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
 724         (parse_uslo16): Likewise.
 725         (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
 726         (parse_d12): Parse gotoff12 and gotofffuncdesc12.
 727         (parse_s12): Likewise.
 728         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 729         * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
 730         (parse_uslo16): Likewise.
 731         (parse_uhi16): Parse gothi and gotfuncdeschi.
 732         (parse_d12): Parse got12 and gotfuncdesc12.
 733         (parse_s12): Likewise.
 734
 735 2004-01-02  Albert Bartoszko  <albar@nt.kegel.com.pl>
 736
 737         * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
 738         instruction which looks similar to an 'rla' instruction.
 739
 740 For older changes see ChangeLog-0203
 741 \f
 742 Local Variables:
 743 mode: change-log
 744 left-margin: 8
 745 fill-column: 74
 746 version-control: never
 747 End: