opcodes/ChangeLog

   1 2019-12-11  Alan Modra  <amodra@gmail.com>
   2
   3         PR 25270
   4         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
   5         false when field is zero for sve_size_tsz_bhs.
   6
   7 2019-12-11  Alan Modra  <amodra@gmail.com>
   8
   9         * epiphany-ibld.c: Regenerate.
  10
  11 2019-12-10  Alan Modra  <amodra@gmail.com>
  12
  13         PR 24960
  14         * disassemble.c (disassemble_free_target): New function.
  15
  16 2019-12-10  Alan Modra  <amodra@gmail.com>
  17
  18         * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
  19         * disassemble.c (disassemble_init_for_target): Likewise.
  20         * bpf-dis.c: Regenerate.
  21         * epiphany-dis.c: Regenerate.
  22         * fr30-dis.c: Regenerate.
  23         * frv-dis.c: Regenerate.
  24         * ip2k-dis.c: Regenerate.
  25         * iq2000-dis.c: Regenerate.
  26         * lm32-dis.c: Regenerate.
  27         * m32c-dis.c: Regenerate.
  28         * m32r-dis.c: Regenerate.
  29         * mep-dis.c: Regenerate.
  30         * mt-dis.c: Regenerate.
  31         * or1k-dis.c: Regenerate.
  32         * xc16x-dis.c: Regenerate.
  33         * xstormy16-dis.c: Regenerate.
  34
  35 2019-12-10  Alan Modra  <amodra@gmail.com>
  36
  37         * ppc-dis.c (private): Delete variable.
  38         (get_powerpc_dialect): Don't segfault on NULL info->private_data.
  39         (powerpc_init_dialect): Don't use global private.
  40
  41 2019-12-10  Alan Modra  <amodra@gmail.com>
  42
  43         * s12z-opc.c: Formatting.
  44
  45 2019-12-08  Alan Modra  <amodra@gmail.com>
  46
  47         * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
  48         registers.
  49
  50 2019-12-05  Jan Beulich  <jbeulich@suse.com>
  51
  52         * aarch64-tbl.h (aarch64_feature_crypto,
  53         aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
  54         CRYPTO_V8_2_INSN): Delete.
  55
  56 2019-12-05  Alan Modra  <amodra@gmail.com>
  57
  58         PR 25249
  59         * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
  60         (struct string_buf): New.
  61         (strbuf): New function.
  62         (get_field): Use strbuf rather than strdup of local temp.
  63         (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
  64         (get_field_rfsl, get_field_imm15): Likewise.
  65         (get_field_rd, get_field_r1, get_field_r2): Update macros.
  66         (get_field_special): Likewise.  Don't strcpy spr.  Formatting.
  67         (print_insn_microblaze): Formatting.  Init and pass string_buf to
  68         get_field functions.
  69
  70 2019-12-04  Jan Beulich  <jbeulich@suse.com>
  71
  72         * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
  73         * i386-tbl.h: Re-generate.
  74
  75 2019-12-04  Jan Beulich  <jbeulich@suse.com>
  76
  77         * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
  78
  79 2019-12-04  Jan Beulich  <jbeulich@suse.com>
  80
  81         * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
  82         forms.
  83         (xbegin): Drop DefaultSize.
  84         * i386-tbl.h: Re-generate.
  85
  86 2019-11-22  Mihail Ionescu  <mihail.ionescu@arm.com>
  87
  88         * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
  89         Change the coproc CRC conditions to use the extension
  90         feature set, second word, base on ARM_EXT2_CRC.
  91
  92 2019-11-14  Jan Beulich  <jbeulich@suse.com>
  93
  94         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
  95         * i386-tbl.h: Re-generate.
  96
  97 2019-11-14  Jan Beulich  <jbeulich@suse.com>
  98
  99         * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
 100         JumpInterSegment, and JumpAbsolute entries.
 101         * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
 102         JUMP_ABSOLUTE): Define.
 103         (struct i386_opcode_modifier): Extend jump field to 3 bits.
 104         Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
 105         fields.
 106         * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
 107         JumpInterSegment): Define.
 108         * i386-tbl.h: Re-generate.
 109
 110 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 111
 112         * i386-gen.c (operand_type_init): Remove
 113         OPERAND_TYPE_JUMPABSOLUTE entry.
 114         (opcode_modifiers): Add JumpAbsolute entry.
 115         (operand_types): Remove JumpAbsolute entry.
 116         * i386-opc.h (JumpAbsolute): Move between enums.
 117         (struct i386_opcode_modifier): Add jumpabsolute field.
 118         (union i386_operand_type): Remove jumpabsolute field.
 119         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
 120         * i386-init.h, i386-tbl.h: Re-generate.
 121
 122 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 123
 124         * i386-gen.c (opcode_modifiers): Add AnySize entry.
 125         (operand_types): Remove AnySize entry.
 126         * i386-opc.h (AnySize): Move between enums.
 127         (struct i386_opcode_modifier): Add anysize field.
 128         (OTUnused): Un-comment.
 129         (union i386_operand_type): Remove anysize field.
 130         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
 131         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
 132         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
 133         AnySize.
 134         * i386-tbl.h: Re-generate.
 135
 136 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
 137
 138         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
 139         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
 140         use the floating point register (FPR).
 141
 142 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
 143
 144         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
 145         cmode 1101.
 146         (is_mve_encoding_conflict): Update cmode conflict checks for
 147         MVE_VMVN_IMM.
 148
 149 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 150
 151         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
 152         entry.
 153         (operand_types): Remove EsSeg entry.
 154         (main): Replace stale use of OTMax.
 155         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
 156         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
 157         (EsSeg): Delete.
 158         (OTUnused): Comment out.
 159         (union i386_operand_type): Remove esseg field.
 160         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
 161         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
 162         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
 163         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
 164         * i386-init.h, i386-tbl.h: Re-generate.
 165
 166 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 167
 168         * i386-gen.c (operand_instances): Add RegB entry.
 169         * i386-opc.h (enum operand_instance): Add RegB.
 170         * i386-opc.tbl (RegC, RegD, RegB): Define.
 171         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
 172         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
 173         monitorx, mwaitx): Drop ImmExt and convert encodings
 174         accordingly.
 175         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
 176         (edx, rdx): Add Instance=RegD.
 177         (ebx, rbx): Add Instance=RegB.
 178         * i386-tbl.h: Re-generate.
 179
 180 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 181
 182         * i386-gen.c (operand_type_init): Adjust
 183         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
 184         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
 185         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
 186         (operand_instances): New.
 187         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
 188         (output_operand_type): New parameter "instance". Process it.
 189         (process_i386_operand_type): New local variable "instance".
 190         (main): Adjust static assertions.
 191         * i386-opc.h (INSTANCE_WIDTH): Define.
 192         (enum operand_instance): New.
 193         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
 194         (union i386_operand_type): Replace acc, inoutportreg, and
 195         shiftcount by instance.
 196         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
 197         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
 198         Add Instance=.
 199         * i386-init.h, i386-tbl.h: Re-generate.
 200
 201 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 202
 203         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
 204         smaxp/sminp entries' "tied_operand" field to 2.
 205
 206 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 207
 208         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 209         "index" local variable by that of the already existing "num".
 210
 211 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 212
 213         PR gas/25167
 214         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 215         * i386-tbl.h: Regenerated.
 216
 217 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 218
 219         * i386-gen.c (operand_type_init): Add Class= to
 220         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 221         OPERAND_TYPE_REGBND entry.
 222         (operand_classes): Add RegMask and RegBND entries.
 223         (operand_types): Drop RegMask and RegBND entry.
 224         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 225         (RegMask, RegBND): Delete.
 226         (union i386_operand_type): Remove regmask and regbnd fields.
 227         * i386-opc.tbl (RegMask, RegBND): Define.
 228         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 229         Class=RegBND.
 230         * i386-init.h, i386-tbl.h: Re-generate.
 231
 232 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 233
 234         * i386-gen.c (operand_type_init): Add Class= to
 235         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 236         OPERAND_TYPE_REGZMM entries.
 237         (operand_classes): Add RegMMX and RegSIMD entries.
 238         (operand_types): Drop RegMMX and RegSIMD entries.
 239         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 240         (RegMMX, RegSIMD): Delete.
 241         (union i386_operand_type): Remove regmmx and regsimd fields.
 242         * i386-opc.tbl (RegMMX): Define.
 243         (RegXMM, RegYMM, RegZMM): Add Class=.
 244         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 245         Class=RegSIMD.
 246         * i386-init.h, i386-tbl.h: Re-generate.
 247
 248 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 249
 250         * i386-gen.c (operand_type_init): Add Class= to
 251         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 252         entries.
 253         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 254         (operand_types): Drop Control, Debug, and Test entries.
 255         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 256         (Control, Debug, Test): Delete.
 257         (union i386_operand_type): Remove control, debug, and test
 258         fields.
 259         * i386-opc.tbl (Control, Debug, Test): Define.
 260         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 261         Class=RegDR, and Test by Class=RegTR.
 262         * i386-init.h, i386-tbl.h: Re-generate.
 263
 264 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 265
 266         * i386-gen.c (operand_type_init): Add Class= to
 267         OPERAND_TYPE_SREG entry.
 268         (operand_classes): Add SReg entry.
 269         (operand_types): Drop SReg entry.
 270         * i386-opc.h (enum operand_class): Add SReg.
 271         (SReg): Delete.
 272         (union i386_operand_type): Remove sreg field.
 273         * i386-opc.tbl (SReg): Define.
 274         * i386-reg.tbl: Replace SReg by Class=SReg.
 275         * i386-init.h, i386-tbl.h: Re-generate.
 276
 277 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 278
 279         * i386-gen.c (operand_type_init): Add Class=. New
 280         OPERAND_TYPE_ANYIMM entry.
 281         (operand_classes): New.
 282         (operand_types): Drop Reg entry.
 283         (output_operand_type): New parameter "class". Process it.
 284         (process_i386_operand_type): New local variable "class".
 285         (main): Adjust static assertions.
 286         * i386-opc.h (CLASS_WIDTH): Define.
 287         (enum operand_class): New.
 288         (Reg): Replace by Class. Adjust comment.
 289         (union i386_operand_type): Replace reg by class.
 290         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 291         Class=.
 292         * i386-reg.tbl: Replace Reg by Class=Reg.
 293         * i386-init.h: Re-generate.
 294
 295 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 296
 297         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 298         (aarch64_opcode_table): Add data gathering hint mnemonic.
 299         * opcodes/aarch64-dis-2.c: Account for new instruction.
 300
 301 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 302
 303         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 304
 305
 306 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 307
 308         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 309         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 310         aarch64_feature_f64mm): New feature sets.
 311         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 312         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 313         instructions.
 314         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 315         macros.
 316         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 317         (OP_SVE_QQQ): New qualifier.
 318         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 319         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 320         the movprfx constraint.
 321         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 322         (aarch64_opcode_table): Define new instructions smmla,
 323         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 324         uzip{1/2}, trn{1/2}.
 325         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 326         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 327         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 328         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 329         Account for new instructions.
 330         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 331         S4x32 operand.
 332         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 333
 334 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 335 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 336
 337         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 338         Armv8.6-A.
 339         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 340         (neon_opcodes): Add bfloat SIMD instructions.
 341         (print_insn_coprocessor): Add new control character %b to print
 342         condition code without checking cp_num.
 343         (print_insn_neon): Account for BFloat16 instructions that have no
 344         special top-byte handling.
 345
 346 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 347 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 348
 349         * arm-dis.c (print_insn_coprocessor,
 350         print_insn_generic_coprocessor): Create wrapper functions around
 351         the implementation of the print_insn_coprocessor control codes.
 352         (print_insn_coprocessor_1): Original print_insn_coprocessor
 353         function that now takes which array to look at as an argument.
 354         (print_insn_arm): Use both print_insn_coprocessor and
 355         print_insn_generic_coprocessor.
 356         (print_insn_thumb32): As above.
 357
 358 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 359 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 360
 361         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 362         in reglane special case.
 363         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 364         aarch64_find_next_opcode): Account for new instructions.
 365         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 366         in reglane special case.
 367         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 368         new AARCH64_OPND_QLF_S_2H qualifier.
 369         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 370         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 371         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 372         sets.
 373         (BFLOAT_SVE, BFLOAT): New feature set macros.
 374         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 375         instructions.
 376         (aarch64_opcode_table): Define new instructions bfdot,
 377         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 378         bfcvtn2, bfcvt.
 379
 380 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 381 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 382
 383         * aarch64-tbl.h (ARMV8_6): New macro.
 384
 385 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 386
 387         * i386-dis.c (prefix_table): Add mcommit.
 388         (rm_table): Add rdpru.
 389         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 390         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 391         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 392         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 393         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 394         * i386-opc.tbl (mcommit, rdpru): New.
 395         * i386-init.h, i386-tbl.h: Re-generate.
 396
 397 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 398
 399         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 400         "names32" instead.
 401         (OP_Monitor): Drop local variable "op1_names", re-purpose
 402         "names" for it instead, and replace former "names" uses by
 403         "names32" ones.
 404
 405 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 406
 407         PR/gas 25167
 408         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 409         operand-less forms.
 410         * opcodes/i386-tbl.h: Re-generate.
 411
 412 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 413
 414         * i386-dis.c (OP_Mwaitx): Delete.
 415         (prefix_table): Use OP_Mwait for mwaitx entry.
 416         (OP_Mwait): Also handle mwaitx.
 417
 418 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 419
 420         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 421         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 422         (prefix_table): Add respective entries.
 423         (rm_table): Link to those entries.
 424
 425 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 426
 427         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 428         (REG_0F1C_P_0_MOD_0): ... this.
 429         (REG_0F1E_MOD_3): Rename to ...
 430         (REG_0F1E_P_1_MOD_3): ... this.
 431         (RM_0F01_REG_5): Rename to ...
 432         (RM_0F01_REG_5_MOD_3): ... this.
 433         (RM_0F01_REG_7): Rename to ...
 434         (RM_0F01_REG_7_MOD_3): ... this.
 435         (RM_0F1E_MOD_3_REG_7): Rename to ...
 436         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 437         (RM_0FAE_REG_6): Rename to ...
 438         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 439         (RM_0FAE_REG_7): Rename to ...
 440         (RM_0FAE_REG_7_MOD_3): ... this.
 441         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 442         (PREFIX_0F01_REG_5_MOD_0): ... this.
 443         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 444         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 445         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 446         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 447         (PREFIX_0FAE_REG_0): Rename to ...
 448         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 449         (PREFIX_0FAE_REG_1): Rename to ...
 450         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 451         (PREFIX_0FAE_REG_2): Rename to ...
 452         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 453         (PREFIX_0FAE_REG_3): Rename to ...
 454         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 455         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 456         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 457         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 458         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 459         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 460         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 461         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 462         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 463         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 464         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 465         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 466         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 467         (PREFIX_0FAE_REG_7): Rename to ...
 468         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 469         (PREFIX_MOD_0_0FC3): Rename to ...
 470         (PREFIX_0FC3_MOD_0): ... this.
 471         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 472         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 473         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 474         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 475         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 476         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 477         (reg_table, prefix_table, mod_table, rm_table): Adjust
 478         accordingly.
 479
 480 2019-11-04  Nick Clifton  <nickc@redhat.com>
 481
 482         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 483         of a v850 system register.  Move the v850_sreg_names array into
 484         this function.
 485         (get_v850_reg_name): Likewise for ordinary register names.
 486         (get_v850_vreg_name): Likewise for vector register names.
 487         (get_v850_cc_name): Likewise for condition codes.
 488         * get_v850_float_cc_name): Likewise for floating point condition
 489         codes.
 490         (get_v850_cacheop_name): Likewise for cache-ops.
 491         (get_v850_prefop_name): Likewise for pref-ops.
 492         (disassemble): Use the new accessor functions.
 493
 494 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 495
 496         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 497         immediate for the writeback form of ldraa/ldrab if it is 0.
 498         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 499         * aarch64-opc-2.c: Regenerated.
 500
 501 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 502
 503         * i386-gen.c (operand_type_shorthands): Delete.
 504         (operand_type_init): Expand previous shorthands.
 505         (set_bitfield_from_shorthand): Rename back to ...
 506         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 507         of operand_type_init[].
 508         (set_bitfield): Adjust call to the above function.
 509         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 510         RegXMM, RegYMM, RegZMM): Define.
 511         * i386-reg.tbl: Expand prior shorthands.
 512
 513 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 514
 515         * i386-gen.c (output_i386_opcode): Change order of fields
 516         emitted to output.
 517         * i386-opc.h (struct insn_template): Move operands field.
 518         Convert extension_opcode field to unsigned short.
 519         * i386-tbl.h: Re-generate.
 520
 521 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 522
 523         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 524         of W.
 525         * i386-opc.h (W): Extend comment.
 526         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 527         general purpose variants not allowing for byte operands.
 528         * i386-tbl.h: Re-generate.
 529
 530 2019-10-29  Nick Clifton  <nickc@redhat.com>
 531
 532         * tic30-dis.c (print_branch): Correct size of operand array.
 533
 534 2019-10-29  Nick Clifton  <nickc@redhat.com>
 535
 536         * d30v-dis.c (print_insn): Check that operand index is valid
 537         before attempting to access the operands array.
 538
 539 2019-10-29  Nick Clifton  <nickc@redhat.com>
 540
 541         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 542         locating the bit to be tested.
 543
 544 2019-10-29  Nick Clifton  <nickc@redhat.com>
 545
 546         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 547         values.
 548         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 549         (print_insn_s12z):  Check for illegal size values.
 550
 551 2019-10-28  Nick Clifton  <nickc@redhat.com>
 552
 553         * csky-dis.c (csky_chars_to_number): Check for a negative
 554         count. Use an unsigned integer to construct the return value.
 555
 556 2019-10-28  Nick Clifton  <nickc@redhat.com>
 557
 558         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 559         operand buffer.  Set value to 15 not 13.
 560         (get_register_operand): Use OPERAND_BUFFER_LEN.
 561         (get_indirect_operand): Likewise.
 562         (print_two_operand): Likewise.
 563         (print_three_operand): Likewise.
 564         (print_oar_insn): Likewise.
 565
 566 2019-10-28  Nick Clifton  <nickc@redhat.com>
 567
 568         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 569         (bit_extract_simple): Likewise.
 570         (bit_copy): Likewise.
 571         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 572         index_offset array are not accessed.
 573
 574 2019-10-28  Nick Clifton  <nickc@redhat.com>
 575
 576         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 577         operand.
 578
 579 2019-10-25  Nick Clifton  <nickc@redhat.com>
 580
 581         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 582         access to opcodes.op array element.
 583
 584 2019-10-23  Nick Clifton  <nickc@redhat.com>
 585
 586         * rx-dis.c (get_register_name): Fix spelling typo in error
 587         message.
 588         (get_condition_name, get_flag_name, get_double_register_name)
 589         (get_double_register_high_name, get_double_register_low_name)
 590         (get_double_control_register_name, get_double_condition_name)
 591         (get_opsize_name, get_size_name): Likewise.
 592
 593 2019-10-22  Nick Clifton  <nickc@redhat.com>
 594
 595         * rx-dis.c (get_size_name): New function.  Provides safe
 596         access to name array.
 597         (get_opsize_name): Likewise.
 598         (print_insn_rx): Use the accessor functions.
 599
 600 2019-10-16  Nick Clifton  <nickc@redhat.com>
 601
 602         * rx-dis.c (get_register_name): New function.  Provides safe
 603         access to name array.
 604         (get_condition_name, get_flag_name, get_double_register_name)
 605         (get_double_register_high_name, get_double_register_low_name)
 606         (get_double_control_register_name, get_double_condition_name):
 607         Likewise.
 608         (print_insn_rx): Use the accessor functions.
 609
 610 2019-10-09  Nick Clifton  <nickc@redhat.com>
 611
 612         PR 25041
 613         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 614         instructions.
 615
 616 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 617
 618         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 619         (cmpsd): Likewise. Move EsSeg to other operand.
 620         * opcodes/i386-tbl.h: Re-generate.
 621
 622 2019-09-23  Alan Modra  <amodra@gmail.com>
 623
 624         * m68k-dis.c: Include cpu-m68k.h
 625
 626 2019-09-23  Alan Modra  <amodra@gmail.com>
 627
 628         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 629         "elf/mips.h" earlier.
 630
 631 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 632
 633         PR gas/25012
 634         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 635         with SReg operand.
 636         * i386-tbl.h: Re-generate.
 637
 638 2019-09-18  Alan Modra  <amodra@gmail.com>
 639
 640         * arc-ext.c: Update throughout for bfd section macro changes.
 641
 642 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 643
 644         * Makefile.in: Re-generate.
 645         * configure: Re-generate.
 646
 647 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 648
 649         * riscv-opc.c (riscv_opcodes): Change subset field
 650         to insn_class field for all instructions.
 651         (riscv_insn_types): Likewise.
 652
 653 2019-09-16  Phil Blundell  <pb@pbcl.net>
 654
 655         * configure: Regenerated.
 656
 657 2019-09-10  Miod Vallat  <miod@online.fr>
 658
 659         PR 24982
 660         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 661
 662 2019-09-09  Phil Blundell  <pb@pbcl.net>
 663
 664         binutils 2.33 branch created.
 665
 666 2019-09-03  Nick Clifton  <nickc@redhat.com>
 667
 668         PR 24961
 669         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 670         greater than zero before indexing via (bufcnt -1).
 671
 672 2019-09-03  Nick Clifton  <nickc@redhat.com>
 673
 674         PR 24958
 675         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 676         (MAX_SPEC_REG_NAME_LEN): Define.
 677         (struct mmix_dis_info): Use defined constants for array lengths.
 678         (get_reg_name): New function.
 679         (get_sprec_reg_name): New function.
 680         (print_insn_mmix): Use new functions.
 681
 682 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 683
 684         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 685         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 686         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 687
 688 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 689
 690         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 691         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 692         (aarch64_sys_reg_supported_p): Update checks for the above.
 693
 694 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 695
 696         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 697         cases MVE_SQRSHRL and MVE_UQRSHLL.
 698         (print_insn_mve): Add case for specifier 'k' to check
 699         specific bit of the instruction.
 700
 701 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 702
 703         PR 24854
 704         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 705         encountering an unknown machine type.
 706         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 707         cases return -1 rather than calling abort.
 708
 709 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 710
 711         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 712         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 713         IgnoreSize.
 714         * i386-tbl.h: Re-generate.
 715
 716 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 717
 718         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 719         instructions.
 720
 721 2019-07-30  Mel Chen <mel.chen@sifive.com>
 722
 723         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 724         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 725
 726         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 727         fscsr.
 728
 729 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 730
 731         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 732         and MPY class instructions.
 733         (parse_option): Add nps400 option.
 734         (print_arc_disassembler_options): Add nps400 info.
 735
 736 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 737
 738         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 739         (bspop): Likewise.
 740         (modapp): Likewise.
 741         * arc-opc.c (RAD_CHK): Add.
 742         * arc-tbl.h: Regenerate.
 743
 744 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 745
 746         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 747         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 748
 749 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 750
 751         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 752         instructions as UNPREDICTABLE.
 753
 754 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 755
 756         * bpf-desc.c: Regenerated.
 757
 758 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 759
 760         * i386-gen.c (static_assert): Define.
 761         (main): Use it.
 762         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 763         (Opcode_Modifier_Num): ... this.
 764         (Mem): Delete.
 765
 766 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 767
 768         * i386-gen.c (operand_types): Move RegMem ...
 769         (opcode_modifiers): ... here.
 770         * i386-opc.h (RegMem): Move to opcode modifer enum.
 771         (union i386_operand_type): Move regmem field ...
 772         (struct i386_opcode_modifier): ... here.
 773         * i386-opc.tbl (RegMem): Define.
 774         (mov, movq): Move RegMem on segment, control, debug, and test
 775         register flavors.
 776         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 777         to non-SSE2AVX flavor.
 778         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 779         Move RegMem on register only flavors. Drop IgnoreSize from
 780         legacy encoding flavors.
 781         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 782         flavors.
 783         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 784         register only flavors.
 785         (vmovd): Move RegMem and drop IgnoreSize on register only
 786         flavor. Change opcode and operand order to store form.
 787         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 788
 789 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 790
 791         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 792         entries.
 793         * i386-opc.h (SReg2, SReg3): Replace by ...
 794         (SReg): ... this.
 795         (union i386_operand_type): Replace sreg fields.
 796         * i386-opc.tbl (mov, ): Use SReg.
 797         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 798         register flavors.
 799         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 800         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 801
 802 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 803
 804         * bpf-desc.c: Regenerate.
 805         * bpf-opc.c: Likewise.
 806         * bpf-opc.h: Likewise.
 807
 808 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 809
 810         * bpf-desc.c: Regenerate.
 811         * bpf-opc.c: Likewise.
 812
 813 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 814
 815         * arm-dis.c (print_insn_coprocessor): Rename index to
 816         index_operand.
 817
 818 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 819
 820         * riscv-opc.c (riscv_insn_types): Add r4 type.
 821
 822         * riscv-opc.c (riscv_insn_types): Add b and j type.
 823
 824         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 825         format for sb type and correct s type.
 826
 827 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 828
 829         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 830         SVE FMOV alias of FCPY.
 831
 832 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 833
 834         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 835         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 836
 837 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 838
 839         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 840         registers in an instruction prefixed by MOVPRFX.
 841
 842 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 843
 844         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 845         sve_size_13 icode to account for variant behaviour of
 846         pmull{t,b}.
 847         * aarch64-dis-2.c: Regenerate.
 848         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 849         sve_size_13 icode to account for variant behaviour of
 850         pmull{t,b}.
 851         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 852         (OP_SVE_VVV_Q_D): Add new qualifier.
 853         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 854         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 855         AES and those not.
 856
 857 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 858
 859         * opcodes/i386-gen.c (operand_type_init): Remove
 860         OPERAND_TYPE_VEC_IMM4 entry.
 861         (operand_types): Remove Vec_Imm4.
 862         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 863         (union i386_operand_type): Remove vec_imm4.
 864         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 865         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 866
 867 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 868
 869         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 870         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 871         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 872         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 873         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 874         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 875         * i386-tbl.h: Re-generate.
 876
 877 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 878
 879         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 880         register operands.
 881         * i386-tbl.h: Re-generate.
 882
 883 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 884
 885         * i386-opc.tbl (C): New.
 886         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 887         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 888         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 889         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 890         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 891         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 892         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 893         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 894         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 895         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 896         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 897         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 898         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 899         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 900         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 901         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 902         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 903         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 904         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 905         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 906         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 907         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 908         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 909         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 910         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 911         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 912         flavors.
 913         * i386-tbl.h: Re-generate.
 914
 915 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 916
 917         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 918         register operands.
 919         * i386-tbl.h: Re-generate.
 920
 921 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 922
 923         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 924         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 925         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 926         * i386-tbl.h: Re-generate.
 927
 928 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 929
 930         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 931         Disp8MemShift from register only templates.
 932         * i386-tbl.h: Re-generate.
 933
 934 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 935
 936         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 937         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 938         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 939         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 940         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 941         EVEX_W_0F11_P_3_M_1): Delete.
 942         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 943         EVEX_W_0F11_P_3): New.
 944         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 945         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 946         MOD_EVEX_0F11_PREFIX_3 table entries.
 947         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 948         PREFIX_EVEX_0F11 table entries.
 949         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 950         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 951         EVEX_W_0F11_P_3_M_{0,1} table entries.
 952
 953 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 954
 955         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 956         Delete.
 957
 958 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 959
 960         PR binutils/24719
 961         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 962         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 963         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 964         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 965         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 966         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 967         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 968         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 969         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 970         PREFIX_EVEX_0F38C6_REG_6 entries.
 971         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 972         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 973         EVEX_W_0F38C7_R_6_P_2 entries.
 974         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 975         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 976         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 977         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 978         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 979         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 980         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 981
 982 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 983
 984         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 985         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 986         VEX_LEN_0F2D_P_3): Delete.
 987         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 988         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 989         (prefix_table): ... here.
 990
 991 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 992
 993         * i386-dis.c (Iq): Delete.
 994         (Id): New.
 995         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 996         TBM insns.
 997         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 998         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 999         (OP_E_memory): Also honor needindex when deciding whether an
1000         address size prefix needs printing.
1001         (OP_I): Remove handling of q_mode. Add handling of d_mode.
1002
1003 2019-06-26  Jim Wilson  <jimw@sifive.com>
1004
1005         PR binutils/24739
1006         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1007         Set info->display_endian to info->endian_code.
1008
1009 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1010
1011         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1012         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1013         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1014         OPERAND_TYPE_ACC64 entries.
1015         * i386-init.h: Re-generate.
1016
1017 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1018
1019         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1020         Delete.
1021         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1022         of dqa_mode.
1023         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1024         entries here.
1025         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1026         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1027
1028 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1029
1030         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1031         variables.
1032
1033 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1034
1035         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1036         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1037         movnti.
1038         * i386-opc.tbl (movnti): Add IgnoreSize.
1039         * i386-tbl.h: Re-generate.
1040
1041 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1042
1043         * i386-opc.tbl (and): Mark Imm8S form for optimization.
1044         * i386-tbl.h: Re-generate.
1045
1046 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
1047
1048         * i386-dis-evex.h: Break into ...
1049         * i386-dis-evex-len.h: New file.
1050         * i386-dis-evex-mod.h: Likewise.
1051         * i386-dis-evex-prefix.h: Likewise.
1052         * i386-dis-evex-reg.h: Likewise.
1053         * i386-dis-evex-w.h: Likewise.
1054         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1055         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1056         i386-dis-evex-mod.h.
1057
1058 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
1059
1060         PR binutils/24700
1061         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1062         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1063         EVEX_W_0F385B_P_2.
1064         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1065         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1066         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1067         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1068         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1069         EVEX_LEN_0F385B_P_2_W_1.
1070         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1071         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1072         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1073         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1074         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1075         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1076         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1077         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1078         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1079         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1080
1081 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
1082
1083         PR binutils/24691
1084         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1085         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1086         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1087         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1088         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1089         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1090         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1091         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1092         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1093         EVEX_LEN_0F3A43_P_2_W_1.
1094         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1095         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1096         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1097         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1098         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1099         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1100         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1101         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1102         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1103         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1104         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1105         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1106
1107 2019-06-14  Nick Clifton  <nickc@redhat.com>
1108
1109         * po/fr.po; Updated French translation.
1110
1111 2019-06-13  Stafford Horne  <shorne@gmail.com>
1112
1113         * or1k-asm.c: Regenerated.
1114         * or1k-desc.c: Regenerated.
1115         * or1k-desc.h: Regenerated.
1116         * or1k-dis.c: Regenerated.
1117         * or1k-ibld.c: Regenerated.
1118         * or1k-opc.c: Regenerated.
1119         * or1k-opc.h: Regenerated.
1120         * or1k-opinst.c: Regenerated.
1121
1122 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1123
1124         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1125
1126 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1127
1128         PR binutils/24633
1129         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1130         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1131         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1132         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1133         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1134         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1135         EVEX_LEN_0F3A1B_P_2_W_1.
1136         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1137         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1138         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1139         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1140         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1141         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1142         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1143         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1144
1145 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1146
1147         PR binutils/24626
1148         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1149         EVEX.vvvv when disassembling VEX and EVEX instructions.
1150         (OP_VEX): Set vex.register_specifier to 0 after readding
1151         vex.register_specifier.
1152         (OP_Vex_2src_1): Likewise.
1153         (OP_Vex_2src_2): Likewise.
1154         (OP_LWP_E): Likewise.
1155         (OP_EX_Vex): Don't check vex.register_specifier.
1156         (OP_XMM_Vex): Likewise.
1157
1158 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1159             Lili Cui  <lili.cui@intel.com>
1160
1161         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1162         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1163         instructions.
1164         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1165         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1166         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1167         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1168         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1169         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1170         * i386-init.h: Regenerated.
1171         * i386-tbl.h: Likewise.
1172
1173 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1174             Lili Cui  <lili.cui@intel.com>
1175
1176         * doc/c-i386.texi: Document enqcmd.
1177         * testsuite/gas/i386/enqcmd-intel.d: New file.
1178         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1179         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1180         * testsuite/gas/i386/enqcmd.d: Likewise.
1181         * testsuite/gas/i386/enqcmd.s: Likewise.
1182         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1183         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1184         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1185         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1186         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1187         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1188         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1189         and x86-64-enqcmd.
1190
1191 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1192
1193         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1194
1195 2019-06-03  Alan Modra  <amodra@gmail.com>
1196
1197         * ppc-dis.c (prefix_opcd_indices): Correct size.
1198
1199 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1200
1201         PR gas/24625
1202         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1203         Disp8ShiftVL.
1204         * i386-tbl.h: Regenerated.
1205
1206 2019-05-24  Alan Modra  <amodra@gmail.com>
1207
1208         * po/POTFILES.in: Regenerate.
1209
1210 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1211             Alan Modra  <amodra@gmail.com>
1212
1213         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1214         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1215         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1216         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1217         XTOP>): Define and add entries.
1218         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1219         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1220         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1221         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1222
1223 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1224             Alan Modra  <amodra@gmail.com>
1225
1226         * ppc-dis.c (ppc_opts): Add "future" entry.
1227         (PREFIX_OPCD_SEGS): Define.
1228         (prefix_opcd_indices): New array.
1229         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1230         (lookup_prefix): New function.
1231         (print_insn_powerpc): Handle 64-bit prefix instructions.
1232         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1233         (PMRR, POWERXX): Define.
1234         (prefix_opcodes): New instruction table.
1235         (prefix_num_opcodes): New constant.
1236
1237 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1238
1239         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1240         * configure: Regenerated.
1241         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1242         and cpu/bpf.opc.
1243         (HFILES): Add bpf-desc.h and bpf-opc.h.
1244         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1245         bpf-ibld.c and bpf-opc.c.
1246         (BPF_DEPS): Define.
1247         * Makefile.in: Regenerated.
1248         * disassemble.c (ARCH_bpf): Define.
1249         (disassembler): Add case for bfd_arch_bpf.
1250         (disassemble_init_for_target): Likewise.
1251         (enum epbf_isa_attr): Define.
1252         * disassemble.h: extern print_insn_bpf.
1253         * bpf-asm.c: Generated.
1254         * bpf-opc.h: Likewise.
1255         * bpf-opc.c: Likewise.
1256         * bpf-ibld.c: Likewise.
1257         * bpf-dis.c: Likewise.
1258         * bpf-desc.h: Likewise.
1259         * bpf-desc.c: Likewise.
1260
1261 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1262
1263         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1264         and VMSR with the new operands.
1265
1266 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1267
1268         * arm-dis.c (enum mve_instructions): New enum
1269         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1270         and cneg.
1271         (mve_opcodes): New instructions as above.
1272         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1273         csneg and csel.
1274         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1275
1276 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1277
1278         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1279         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1280         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1281         uqshl, urshrl and urshr.
1282         (is_mve_okay_in_it): Add new instructions to TRUE list.
1283         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1284         (print_insn_mve): Updated to accept new %j,
1285         %<bitfield>m and %<bitfield>n patterns.
1286
1287 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1288
1289         * mips-opc.c (mips_builtin_opcodes): Change source register
1290         constraint for DAUI.
1291
1292 2019-05-20  Nick Clifton  <nickc@redhat.com>
1293
1294         * po/fr.po: Updated French translation.
1295
1296 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1297             Michael Collison <michael.collison@arm.com>
1298
1299         * arm-dis.c (thumb32_opcodes): Add new instructions.
1300         (enum mve_instructions): Likewise.
1301         (enum mve_undefined): Add new reasons.
1302         (is_mve_encoding_conflict): Handle new instructions.
1303         (is_mve_undefined): Likewise.
1304         (is_mve_unpredictable): Likewise.
1305         (print_mve_undefined): Likewise.
1306         (print_mve_size): Likewise.
1307
1308 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1309             Michael Collison <michael.collison@arm.com>
1310
1311         * arm-dis.c (thumb32_opcodes): Add new instructions.
1312         (enum mve_instructions): Likewise.
1313         (is_mve_encoding_conflict): Handle new instructions.
1314         (is_mve_undefined): Likewise.
1315         (is_mve_unpredictable): Likewise.
1316         (print_mve_size): Likewise.
1317
1318 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1319             Michael Collison <michael.collison@arm.com>
1320
1321         * arm-dis.c (thumb32_opcodes): Add new instructions.
1322         (enum mve_instructions): Likewise.
1323         (is_mve_encoding_conflict): Likewise.
1324         (is_mve_unpredictable): Likewise.
1325         (print_mve_size): Likewise.
1326
1327 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1328             Michael Collison <michael.collison@arm.com>
1329
1330         * arm-dis.c (thumb32_opcodes): Add new instructions.
1331         (enum mve_instructions): Likewise.
1332         (is_mve_encoding_conflict): Handle new instructions.
1333         (is_mve_undefined): Likewise.
1334         (is_mve_unpredictable): Likewise.
1335         (print_mve_size): Likewise.
1336
1337 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1338             Michael Collison <michael.collison@arm.com>
1339
1340         * arm-dis.c (thumb32_opcodes): Add new instructions.
1341         (enum mve_instructions): Likewise.
1342         (is_mve_encoding_conflict): Handle new instructions.
1343         (is_mve_undefined): Likewise.
1344         (is_mve_unpredictable): Likewise.
1345         (print_mve_size): Likewise.
1346         (print_insn_mve): Likewise.
1347
1348 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1349             Michael Collison <michael.collison@arm.com>
1350
1351         * arm-dis.c (thumb32_opcodes): Add new instructions.
1352         (print_insn_thumb32): Handle new instructions.
1353
1354 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1355             Michael Collison <michael.collison@arm.com>
1356
1357         * arm-dis.c (enum mve_instructions): Add new instructions.
1358         (enum mve_undefined): Add new reasons.
1359         (is_mve_encoding_conflict): Handle new instructions.
1360         (is_mve_undefined): Likewise.
1361         (is_mve_unpredictable): Likewise.
1362         (print_mve_undefined): Likewise.
1363         (print_mve_size): Likewise.
1364         (print_mve_shift_n): Likewise.
1365         (print_insn_mve): Likewise.
1366
1367 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1368             Michael Collison <michael.collison@arm.com>
1369
1370         * arm-dis.c (enum mve_instructions): Add new instructions.
1371         (is_mve_encoding_conflict): Handle new instructions.
1372         (is_mve_unpredictable): Likewise.
1373         (print_mve_rotate): Likewise.
1374         (print_mve_size): Likewise.
1375         (print_insn_mve): Likewise.
1376
1377 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1378             Michael Collison <michael.collison@arm.com>
1379
1380         * arm-dis.c (enum mve_instructions): Add new instructions.
1381         (is_mve_encoding_conflict): Handle new instructions.
1382         (is_mve_unpredictable): Likewise.
1383         (print_mve_size): Likewise.
1384         (print_insn_mve): Likewise.
1385
1386 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1387             Michael Collison <michael.collison@arm.com>
1388
1389         * arm-dis.c (enum mve_instructions): Add new instructions.
1390         (enum mve_undefined): Add new reasons.
1391         (is_mve_encoding_conflict): Handle new instructions.
1392         (is_mve_undefined): Likewise.
1393         (is_mve_unpredictable): Likewise.
1394         (print_mve_undefined): Likewise.
1395         (print_mve_size): Likewise.
1396         (print_insn_mve): Likewise.
1397
1398 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1399             Michael Collison <michael.collison@arm.com>
1400
1401         * arm-dis.c (enum mve_instructions): Add new instructions.
1402         (is_mve_encoding_conflict): Handle new instructions.
1403         (is_mve_undefined): Likewise.
1404         (is_mve_unpredictable): Likewise.
1405         (print_mve_size): Likewise.
1406         (print_insn_mve): Likewise.
1407
1408 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1409             Michael Collison <michael.collison@arm.com>
1410
1411         * arm-dis.c (enum mve_instructions): Add new instructions.
1412         (enum mve_unpredictable): Add new reasons.
1413         (enum mve_undefined): Likewise.
1414         (is_mve_okay_in_it): Handle new isntructions.
1415         (is_mve_encoding_conflict): Likewise.
1416         (is_mve_undefined): Likewise.
1417         (is_mve_unpredictable): Likewise.
1418         (print_mve_vmov_index): Likewise.
1419         (print_simd_imm8): Likewise.
1420         (print_mve_undefined): Likewise.
1421         (print_mve_unpredictable): Likewise.
1422         (print_mve_size): Likewise.
1423         (print_insn_mve): Likewise.
1424
1425 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1426             Michael Collison <michael.collison@arm.com>
1427
1428         * arm-dis.c (enum mve_instructions): Add new instructions.
1429         (enum mve_unpredictable): Add new reasons.
1430         (enum mve_undefined): Likewise.
1431         (is_mve_encoding_conflict): Handle new instructions.
1432         (is_mve_undefined): Likewise.
1433         (is_mve_unpredictable): Likewise.
1434         (print_mve_undefined): Likewise.
1435         (print_mve_unpredictable): Likewise.
1436         (print_mve_rounding_mode): Likewise.
1437         (print_mve_vcvt_size): Likewise.
1438         (print_mve_size): Likewise.
1439         (print_insn_mve): Likewise.
1440
1441 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1442             Michael Collison <michael.collison@arm.com>
1443
1444         * arm-dis.c (enum mve_instructions): Add new instructions.
1445         (enum mve_unpredictable): Add new reasons.
1446         (enum mve_undefined): Likewise.
1447         (is_mve_undefined): Handle new instructions.
1448         (is_mve_unpredictable): Likewise.
1449         (print_mve_undefined): Likewise.
1450         (print_mve_unpredictable): Likewise.
1451         (print_mve_size): Likewise.
1452         (print_insn_mve): Likewise.
1453
1454 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1455             Michael Collison <michael.collison@arm.com>
1456
1457         * arm-dis.c (enum mve_instructions): Add new instructions.
1458         (enum mve_undefined): Add new reasons.
1459         (insns): Add new instructions.
1460         (is_mve_encoding_conflict):
1461         (print_mve_vld_str_addr): New print function.
1462         (is_mve_undefined): Handle new instructions.
1463         (is_mve_unpredictable): Likewise.
1464         (print_mve_undefined): Likewise.
1465         (print_mve_size): Likewise.
1466         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1467         (print_insn_mve):  Handle new operands.
1468
1469 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1470             Michael Collison <michael.collison@arm.com>
1471
1472         * arm-dis.c (enum mve_instructions): Add new instructions.
1473         (enum mve_unpredictable): Add new reasons.
1474         (is_mve_encoding_conflict): Handle new instructions.
1475         (is_mve_unpredictable): Likewise.
1476         (mve_opcodes): Add new instructions.
1477         (print_mve_unpredictable): Handle new reasons.
1478         (print_mve_register_blocks): New print function.
1479         (print_mve_size): Handle new instructions.
1480         (print_insn_mve): Likewise.
1481
1482 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1483             Michael Collison <michael.collison@arm.com>
1484
1485         * arm-dis.c (enum mve_instructions): Add new instructions.
1486         (enum mve_unpredictable): Add new reasons.
1487         (enum mve_undefined): Likewise.
1488         (is_mve_encoding_conflict): Handle new instructions.
1489         (is_mve_undefined): Likewise.
1490         (is_mve_unpredictable): Likewise.
1491         (coprocessor_opcodes): Move NEON VDUP from here...
1492         (neon_opcodes): ... to here.
1493         (mve_opcodes): Add new instructions.
1494         (print_mve_undefined):  Handle new reasons.
1495         (print_mve_unpredictable): Likewise.
1496         (print_mve_size): Handle new instructions.
1497         (print_insn_neon): Handle vdup.
1498         (print_insn_mve): Handle new operands.
1499
1500 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1501             Michael Collison <michael.collison@arm.com>
1502
1503         * arm-dis.c (enum mve_instructions): Add new instructions.
1504         (enum mve_unpredictable): Add new values.
1505         (mve_opcodes): Add new instructions.
1506         (vec_condnames): New array with vector conditions.
1507         (mve_predicatenames): New array with predicate suffixes.
1508         (mve_vec_sizename): New array with vector sizes.
1509         (enum vpt_pred_state): New enum with vector predication states.
1510         (struct vpt_block): New struct type for vpt blocks.
1511         (vpt_block_state): Global struct to keep track of state.
1512         (mve_extract_pred_mask): New helper function.
1513         (num_instructions_vpt_block): Likewise.
1514         (mark_outside_vpt_block): Likewise.
1515         (mark_inside_vpt_block): Likewise.
1516         (invert_next_predicate_state): Likewise.
1517         (update_next_predicate_state): Likewise.
1518         (update_vpt_block_state): Likewise.
1519         (is_vpt_instruction): Likewise.
1520         (is_mve_encoding_conflict): Add entries for new instructions.
1521         (is_mve_unpredictable): Likewise.
1522         (print_mve_unpredictable): Handle new cases.
1523         (print_instruction_predicate): Likewise.
1524         (print_mve_size): New function.
1525         (print_vec_condition): New function.
1526         (print_insn_mve): Handle vpt blocks and new print operands.
1527
1528 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1529
1530         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1531         8, 14 and 15 for Armv8.1-M Mainline.
1532
1533 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1534             Michael Collison <michael.collison@arm.com>
1535
1536         * arm-dis.c (enum mve_instructions): New enum.
1537         (enum mve_unpredictable): Likewise.
1538         (enum mve_undefined): Likewise.
1539         (struct mopcode32): New struct.
1540         (is_mve_okay_in_it): New function.
1541         (is_mve_architecture): Likewise.
1542         (arm_decode_field): Likewise.
1543         (arm_decode_field_multiple): Likewise.
1544         (is_mve_encoding_conflict): Likewise.
1545         (is_mve_undefined): Likewise.
1546         (is_mve_unpredictable): Likewise.
1547         (print_mve_undefined): Likewise.
1548         (print_mve_unpredictable): Likewise.
1549         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1550         (print_insn_mve): New function.
1551         (print_insn_thumb32): Handle MVE architecture.
1552         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1553
1554 2019-05-10  Nick Clifton  <nickc@redhat.com>
1555
1556         PR 24538
1557         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1558         end of the table prematurely.
1559
1560 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1561
1562         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1563         macros for R6.
1564
1565 2019-05-11  Alan Modra  <amodra@gmail.com>
1566
1567         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1568         when -Mraw is in effect.
1569
1570 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1571
1572         * aarch64-dis-2.c: Regenerate.
1573         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1574         (OP_SVE_BBB): New variant set.
1575         (OP_SVE_DDDD): New variant set.
1576         (OP_SVE_HHH): New variant set.
1577         (OP_SVE_HHHU): New variant set.
1578         (OP_SVE_SSS): New variant set.
1579         (OP_SVE_SSSU): New variant set.
1580         (OP_SVE_SHH): New variant set.
1581         (OP_SVE_SBBU): New variant set.
1582         (OP_SVE_DSS): New variant set.
1583         (OP_SVE_DHHU): New variant set.
1584         (OP_SVE_VMV_HSD_BHS): New variant set.
1585         (OP_SVE_VVU_HSD_BHS): New variant set.
1586         (OP_SVE_VVVU_SD_BH): New variant set.
1587         (OP_SVE_VVVU_BHSD): New variant set.
1588         (OP_SVE_VVV_QHD_DBS): New variant set.
1589         (OP_SVE_VVV_HSD_BHS): New variant set.
1590         (OP_SVE_VVV_HSD_BHS2): New variant set.
1591         (OP_SVE_VVV_BHS_HSD): New variant set.
1592         (OP_SVE_VV_BHS_HSD): New variant set.
1593         (OP_SVE_VVV_SD): New variant set.
1594         (OP_SVE_VVU_BHS_HSD): New variant set.
1595         (OP_SVE_VZVV_SD): New variant set.
1596         (OP_SVE_VZVV_BH): New variant set.
1597         (OP_SVE_VZV_SD): New variant set.
1598         (aarch64_opcode_table): Add sve2 instructions.
1599
1600 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1601
1602         * aarch64-asm-2.c: Regenerated.
1603         * aarch64-dis-2.c: Regenerated.
1604         * aarch64-opc-2.c: Regenerated.
1605         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1606         for SVE_SHLIMM_UNPRED_22.
1607         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1608         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1609         operand.
1610
1611 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1612
1613         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1614         sve_size_tsz_bhs iclass encode.
1615         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1616         sve_size_tsz_bhs iclass decode.
1617
1618 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1619
1620         * aarch64-asm-2.c: Regenerated.
1621         * aarch64-dis-2.c: Regenerated.
1622         * aarch64-opc-2.c: Regenerated.
1623         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1624         for SVE_Zm4_11_INDEX.
1625         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1626         (fields): Handle SVE_i2h field.
1627         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1628         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1629
1630 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1631
1632         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1633         sve_shift_tsz_bhsd iclass encode.
1634         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1635         sve_shift_tsz_bhsd iclass decode.
1636
1637 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1638
1639         * aarch64-asm-2.c: Regenerated.
1640         * aarch64-dis-2.c: Regenerated.
1641         * aarch64-opc-2.c: Regenerated.
1642         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1643         (aarch64_encode_variant_using_iclass): Handle
1644         sve_shift_tsz_hsd iclass encode.
1645         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1646         sve_shift_tsz_hsd iclass decode.
1647         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1648         for SVE_SHRIMM_UNPRED_22.
1649         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1650         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1651         operand.
1652
1653 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1654
1655         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1656         sve_size_013 iclass encode.
1657         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1658         sve_size_013 iclass decode.
1659
1660 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1661
1662         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1663         sve_size_bh iclass encode.
1664         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1665         sve_size_bh iclass decode.
1666
1667 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1668
1669         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1670         sve_size_sd2 iclass encode.
1671         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1672         sve_size_sd2 iclass decode.
1673         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1674         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1675
1676 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1677
1678         * aarch64-asm-2.c: Regenerated.
1679         * aarch64-dis-2.c: Regenerated.
1680         * aarch64-opc-2.c: Regenerated.
1681         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1682         for SVE_ADDR_ZX.
1683         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1684         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1685
1686 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1687
1688         * aarch64-asm-2.c: Regenerated.
1689         * aarch64-dis-2.c: Regenerated.
1690         * aarch64-opc-2.c: Regenerated.
1691         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1692         for SVE_Zm3_11_INDEX.
1693         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1694         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1695         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1696         fields.
1697         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1698
1699 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1700
1701         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1702         sve_size_hsd2 iclass encode.
1703         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1704         sve_size_hsd2 iclass decode.
1705         * aarch64-opc.c (fields): Handle SVE_size field.
1706         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1707
1708 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1709
1710         * aarch64-asm-2.c: Regenerated.
1711         * aarch64-dis-2.c: Regenerated.
1712         * aarch64-opc-2.c: Regenerated.
1713         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1714         for SVE_IMM_ROT3.
1715         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1716         (fields): Handle SVE_rot3 field.
1717         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1718         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1719
1720 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1721
1722         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1723         instructions.
1724
1725 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1726
1727         * aarch64-tbl.h
1728         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1729         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1730         aarch64_feature_sve2bitperm): New feature sets.
1731         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1732         for feature set addresses.
1733         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1734         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1735
1736 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1737             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1738
1739         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1740         argument and set ASE_EVA_R6 appropriately.
1741         (set_default_mips_dis_options): Pass ISA to above.
1742         (parse_mips_dis_option): Likewise.
1743         * mips-opc.c (EVAR6): New macro.
1744         (mips_builtin_opcodes): Add llwpe, scwpe.
1745
1746 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1747
1748         * aarch64-asm-2.c: Regenerated.
1749         * aarch64-dis-2.c: Regenerated.
1750         * aarch64-opc-2.c: Regenerated.
1751         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1752         AARCH64_OPND_TME_UIMM16.
1753         (aarch64_print_operand): Likewise.
1754         * aarch64-tbl.h (QL_IMM_NIL): New.
1755         (TME): New.
1756         (_TME_INSN): New.
1757         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1758
1759 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1760
1761         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1762
1763 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1764             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1765
1766         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1767
1768 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1769
1770         * s12z-opc.h: Add extern "C" bracketing to help
1771         users who wish to use this interface in c++ code.
1772
1773 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1774
1775         * s12z-opc.c (bm_decode): Handle bit map operations with the
1776         "reserved0" mode.
1777
1778 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1779
1780         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1781         specifier.  Add entries for VLDR and VSTR of system registers.
1782         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1783         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1784         of %J and %K format specifier.
1785
1786 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1787
1788         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1789         Add new entries for VSCCLRM instruction.
1790         (print_insn_coprocessor): Handle new %C format control code.
1791
1792 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1793
1794         * arm-dis.c (enum isa): New enum.
1795         (struct sopcode32): New structure.
1796         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1797         set isa field of all current entries to ANY.
1798         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1799         Only match an entry if its isa field allows the current mode.
1800
1801 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1802
1803         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1804         CLRM.
1805         (print_insn_thumb32): Add logic to print %n CLRM register list.
1806
1807 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1808
1809         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1810         and %Q patterns.
1811
1812 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1813
1814         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1815         (print_insn_thumb32): Edit the switch case for %Z.
1816
1817 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1818
1819         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1820
1821 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1822
1823         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1824
1825 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1826
1827         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1828
1829 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1830
1831         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1832         Arm register with r13 and r15 unpredictable.
1833         (thumb32_opcodes): New instructions for bfx and bflx.
1834
1835 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1836
1837         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1838
1839 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1840
1841         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1842
1843 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1844
1845         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1846
1847 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1848
1849         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1850
1851 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1852
1853         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1854         "optr". ("operator" is a reserved word in c++).
1855
1856 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1857
1858         * aarch64-opc.c (aarch64_print_operand): Add case for
1859         AARCH64_OPND_Rt_SP.
1860         (verify_constraints): Likewise.
1861         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1862         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1863         to accept Rt|SP as first operand.
1864         (AARCH64_OPERANDS): Add new Rt_SP.
1865         * aarch64-asm-2.c: Regenerated.
1866         * aarch64-dis-2.c: Regenerated.
1867         * aarch64-opc-2.c: Regenerated.
1868
1869 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1870
1871         * aarch64-asm-2.c: Regenerated.
1872         * aarch64-dis-2.c: Likewise.
1873         * aarch64-opc-2.c: Likewise.
1874         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1875
1876 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1877
1878         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1879
1880 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1881
1882         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1883         * i386-init.h: Regenerated.
1884
1885 2019-04-07  Alan Modra  <amodra@gmail.com>
1886
1887         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1888         op_separator to control printing of spaces, comma and parens
1889         rather than need_comma, need_paren and spaces vars.
1890
1891 2019-04-07  Alan Modra  <amodra@gmail.com>
1892
1893         PR 24421
1894         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1895         (print_insn_neon, print_insn_arm): Likewise.
1896
1897 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1898
1899         * i386-dis-evex.h (evex_table): Updated to support BF16
1900         instructions.
1901         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1902         and EVEX_W_0F3872_P_3.
1903         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1904         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1905         * i386-opc.h (enum): Add CpuAVX512_BF16.
1906         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1907         * i386-opc.tbl: Add AVX512 BF16 instructions.
1908         * i386-init.h: Regenerated.
1909         * i386-tbl.h: Likewise.
1910
1911 2019-04-05  Alan Modra  <amodra@gmail.com>
1912
1913         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1914         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1915         to favour printing of "-" branch hint when using the "y" bit.
1916         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1917
1918 2019-04-05  Alan Modra  <amodra@gmail.com>
1919
1920         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1921         opcode until first operand is output.
1922
1923 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1924
1925         PR gas/24349
1926         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1927         (valid_bo_post_v2): Add support for 'at' branch hints.
1928         (insert_bo): Only error on branch on ctr.
1929         (get_bo_hint_mask): New function.
1930         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1931         for inserting 'at' branch hints.
1932         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1933         for extracting 'at' branch hints.
1934         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1935         (BOE): Delete operand.
1936         (BOM, BOP): New operands.
1937         (RM): Update value.
1938         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1939         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1940         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1941         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1942         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1943         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1944         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1945         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1946         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1947         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1948         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1949         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1950         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1951         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1952         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1953         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1954         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1955         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1956         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1957         bttarl+>: New extended mnemonics.
1958
1959 2019-03-28  Alan Modra  <amodra@gmail.com>
1960
1961         PR 24390
1962         * ppc-opc.c (BTF): Define.
1963         (powerpc_opcodes): Use for mtfsb*.
1964         * ppc-dis.c (print_insn_powerpc): Print fields with both
1965         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1966
1967 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1968
1969         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1970         (mapping_symbol_for_insn): Implement new algorithm.
1971         (print_insn): Remove duplicate code.
1972
1973 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1974
1975         * aarch64-dis.c (print_insn_aarch64):
1976         Implement override.
1977
1978 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1979
1980         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1981         order.
1982
1983 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1984
1985         * aarch64-dis.c (last_stop_offset): New.
1986         (print_insn_aarch64): Use stop_offset.
1987
1988 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1989
1990         PR gas/24359
1991         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1992         CPU_ANY_AVX2_FLAGS.
1993         * i386-init.h: Regenerated.
1994
1995 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1996
1997         PR gas/24348
1998         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1999         vmovdqu16, vmovdqu32 and vmovdqu64.
2000         * i386-tbl.h: Regenerated.
2001
2002 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2003
2004         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
2005         from vstrszb, vstrszh, and vstrszf.
2006
2007 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2008
2009         * s390-opc.txt: Add instruction descriptions.
2010
2011 2019-02-08  Jim Wilson  <jimw@sifive.com>
2012
2013         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2014         <bne>: Likewise.
2015
2016 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2017
2018         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2019
2020 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2021
2022         PR binutils/23212
2023         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2024         * aarch64-opc.c (verify_elem_sd): New.
2025         (fields): Add FLD_sz entr.
2026         * aarch64-tbl.h (_SIMD_INSN): New.
2027         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2028         fmulx scalar and vector by element isns.
2029
2030 2019-02-07  Nick Clifton  <nickc@redhat.com>
2031
2032         * po/sv.po: Updated Swedish translation.
2033
2034 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
2035
2036         * s390-mkopc.c (main): Accept arch13 as cpu string.
2037         * s390-opc.c: Add new instruction formats and instruction opcode
2038         masks.
2039         * s390-opc.txt: Add new arch13 instructions.
2040
2041 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2042
2043         * aarch64-tbl.h (QL_LDST_AT): Update macro.
2044         (aarch64_opcode): Change encoding for stg, stzg
2045         st2g and st2zg.
2046         * aarch64-asm-2.c: Regenerated.
2047         * aarch64-dis-2.c: Regenerated.
2048         * aarch64-opc-2.c: Regenerated.
2049
2050 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2051
2052         * aarch64-asm-2.c: Regenerated.
2053         * aarch64-dis-2.c: Likewise.
2054         * aarch64-opc-2.c: Likewise.
2055         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2056
2057 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2058             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
2059
2060         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2061         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2062         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2063         * aarch64-dis.h (ext_addr_simple_2): Likewise.
2064         * aarch64-opc.c (operand_general_constraint_met_p): Remove
2065         case for ldstgv_indexed.
2066         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2067         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2068         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2069         * aarch64-asm-2.c: Regenerated.
2070         * aarch64-dis-2.c: Regenerated.
2071         * aarch64-opc-2.c: Regenerated.
2072
2073 2019-01-23  Nick Clifton  <nickc@redhat.com>
2074
2075         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2076
2077 2019-01-21  Nick Clifton  <nickc@redhat.com>
2078
2079         * po/de.po: Updated German translation.
2080         * po/uk.po: Updated Ukranian translation.
2081
2082 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
2083         * mips-dis.c (mips_arch_choices): Fix typo in
2084         gs464, gs464e and gs264e descriptors.
2085
2086 2019-01-19  Nick Clifton  <nickc@redhat.com>
2087
2088         * configure: Regenerate.
2089         * po/opcodes.pot: Regenerate.
2090
2091 2018-06-24  Nick Clifton  <nickc@redhat.com>
2092
2093         2.32 branch created.
2094
2095 2019-01-09  John Darrington <john@darrington.wattle.id.au>
2096
2097         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
2098         if it is null.
2099         -dis.c (opr_emit_disassembly): Do not omit an index if it is
2100         zero.
2101
2102 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
2103
2104         * configure: Regenerate.
2105
2106 2019-01-07  Alan Modra  <amodra@gmail.com>
2107
2108         * configure: Regenerate.
2109         * po/POTFILES.in: Regenerate.
2110
2111 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2112
2113         * s12z-opc.c: New file.
2114         * s12z-opc.h: New file.
2115         * s12z-dis.c: Removed all code not directly related to display
2116         of instructions.  Used the interface provided by the new files
2117         instead.
2118         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2119         * Makefile.in: Regenerate.
2120         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2121         * configure: Regenerate.
2122
2123 2019-01-01  Alan Modra  <amodra@gmail.com>
2124
2125         Update year range in copyright notice of all files.
2126
2127 For older changes see ChangeLog-2018
2128 \f
2129 Copyright (C) 2019 Free Software Foundation, Inc.
2130
2131 Copying and distribution of this file, with or without modification,
2132 are permitted in any medium without royalty provided the copyright
2133 notice and this notice are preserved.
2134
2135 Local Variables:
2136 mode: change-log
2137 left-margin: 8
2138 fill-column: 74
2139 version-control: never
2140 End: