opcodes/ChangeLog

   1 2006-11-30  Jan Beulich  <jbeulich@novell.com>
   2
   3         * i386-dis.c (dis386): Use 'R' and 'O' for cbw/cwd unconditionally.
   4         (putop): For 'O' suffix, print 'q' in Intel mode, and mark data prefix
   5         used. For 'R' and 'W' suffix, simplify and fix Intel mode.
   6
   7 2006-11-29  Paul Brook  <paul@codesourcery.com>
   8
   9         * arm-dis.c (coprocessor_opcodes): Fix bitfields for fconstd/fconstd.
  10
  11 2006-11-22  Daniel Jacobowitz  <dan@codesourcery.com>
  12
  13         * arm-dis.c (last_is_thumb): Delete.
  14         (enum map_type, last_type): New.
  15         (print_insn_data): New.
  16         (get_sym_code_type): Take MAP_TYPE argument.  Check the type of
  17         the right symbol.  Handle $d.
  18         (print_insn): Check for mapping symbols even without a normal
  19         symbol.  Adjust searching.  If $d is found see how much data
  20         to print.  Handle data.
  21
  22 2006-11-16  Nathan Sidwell  <nathan@codesourcery.com>
  23
  24         * m68k-opc.c (m68k_opcodes): Place trap instructions before set
  25         conditionals.  Add tpf coldfire instruction as alias for trapf.
  26
  27 2006-11-09  H.J. Lu  <hongjiu.lu@intel.com>
  28
  29         * i386-dis.c (print_insn): Check PREFIX_REPNZ before
  30         PREFIX_DATA when prefix user table is used.
  31
  32 2006-11-09  H.J. Lu  <hongjiu.lu@intel.com>
  33
  34         * i386-dis.c (twobyte_uses_SSE_prefix): Renamed to ...
  35         (twobyte_uses_DATA_prefix): This.
  36         (twobyte_uses_REPNZ_prefix): New.
  37         (twobyte_uses_REPZ_prefix): Likewise.
  38         (threebyte_0x38_uses_DATA_prefix): Likewise.
  39         (threebyte_0x38_uses_REPNZ_prefix): Likewise.
  40         (threebyte_0x38_uses_REPZ_prefix): Likewise.
  41         (threebyte_0x3a_uses_DATA_prefix): Likewise.
  42         (threebyte_0x3a_uses_REPNZ_prefix): Likewise.
  43         (threebyte_0x3a_uses_REPZ_prefix): Likewise.
  44         (print_insn): Updated checking usages of DATA/REPNZ/REPZ
  45         prefixes.
  46
  47 2006-11-06  Troy Rollo  <troy@corvu.com.au>
  48
  49         * ppc-opc.c: Restore COM to mfcr wrongly removed 2003-07-04.
  50
  51 2006-11-01  Mei Ligang  <ligang@sunnorth.com.cn>
  52
  53         * score-opc.h (score_opcodes): Delete modifier '0x'.
  54
  55 2006-10-30  Paul Brook  <paul@codesourcery.com>
  56
  57         * arm-dis.c (last_is_thumb, last_mapping_sym, last_mapping_addr): New.
  58         (get_sym_code_type): New function.
  59         (print_insn): Search for mapping symbols.
  60
  61 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
  62
  63         * score-dis.c (print_insn): Correct the error code to print
  64         correct PCE instruction disassembly.
  65
  66 2006-10-26  Ben Elliston  <bje@au.ibm.com>
  67             Anton Blanchard  <anton@samba.org>
  68             Peter Bergner  <bergner@vnet.ibm.com>
  69
  70         * ppc-opc.c (A_L, DCM, DGM, TE, RMC, R, SP, S, SH16, XRT_L, EH,
  71         AFRALFRC_MASK, Z, ZRC, Z_MASK, XLRT_MASK, XEH_MASK): Define.
  72         (POWER6): Define.
  73         (powerpc_opcodes): Extend "lwarx", "ldarx", "dcbf", "fres", "fres.",
  74         "frsqrtes", "frsqrtes." "fre", "fre.", "frsqrte" and "frsqrte.".
  75         Add "doze", "nap", "sleep", "rvwinkle", "dcbfl", "prtyw", "prtyd",
  76         "mfcfar", "cmpb", "lfdpx", "stfdpx", "mtcfar", "mffgpr", "mftgpr",
  77         "lwzcix", "lhzcix", "lbzcix", "ldcix", "lfiwax", "stwcix", "sthcix",
  78         "stbcix", "stdcix", "lfdp", "dadd", "dadd.", "dqua", "dqua.", "dmul",
  79         "dmul.", "drrnd", "drrnd.", "dscli", "dscli.", "dquai", "dquai.",
  80         "dscri", "dscri.", "drintx", "drintx.", "dcmpo", "dtstex", "dtstdc",
  81         "dtstdg", "dtstsf", "drintn", "drintn.", "dctdp", "dctdp.", "dctfix",
  82         "dctfix.", "ddedpd", "ddedpd.", "dxex", "dxex.", "dsub", "dsub.",
  83         "ddiv", "ddiv.", "dcmpu", "drsp", "drsp.", "dcffix", "dcffix.",
  84         "denbcd", "denbcd.", "diex", "diex.", "stfdp", "daddq", "daddq.",
  85         "dquaq", "dquaq.", "fcpsgn", "fcpsgn.", "dmulq", "dmulq.",
  86         "drrndq", "drrndq.", "dscliq", "dscliq.", "dquaiq", "dquaiq.",
  87         "dscriq", "dscriq.", "drintxq", "drintxq.", "dcmpoq", "dtstexq",
  88         "dtstdcq", "dtstdgq", "dtstsfq", "drintnq", "drintnq.",
  89         "dctqpq", "dctqpq.", "dctfixq", "dctfixq.", "ddedpdq", "ddedpdq.",
  90         "dxexq", "dxexq.", "dsubq", "dsubq.", "ddivq", "ddivq.", "dcmpuq",
  91         "drdpq", "drdpq.", "dcffixq", "dcffixq.", "denbcdq", "denbcdq.",
  92         "diexq" and "diexq." opcodes.
  93
  94 2006-10-26  Daniel Jacobowitz  <dan@codesourcery.com>
  95
  96         * h8300-dis.c (bfd_h8_disassemble): Add missing consts.
  97
  98 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
  99             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 100             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 101             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 102             Alan Modra  <amodra@bigpond.net.au>
 103
 104         * spu-dis.c: New file.
 105         * spu-opc.c: New file.
 106         * configure.in: Add SPU support.
 107         * disassemble.c: Likewise.
 108         * Makefile.am: Likewise.  Run "make dep-am".
 109         * Makefile.in: Regenerate.
 110         * configure: Regenerate.
 111         * po/POTFILES.in: Regenerate.
 112
 113 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 114
 115         * ppc-opc.c (CELL): New define.
 116         (powerpc_opcodes): Enable hrfid for Cell.  Add ldbrx and stdbrx,
 117         cell specific instructions.  Add {st,l}x{r,l}{,l} cell specific
 118         VMX instructions.
 119         * ppc-dis.c (powerpc_dialect): Handle cell.
 120
 121 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 122
 123         * i386-dis.c (dis386): Add support for the change in POPCNT opcode in
 124         amdfam10 architecture.
 125         (PREGRP37): NEW.
 126         (print_insn): Disallow REP prefix for POPCNT.
 127
 128 2006-10-20  Andrew Stubbs  <andrew.stubbs@st.com>
 129
 130         * sh-dis.c (print_insn_sh): Remove 0x from output to prevent GDB
 131         duplicating it.
 132
 133 2006-10-18  Dave Brolley  <brolley@redhat.com>
 134
 135         * configure.in (BFD_MACHINES): Add cgen-bitset.lo for bfd_sh_arch.
 136         * configure: Regenerated.
 137
 138 2006-09-29  Alan Modra  <amodra@bigpond.net.au>
 139
 140         * po/POTFILES.in: Regenerate.
 141
 142 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 143             Joseph Myers  <joseph@codesourcery.com>
 144             Ian Lance Taylor  <ian@wasabisystems.com>
 145             Ben Elliston  <bje@wasabisystems.com>
 146
 147         * arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
 148         only be used with the default multiply-add operation, so if N is
 149         set, don't bother printing X.  Add new iwmmxt instructions.
 150         (IWMMXT_INSN_COUNT): Update.
 151         (iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
 152         with a 'c' suffix.
 153         (print_insn_coprocessor): Check for iWMMXt2.  Handle format
 154         specifiers 'r', 'i'.
 155
 156 2006-09-24  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 157
 158         PR binutils/3100
 159         * i386-dis.c (prefix_user_table): Fix the second operand of
 160         maskmovdqu instruction to allow only %xmm register instead of
 161         both %xmm register and memory.
 162
 163 2006-09-23  H.J. Lu  <hongjiu.lu@intel.com>
 164
 165         PR binutils/3235
 166         * i386-dis.c (OP_OFF64): Get 32bit offset if there is an
 167         address size prefix.
 168
 169 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 170
 171         * score-dis.c: New file.
 172         * score-opc.h: New file.
 173         * Makefile.am: Add Score files.
 174         * Makefile.in: Regenerate.
 175         * configure.in: Add support for Score target.
 176         * configure: Regenerate.
 177         * disassemble.c: Add support for Score target.
 178
 179 2006-09-16  Nick Clifton  <nickc@redhat.com>
 180             Pedro Alves  <pedro_alves@portugalmail.pt>
 181
 182         * arm-dis.c: Make use of new STRING_COMMA_LEN and CONST_STRNEQ
 183         macros defined in bfd.h.
 184         * cris-dis.c: Likewise.
 185         * h8300-dis.c: Likewise.
 186         * i386-dis.c: Likewise.
 187         * ia64-gen.c: Likewise.
 188         * mips-dis: Likewise.
 189
 190 2006-09-04  Paul Brook  <paul@codesourcery.com>
 191
 192         * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
 193
 194 2006-08-23  H.J. Lu  <hongjiu.lu@intel.com>
 195
 196         * i386-dis.c (three_byte_table): Expand to 256 elements.
 197
 198 2006-08-04  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 199
 200         PR binutils/3000
 201         * i386-dis.c (MXC,EMC): Define.
 202         (OP_MXC): New function to handle cvt* (convert instructions) between
 203         %xmm and %mm register correctly.
 204         (OP_EMC): ditto.
 205         (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
 206         instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
 207         with EMC/MXC.
 208
 209 2006-07-29  Richard Sandiford  <richard@codesourcery.com>
 210
 211         * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
 212         "fdaddl" entry.
 213
 214 2006-07-19  Paul Brook  <paul@codesourcery.com>
 215
 216         * armd-dis.c (arm_opcodes): Fix rbit opcode.
 217
 218 2006-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 219
 220         * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
 221         "sldt", "str" and "smsw".
 222
 223 2006-07-15  H.J. Lu  <hongjiu.lu@intel.com>
 224
 225         PR binutils/2829
 226         * i386-dis.c (GRP11_C6): NEW.
 227         (GRP11_C7): Likewise.
 228         (GRP12): Updated.
 229         (GRP13): Likewise.
 230         (GRP14): Likewise.
 231         (GRP15): Likewise.
 232         (GRP16): Likewise.
 233         (GRPAMD): Likewise.
 234         (GRPPADLCK1): Likewise.
 235         (GRPPADLCK2): Likewise.
 236         (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
 237         respectively.
 238         (grps): Add entries for GRP11_C6 and GRP11_C7.
 239
 240 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 241            Michael Meissner             <michael.meissner@amd.com>
 242
 243         * i386-dis.c (dis386): Add support for 4 operand instructions. Add
 244         support for amdfam10 SSE4a/ABM instructions. Modify all
 245         initializer macros to have additional arguments. Disallow REP
 246         prefix for non-string instructions.
 247         (print_insn): Ditto.
 248
 249 2006-07-05  Julian Brown  <julian@codesourcery.com>
 250
 251         * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
 252
 253 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 254
 255         * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
 256         (twobyte_has_modrm): Set 1 for 0x1f.
 257
 258 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 259
 260         * i386-dis.c (NOP_Fixup): Removed.
 261         (NOP_Fixup1): New.
 262         (NOP_Fixup2): Likewise.
 263         (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
 264
 265 2006-06-12  Julian Brown  <julian@codesourcery.com>
 266
 267         * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
 268         on 64-bit hosts.
 269
 270 2006-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 271
 272         * i386.c (GRP10): Renamed to ...
 273         (GRP12): This.
 274         (GRP11): Renamed to ...
 275         (GRP13): This.
 276         (GRP12): Renamed to ...
 277         (GRP14): This.
 278         (GRP13): Renamed to ...
 279         (GRP15): This.
 280         (GRP14): Renamed to ...
 281         (GRP16): This.
 282         (dis386_twobyte): Updated.
 283         (grps): Likewise.
 284
 285 2006-06-09  Nick Clifton  <nickc@redhat.com>
 286
 287         * po/fi.po: Updated Finnish translation.
 288
 289 2006-06-07  Joseph S. Myers  <joseph@codesourcery.com>
 290
 291         * po/Make-in (pdf, ps): New dummy targets.
 292
 293 2006-06-06  Paul Brook  <paul@codesourcery.com>
 294
 295         * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
 296         instructions.
 297         (neon_opcodes): Add conditional execution specifiers.
 298         (thumb_opcodes): Ditto.
 299         (thumb32_opcodes): Ditto.
 300         (arm_conditional): Change 0xe to "al" and add "" to end.
 301         (ifthen_state, ifthen_next_state, ifthen_address): New.
 302         (IFTHEN_COND): Define.
 303         (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
 304         (print_insn_arm): Change %c to use new values of arm_conditional.
 305         (print_insn_thumb16): Print thumb conditions.  Add %I.
 306         (print_insn_thumb32): Print thumb conditions.
 307         (find_ifthen_state): New function.
 308         (print_insn): Track IT block state.
 309
 310 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 311             Anton Blanchard  <anton@samba.org>
 312             Peter Bergner  <bergner@vnet.ibm.com>
 313
 314         * ppc-dis.c (powerpc_dialect): Handle power6 option.
 315         (print_ppc_disassembler_options): Mention power6.
 316
 317 2006-06-06  Thiemo Seufer  <ths@mips.com>
 318             Chao-ying Fu  <fu@mips.com>
 319
 320         * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
 321         * mips-opc.c: Add DSP64 instructions.
 322
 323 2006-06-06  Alan Modra  <amodra@bigpond.net.au>
 324
 325         * m68hc11-dis.c (print_insn): Warning fix.
 326
 327 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
 328
 329         * po/Make-in (top_builddir): Define.
 330
 331 2006-06-05  Alan Modra  <amodra@bigpond.net.au>
 332
 333         * Makefile.am: Run "make dep-am".
 334         * Makefile.in: Regenerate.
 335         * config.in: Regenerate.
 336
 337 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
 338
 339         * Makefile.am (INCLUDES): Use @INCINTL@.
 340         * acinclude.m4: Include new gettext macros.
 341         * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
 342         Remove local code for po/Makefile.
 343         * Makefile.in, aclocal.m4, configure: Regenerated.
 344
 345 2006-05-30  Nick Clifton  <nickc@redhat.com>
 346
 347         * po/es.po: Updated Spanish translation.
 348
 349 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 350
 351         * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
 352         and fmovem entries.  Put register list entries before immediate
 353         mask entries.  Use "l" rather than "L" in the fmovem entries.
 354         * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
 355         out from INFO.
 356         (m68k_scan_mask): New function, split out from...
 357         (print_insn_m68k): ...here.  If no architecture has been set,
 358         first try printing an m680x0 instruction, then try a Coldfire one.
 359
 360 2006-05-24  Nick Clifton  <nickc@redhat.com>
 361
 362         * po/ga.po: Updated Irish translation.
 363
 364 2006-05-22  Nick Clifton  <nickc@redhat.com>
 365
 366         * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
 367
 368 2006-05-22  Nick Clifton  <nickc@redhat.com>
 369
 370         * po/nl.po: Updated translation.
 371
 372 2006-05-18  Alan Modra  <amodra@bigpond.net.au>
 373
 374         * avr-dis.c: Formatting fix.
 375
 376 2006-05-14  Thiemo Seufer  <ths@mips.com>
 377
 378         * mips16-opc.c (I1, I32, I64): New shortcut defines.
 379         (mips16_opcodes): Change membership of instructions to their
 380         lowest baseline ISA.
 381
 382 2006-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 383
 384         * i386-dis.c (grps): Update sgdt/sidt for 64bit.
 385
 386 2006-05-05  Julian Brown  <julian@codesourcery.com>
 387
 388         * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
 389         vldm/vstm.
 390
 391 2006-05-05  Thiemo Seufer  <ths@mips.com>
 392             David Ung  <davidu@mips.com>
 393
 394         * mips-opc.c: Add macro for cache instruction.
 395
 396 2006-05-04  Thiemo Seufer  <ths@mips.com>
 397             Nigel Stephens  <nigel@mips.com>
 398             David Ung  <davidu@mips.com>
 399
 400         * mips-dis.c (mips_arch_choices): Add smartmips instruction
 401         decoding to MIPS32 and MIPS32R2.  Limit DSP decoding to release
 402         2 ISAs.  Add MIPS3D decoding to MIPS32R2.  Add MT decoding to
 403         MIPS64R2.
 404         * mips-opc.c: fix random typos in comments.
 405         (INSN_SMARTMIPS): New defines.
 406         (mips_builtin_opcodes): Add paired single support for MIPS32R2.
 407         Move bc3f, bc3fl, bc3t, bc3tl downwards.  Move flushi, flushd,
 408         flushid, wb upwards.  Move cfc3, ctc3 downwards.  Rework the
 409         FP_S and FP_D flags to denote single and double register
 410         accesses separately.  Move dmfc3, dmtc3, mfc3, mtc3 downwards.
 411         Allow jr.hb and jalr.hb for release 1 ISAs.  Allow luxc1, suxc1
 412         for MIPS32R2.  Add SmartMIPS instructions.  Add two-argument
 413         variants of bc2f, bc2fl, bc2t, bc2tl.  Add mfhc2, mthc2 to
 414         release 2 ISAs.
 415         * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
 416
 417 2006-05-03  Thiemo Seufer  <ths@mips.com>
 418
 419         * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
 420
 421 2006-05-02  Thiemo Seufer  <ths@mips.com>
 422             Nigel Stephens  <nigel@mips.com>
 423             David Ung  <davidu@mips.com>
 424
 425         * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
 426         (print_mips16_insn_arg): Force mips16 to odd addresses.
 427
 428 2006-04-30  Thiemo Seufer  <ths@mips.com>
 429             David Ung  <davidu@mips.com>
 430
 431         * mips-opc.c (mips_builtin_opcodes): Add udi instructions
 432         "udi0" to "udi15".
 433         * mips-dis.c (print_insn_args): Adds udi argument handling.
 434
 435 2006-04-28  James E Wilson  <wilson@specifix.com>
 436
 437         * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
 438         error message.
 439
 440 2006-04-28  Thiemo Seufer  <ths@mips.com>
 441             David Ung  <davidu@mips.com>
 442             Nigel Stephens  <nigel@mips.com>
 443
 444         * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
 445         names.
 446
 447 2006-04-28  Thiemo Seufer  <ths@mips.com>
 448             Nigel Stephens  <nigel@mips.com>
 449             David Ung  <davidu@mips.com>
 450
 451         * mips-dis.c (print_insn_args): Add mips_opcode argument.
 452         (print_insn_mips):  Adjust print_insn_args call.
 453
 454 2006-04-28  Thiemo Seufer  <ths@mips.com>
 455             Nigel Stephens  <nigel@mips.com>
 456
 457         * mips-dis.c (print_insn_args): Print $fcc only for FP
 458         instructions, use $cc elsewise.
 459
 460 2006-04-28  Thiemo Seufer  <ths@mips.com>
 461             Nigel Stephens  <nigel@mips.com>
 462
 463         * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
 464         Map MIPS16 registers to O32 names.
 465         (print_mips16_insn_arg): Use mips16_reg_names.
 466
 467 2006-04-26  Julian Brown  <julian@codesourcery.com>
 468
 469         * arm-dis.c (print_insn_neon): Disassemble floating-point constant
 470         VMOV.
 471
 472 2006-04-26  Nathan Sidwell  <nathan@codesourcery.com>
 473             Julian Brown  <julian@codesourcery.com>
 474
 475         * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
 476         %<code>[zy] into %[zy]<code>.  Expand meaning of %<bitfield>['`?].
 477         Add unified load/store instruction names.
 478         (neon_opcode_table): New.
 479         (arm_opcodes): Expand meaning of %<bitfield>['`?].
 480         (arm_decode_bitfield): New.
 481         (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
 482         Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
 483         (print_insn_neon): New.
 484         (print_insn_arm): Adjust print_insn_coprocessor call. Call
 485         print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
 486         (print_insn_thumb32): Likewise.
 487
 488 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 489
 490         * Makefile.am: Run "make dep-am".
 491         * Makefile.in: Regenerate.
 492
 493 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 494
 495         * avr-dis.c (avr_operand): Warning fix.
 496
 497         * configure: Regenerate.
 498
 499 2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>
 500
 501         * po/POTFILES.in: Regenerated.
 502
 503 2006-04-12   Hochstein  <hochstein@algo.informatik.tu-darmstadt.de>
 504
 505         PR binutils/2454
 506         * avr-dis.c (avr_operand): Arrange for a comment to appear before
 507         the symolic form of an address, so that the output of objdump -d
 508         can be reassembled.
 509
 510 2006-04-10  DJ Delorie  <dj@redhat.com>
 511
 512         * m32c-asm.c: Regenerate.
 513
 514 2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>
 515
 516         * Makefile.am: Add install-html target.
 517         * Makefile.in: Regenerate.
 518
 519 2006-04-06  Nick Clifton  <nickc@redhat.com>
 520
 521         * po/vi/po: Updated Vietnamese translation.
 522
 523 2006-03-31  Paul Koning  <ni1d@arrl.net>
 524
 525         * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
 526
 527 2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>
 528
 529         * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
 530         logic to identify halfword shifts.
 531
 532 2006-03-16  Paul Brook  <paul@codesourcery.com>
 533
 534         * arm-dis.c (arm_opcodes): Rename swi to svc.
 535         (thumb_opcodes): Ditto.
 536
 537 2006-03-13  DJ Delorie  <dj@redhat.com>
 538
 539         * m32c-asm.c: Regenerate.
 540         * m32c-desc.c: Likewise.
 541         * m32c-desc.h: Likewise.
 542         * m32c-dis.c: Likewise.
 543         * m32c-ibld.c: Likewise.
 544         * m32c-opc.c: Likewise.
 545         * m32c-opc.h: Likewise.
 546
 547 2006-03-10  DJ Delorie  <dj@redhat.com>
 548
 549         * m32c-desc.c: Regenerate with mul.l, mulu.l.
 550         * m32c-opc.c: Likewise.
 551         * m32c-opc.h: Likewise.
 552
 553
 554 2006-03-09  Nick Clifton  <nickc@redhat.com>
 555
 556         * po/sv.po: Updated Swedish translation.
 557
 558 2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>
 559
 560         PR binutils/2428
 561         * i386-dis.c (REP_Fixup): New function.
 562         (AL): Remove duplicate.
 563         (Xbr): New.
 564         (Xvr): Likewise.
 565         (Ybr): Likewise.
 566         (Yvr): Likewise.
 567         (indirDXr): Likewise.
 568         (ALr): Likewise.
 569         (eAXr): Likewise.
 570         (dis386): Updated entries of ins, outs, movs, lods and stos.
 571
 572 2006-03-05  Nick Clifton  <nickc@redhat.com>
 573
 574         * cgen-ibld.in (insert_normal): Cope with attempts to insert a
 575         signed 32-bit value into an unsigned 32-bit field when the host is
 576         a 64-bit machine.
 577         * fr30-ibld.c: Regenerate.
 578         * frv-ibld.c: Regenerate.
 579         * ip2k-ibld.c: Regenerate.
 580         * iq2000-asm.c: Regenerate.
 581         * iq2000-ibld.c: Regenerate.
 582         * m32c-ibld.c: Regenerate.
 583         * m32r-ibld.c: Regenerate.
 584         * openrisc-ibld.c: Regenerate.
 585         * xc16x-ibld.c: Regenerate.
 586         * xstormy16-ibld.c: Regenerate.
 587
 588 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
 589
 590         * xc16x-asm.c: Regenerate.
 591         * xc16x-dis.c: Regenerate.
 592
 593 2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>
 594
 595         * po/Make-in: Add html target.
 596
 597 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 598
 599         * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
 600         Intel Merom New Instructions.
 601         (THREE_BYTE_0): Likewise.
 602         (THREE_BYTE_1): Likewise.
 603         (three_byte_table): Likewise.
 604         (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
 605         THREE_BYTE_1 for entry 0x3a.
 606         (twobyte_has_modrm): Updated.
 607         (twobyte_uses_SSE_prefix): Likewise.
 608         (print_insn): Handle 3-byte opcodes used by Intel Merom New
 609         Instructions.
 610
 611 2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
 612
 613         * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
 614         (v9_hpriv_reg_names): New table.
 615         (print_insn_sparc): Allow values up to 16 for '?' and '!'.
 616         New cases '$' and '%' for read/write hyperprivileged register.
 617         * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
 618         window handling and rdhpr/wrhpr instructions.
 619
 620 2006-02-24  DJ Delorie  <dj@redhat.com>
 621
 622         * m32c-desc.c: Regenerate with linker relaxation attributes.
 623         * m32c-desc.h: Likewise.
 624         * m32c-dis.c: Likewise.
 625         * m32c-opc.c: Likewise.
 626
 627 2006-02-24  Paul Brook  <paul@codesourcery.com>
 628
 629         * arm-dis.c (arm_opcodes): Add V7 instructions.
 630         (thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
 631         (print_arm_address): New function.
 632         (print_insn_arm): Use it.  Add 'P' and 'U' cases.
 633         (psr_name): New function.
 634         (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
 635
 636 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 637
 638         * ia64-opc-i.c (bXc): New.
 639         (mXc): Likewise.
 640         (OpX2TaTbYaXcC): Likewise.
 641         (TF). Likewise.
 642         (TFCM). Likewise.
 643         (ia64_opcodes_i): Add instructions for tf.
 644
 645         * ia64-opc.h (IMMU5b): New.
 646
 647         * ia64-asmtab.c: Regenerated.
 648
 649 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 650
 651         * ia64-gen.c: Update copyright years.
 652         * ia64-opc-b.c: Likewise.
 653
 654 2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 655
 656         * ia64-gen.c (lookup_regindex): Handle ".vm".
 657         (print_dependency_table): Handle '\"'.
 658
 659         * ia64-ic.tbl: Updated from SDM 2.2.
 660         * ia64-raw.tbl: Likewise.
 661         * ia64-waw.tbl: Likewise.
 662         * ia64-asmtab.c: Regenerated.
 663
 664         * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
 665
 666 2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
 667             Anil Paranjape   <anilp1@kpitcummins.com>
 668             Shilin Shakti    <shilins@kpitcummins.com>
 669
 670         * xc16x-desc.h: New file
 671         * xc16x-desc.c: New file
 672         * xc16x-opc.h: New file
 673         * xc16x-opc.c: New file
 674         * xc16x-ibld.c: New file
 675         * xc16x-asm.c: New file
 676         * xc16x-dis.c: New file
 677         * Makefile.am: Entries for xc16x
 678         * Makefile.in: Regenerate
 679         * cofigure.in: Add xc16x target information.
 680         * configure: Regenerate.
 681         * disassemble.c: Add xc16x target information.
 682
 683 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 684
 685         * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
 686         moves.
 687
 688 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 689
 690         * i386-dis.c ('Z'): Add a new macro.
 691         (dis386_twobyte): Use "movZ" for control register moves.
 692
 693 2006-02-10  Nick Clifton  <nickc@redhat.com>
 694
 695         * iq2000-asm.c: Regenerate.
 696
 697 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 698
 699         * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
 700
 701 2006-01-26  David Ung  <davidu@mips.com>
 702
 703         * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
 704         ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
 705         floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
 706         nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
 707         rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
 708
 709 2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>
 710
 711         * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
 712         ld_d_r, pref_xd_cb): Use signed char to hold data to be
 713         disassembled.
 714         * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
 715         buffer overflows when disassembling instructions like
 716         ld (ix+123),0x23
 717         * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
 718         operand, if the offset is negative.
 719
 720 2006-01-17  Arnold Metselaar  <arnoldm@sourceware.org>
 721
 722         * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
 723         unsigned char to hold data to be disassembled.
 724
 725 2006-01-17  Andreas Schwab  <schwab@suse.de>
 726
 727         PR binutils/1486
 728         * disassemble.c (disassemble_init_for_target): Set
 729         disassembler_needs_relocs for bfd_arch_arm.
 730
 731 2006-01-16  Paul Brook  <paul@codesourcery.com>
 732
 733         * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
 734         f?add?, and f?sub? instructions.
 735
 736 2006-01-16  Nick Clifton  <nickc@redhat.com>
 737
 738         * po/zh_CN.po: New Chinese (simplified) translation.
 739         * configure.in (ALL_LINGUAS): Add "zh_CH".
 740         * configure: Regenerate.
 741
 742 2006-01-05  Paul Brook  <paul@codesourcery.com>
 743
 744         * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
 745
 746 2006-01-06  DJ Delorie  <dj@redhat.com>
 747
 748         * m32c-desc.c: Regenerate.
 749         * m32c-opc.c: Regenerate.
 750         * m32c-opc.h: Regenerate.
 751
 752 2006-01-03  DJ Delorie  <dj@redhat.com>
 753
 754         * cgen-ibld.in (extract_normal): Avoid memory range errors.
 755         * m32c-ibld.c: Regenerated.
 756
 757 For older changes see ChangeLog-2005
 758 \f
 759 Local Variables:
 760 mode: change-log
 761 left-margin: 8
 762 fill-column: 74
 763 version-control: never
 764 End: