opcodes/ChangeLog

   1 2019-11-14  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-gen.c (operand_type_init): Remove
   4         OPERAND_TYPE_JUMPABSOLUTE entry.
   5         (opcode_modifiers): Add JumpAbsolute entry.
   6         (operand_types): Remove JumpAbsolute entry.
   7         * i386-opc.h (JumpAbsolute): Move between enums.
   8         (struct i386_opcode_modifier): Add jumpabsolute field.
   9         (union i386_operand_type): Remove jumpabsolute field.
  10         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
  11         * i386-init.h, i386-tbl.h: Re-generate.
  12
  13 2019-11-14  Jan Beulich  <jbeulich@suse.com>
  14
  15         * i386-gen.c (opcode_modifiers): Add AnySize entry.
  16         (operand_types): Remove AnySize entry.
  17         * i386-opc.h (AnySize): Move between enums.
  18         (struct i386_opcode_modifier): Add anysize field.
  19         (OTUnused): Un-comment.
  20         (union i386_operand_type): Remove anysize field.
  21         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
  22         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
  23         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
  24         AnySize.
  25         * i386-tbl.h: Re-generate.
  26
  27 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
  28
  29         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
  30         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
  31         use the floating point register (FPR).
  32
  33 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
  34
  35         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
  36         cmode 1101.
  37         (is_mve_encoding_conflict): Update cmode conflict checks for
  38         MVE_VMVN_IMM.
  39
  40 2019-11-12  Jan Beulich  <jbeulich@suse.com>
  41
  42         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
  43         entry.
  44         (operand_types): Remove EsSeg entry.
  45         (main): Replace stale use of OTMax.
  46         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
  47         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
  48         (EsSeg): Delete.
  49         (OTUnused): Comment out.
  50         (union i386_operand_type): Remove esseg field.
  51         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
  52         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
  53         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
  54         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
  55         * i386-init.h, i386-tbl.h: Re-generate.
  56
  57 2019-11-12  Jan Beulich  <jbeulich@suse.com>
  58
  59         * i386-gen.c (operand_instances): Add RegB entry.
  60         * i386-opc.h (enum operand_instance): Add RegB.
  61         * i386-opc.tbl (RegC, RegD, RegB): Define.
  62         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
  63         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
  64         monitorx, mwaitx): Drop ImmExt and convert encodings
  65         accordingly.
  66         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
  67         (edx, rdx): Add Instance=RegD.
  68         (ebx, rbx): Add Instance=RegB.
  69         * i386-tbl.h: Re-generate.
  70
  71 2019-11-12  Jan Beulich  <jbeulich@suse.com>
  72
  73         * i386-gen.c (operand_type_init): Adjust
  74         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
  75         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
  76         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
  77         (operand_instances): New.
  78         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
  79         (output_operand_type): New parameter "instance". Process it.
  80         (process_i386_operand_type): New local variable "instance".
  81         (main): Adjust static assertions.
  82         * i386-opc.h (INSTANCE_WIDTH): Define.
  83         (enum operand_instance): New.
  84         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
  85         (union i386_operand_type): Replace acc, inoutportreg, and
  86         shiftcount by instance.
  87         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
  88         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
  89         Add Instance=.
  90         * i386-init.h, i386-tbl.h: Re-generate.
  91
  92 2019-11-11  Jan Beulich  <jbeulich@suse.com>
  93
  94         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
  95         smaxp/sminp entries' "tied_operand" field to 2.
  96
  97 2019-11-11  Jan Beulich  <jbeulich@suse.com>
  98
  99         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 100         "index" local variable by that of the already existing "num".
 101
 102 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 103
 104         PR gas/25167
 105         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 106         * i386-tbl.h: Regenerated.
 107
 108 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 109
 110         * i386-gen.c (operand_type_init): Add Class= to
 111         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 112         OPERAND_TYPE_REGBND entry.
 113         (operand_classes): Add RegMask and RegBND entries.
 114         (operand_types): Drop RegMask and RegBND entry.
 115         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 116         (RegMask, RegBND): Delete.
 117         (union i386_operand_type): Remove regmask and regbnd fields.
 118         * i386-opc.tbl (RegMask, RegBND): Define.
 119         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 120         Class=RegBND.
 121         * i386-init.h, i386-tbl.h: Re-generate.
 122
 123 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 124
 125         * i386-gen.c (operand_type_init): Add Class= to
 126         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 127         OPERAND_TYPE_REGZMM entries.
 128         (operand_classes): Add RegMMX and RegSIMD entries.
 129         (operand_types): Drop RegMMX and RegSIMD entries.
 130         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 131         (RegMMX, RegSIMD): Delete.
 132         (union i386_operand_type): Remove regmmx and regsimd fields.
 133         * i386-opc.tbl (RegMMX): Define.
 134         (RegXMM, RegYMM, RegZMM): Add Class=.
 135         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 136         Class=RegSIMD.
 137         * i386-init.h, i386-tbl.h: Re-generate.
 138
 139 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 140
 141         * i386-gen.c (operand_type_init): Add Class= to
 142         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 143         entries.
 144         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 145         (operand_types): Drop Control, Debug, and Test entries.
 146         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 147         (Control, Debug, Test): Delete.
 148         (union i386_operand_type): Remove control, debug, and test
 149         fields.
 150         * i386-opc.tbl (Control, Debug, Test): Define.
 151         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 152         Class=RegDR, and Test by Class=RegTR.
 153         * i386-init.h, i386-tbl.h: Re-generate.
 154
 155 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 156
 157         * i386-gen.c (operand_type_init): Add Class= to
 158         OPERAND_TYPE_SREG entry.
 159         (operand_classes): Add SReg entry.
 160         (operand_types): Drop SReg entry.
 161         * i386-opc.h (enum operand_class): Add SReg.
 162         (SReg): Delete.
 163         (union i386_operand_type): Remove sreg field.
 164         * i386-opc.tbl (SReg): Define.
 165         * i386-reg.tbl: Replace SReg by Class=SReg.
 166         * i386-init.h, i386-tbl.h: Re-generate.
 167
 168 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 169
 170         * i386-gen.c (operand_type_init): Add Class=. New
 171         OPERAND_TYPE_ANYIMM entry.
 172         (operand_classes): New.
 173         (operand_types): Drop Reg entry.
 174         (output_operand_type): New parameter "class". Process it.
 175         (process_i386_operand_type): New local variable "class".
 176         (main): Adjust static assertions.
 177         * i386-opc.h (CLASS_WIDTH): Define.
 178         (enum operand_class): New.
 179         (Reg): Replace by Class. Adjust comment.
 180         (union i386_operand_type): Replace reg by class.
 181         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 182         Class=.
 183         * i386-reg.tbl: Replace Reg by Class=Reg.
 184         * i386-init.h: Re-generate.
 185
 186 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 187
 188         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 189         (aarch64_opcode_table): Add data gathering hint mnemonic.
 190         * opcodes/aarch64-dis-2.c: Account for new instruction.
 191
 192 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 193
 194         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 195
 196
 197 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 198
 199         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 200         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 201         aarch64_feature_f64mm): New feature sets.
 202         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 203         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 204         instructions.
 205         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 206         macros.
 207         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 208         (OP_SVE_QQQ): New qualifier.
 209         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 210         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 211         the movprfx constraint.
 212         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 213         (aarch64_opcode_table): Define new instructions smmla,
 214         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 215         uzip{1/2}, trn{1/2}.
 216         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 217         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 218         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 219         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 220         Account for new instructions.
 221         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 222         S4x32 operand.
 223         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 224
 225 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 226 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 227
 228         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 229         Armv8.6-A.
 230         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 231         (neon_opcodes): Add bfloat SIMD instructions.
 232         (print_insn_coprocessor): Add new control character %b to print
 233         condition code without checking cp_num.
 234         (print_insn_neon): Account for BFloat16 instructions that have no
 235         special top-byte handling.
 236
 237 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 238 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 239
 240         * arm-dis.c (print_insn_coprocessor,
 241         print_insn_generic_coprocessor): Create wrapper functions around
 242         the implementation of the print_insn_coprocessor control codes.
 243         (print_insn_coprocessor_1): Original print_insn_coprocessor
 244         function that now takes which array to look at as an argument.
 245         (print_insn_arm): Use both print_insn_coprocessor and
 246         print_insn_generic_coprocessor.
 247         (print_insn_thumb32): As above.
 248
 249 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 250 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 251
 252         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 253         in reglane special case.
 254         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 255         aarch64_find_next_opcode): Account for new instructions.
 256         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 257         in reglane special case.
 258         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 259         new AARCH64_OPND_QLF_S_2H qualifier.
 260         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 261         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 262         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 263         sets.
 264         (BFLOAT_SVE, BFLOAT): New feature set macros.
 265         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 266         instructions.
 267         (aarch64_opcode_table): Define new instructions bfdot,
 268         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 269         bfcvtn2, bfcvt.
 270
 271 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 272 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 273
 274         * aarch64-tbl.h (ARMV8_6): New macro.
 275
 276 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 277
 278         * i386-dis.c (prefix_table): Add mcommit.
 279         (rm_table): Add rdpru.
 280         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 281         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 282         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 283         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 284         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 285         * i386-opc.tbl (mcommit, rdpru): New.
 286         * i386-init.h, i386-tbl.h: Re-generate.
 287
 288 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 289
 290         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 291         "names32" instead.
 292         (OP_Monitor): Drop local variable "op1_names", re-purpose
 293         "names" for it instead, and replace former "names" uses by
 294         "names32" ones.
 295
 296 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 297
 298         PR/gas 25167
 299         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 300         operand-less forms.
 301         * opcodes/i386-tbl.h: Re-generate.
 302
 303 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 304
 305         * i386-dis.c (OP_Mwaitx): Delete.
 306         (prefix_table): Use OP_Mwait for mwaitx entry.
 307         (OP_Mwait): Also handle mwaitx.
 308
 309 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 310
 311         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 312         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 313         (prefix_table): Add respective entries.
 314         (rm_table): Link to those entries.
 315
 316 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 317
 318         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 319         (REG_0F1C_P_0_MOD_0): ... this.
 320         (REG_0F1E_MOD_3): Rename to ...
 321         (REG_0F1E_P_1_MOD_3): ... this.
 322         (RM_0F01_REG_5): Rename to ...
 323         (RM_0F01_REG_5_MOD_3): ... this.
 324         (RM_0F01_REG_7): Rename to ...
 325         (RM_0F01_REG_7_MOD_3): ... this.
 326         (RM_0F1E_MOD_3_REG_7): Rename to ...
 327         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 328         (RM_0FAE_REG_6): Rename to ...
 329         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 330         (RM_0FAE_REG_7): Rename to ...
 331         (RM_0FAE_REG_7_MOD_3): ... this.
 332         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 333         (PREFIX_0F01_REG_5_MOD_0): ... this.
 334         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 335         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 336         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 337         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 338         (PREFIX_0FAE_REG_0): Rename to ...
 339         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 340         (PREFIX_0FAE_REG_1): Rename to ...
 341         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 342         (PREFIX_0FAE_REG_2): Rename to ...
 343         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 344         (PREFIX_0FAE_REG_3): Rename to ...
 345         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 346         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 347         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 348         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 349         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 350         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 351         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 352         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 353         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 354         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 355         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 356         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 357         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 358         (PREFIX_0FAE_REG_7): Rename to ...
 359         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 360         (PREFIX_MOD_0_0FC3): Rename to ...
 361         (PREFIX_0FC3_MOD_0): ... this.
 362         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 363         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 364         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 365         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 366         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 367         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 368         (reg_table, prefix_table, mod_table, rm_table): Adjust
 369         accordingly.
 370
 371 2019-11-04  Nick Clifton  <nickc@redhat.com>
 372
 373         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 374         of a v850 system register.  Move the v850_sreg_names array into
 375         this function.
 376         (get_v850_reg_name): Likewise for ordinary register names.
 377         (get_v850_vreg_name): Likewise for vector register names.
 378         (get_v850_cc_name): Likewise for condition codes.
 379         * get_v850_float_cc_name): Likewise for floating point condition
 380         codes.
 381         (get_v850_cacheop_name): Likewise for cache-ops.
 382         (get_v850_prefop_name): Likewise for pref-ops.
 383         (disassemble): Use the new accessor functions.
 384
 385 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 386
 387         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 388         immediate for the writeback form of ldraa/ldrab if it is 0.
 389         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 390         * aarch64-opc-2.c: Regenerated.
 391
 392 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 393
 394         * i386-gen.c (operand_type_shorthands): Delete.
 395         (operand_type_init): Expand previous shorthands.
 396         (set_bitfield_from_shorthand): Rename back to ...
 397         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 398         of operand_type_init[].
 399         (set_bitfield): Adjust call to the above function.
 400         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 401         RegXMM, RegYMM, RegZMM): Define.
 402         * i386-reg.tbl: Expand prior shorthands.
 403
 404 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 405
 406         * i386-gen.c (output_i386_opcode): Change order of fields
 407         emitted to output.
 408         * i386-opc.h (struct insn_template): Move operands field.
 409         Convert extension_opcode field to unsigned short.
 410         * i386-tbl.h: Re-generate.
 411
 412 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 413
 414         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 415         of W.
 416         * i386-opc.h (W): Extend comment.
 417         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 418         general purpose variants not allowing for byte operands.
 419         * i386-tbl.h: Re-generate.
 420
 421 2019-10-29  Nick Clifton  <nickc@redhat.com>
 422
 423         * tic30-dis.c (print_branch): Correct size of operand array.
 424
 425 2019-10-29  Nick Clifton  <nickc@redhat.com>
 426
 427         * d30v-dis.c (print_insn): Check that operand index is valid
 428         before attempting to access the operands array.
 429
 430 2019-10-29  Nick Clifton  <nickc@redhat.com>
 431
 432         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 433         locating the bit to be tested.
 434
 435 2019-10-29  Nick Clifton  <nickc@redhat.com>
 436
 437         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 438         values.
 439         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 440         (print_insn_s12z):  Check for illegal size values.
 441
 442 2019-10-28  Nick Clifton  <nickc@redhat.com>
 443
 444         * csky-dis.c (csky_chars_to_number): Check for a negative
 445         count. Use an unsigned integer to construct the return value.
 446
 447 2019-10-28  Nick Clifton  <nickc@redhat.com>
 448
 449         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 450         operand buffer.  Set value to 15 not 13.
 451         (get_register_operand): Use OPERAND_BUFFER_LEN.
 452         (get_indirect_operand): Likewise.
 453         (print_two_operand): Likewise.
 454         (print_three_operand): Likewise.
 455         (print_oar_insn): Likewise.
 456
 457 2019-10-28  Nick Clifton  <nickc@redhat.com>
 458
 459         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 460         (bit_extract_simple): Likewise.
 461         (bit_copy): Likewise.
 462         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 463         index_offset array are not accessed.
 464
 465 2019-10-28  Nick Clifton  <nickc@redhat.com>
 466
 467         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 468         operand.
 469
 470 2019-10-25  Nick Clifton  <nickc@redhat.com>
 471
 472         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 473         access to opcodes.op array element.
 474
 475 2019-10-23  Nick Clifton  <nickc@redhat.com>
 476
 477         * rx-dis.c (get_register_name): Fix spelling typo in error
 478         message.
 479         (get_condition_name, get_flag_name, get_double_register_name)
 480         (get_double_register_high_name, get_double_register_low_name)
 481         (get_double_control_register_name, get_double_condition_name)
 482         (get_opsize_name, get_size_name): Likewise.
 483
 484 2019-10-22  Nick Clifton  <nickc@redhat.com>
 485
 486         * rx-dis.c (get_size_name): New function.  Provides safe
 487         access to name array.
 488         (get_opsize_name): Likewise.
 489         (print_insn_rx): Use the accessor functions.
 490
 491 2019-10-16  Nick Clifton  <nickc@redhat.com>
 492
 493         * rx-dis.c (get_register_name): New function.  Provides safe
 494         access to name array.
 495         (get_condition_name, get_flag_name, get_double_register_name)
 496         (get_double_register_high_name, get_double_register_low_name)
 497         (get_double_control_register_name, get_double_condition_name):
 498         Likewise.
 499         (print_insn_rx): Use the accessor functions.
 500
 501 2019-10-09  Nick Clifton  <nickc@redhat.com>
 502
 503         PR 25041
 504         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 505         instructions.
 506
 507 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 508
 509         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 510         (cmpsd): Likewise. Move EsSeg to other operand.
 511         * opcodes/i386-tbl.h: Re-generate.
 512
 513 2019-09-23  Alan Modra  <amodra@gmail.com>
 514
 515         * m68k-dis.c: Include cpu-m68k.h
 516
 517 2019-09-23  Alan Modra  <amodra@gmail.com>
 518
 519         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 520         "elf/mips.h" earlier.
 521
 522 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 523
 524         PR gas/25012
 525         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 526         with SReg operand.
 527         * i386-tbl.h: Re-generate.
 528
 529 2019-09-18  Alan Modra  <amodra@gmail.com>
 530
 531         * arc-ext.c: Update throughout for bfd section macro changes.
 532
 533 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 534
 535         * Makefile.in: Re-generate.
 536         * configure: Re-generate.
 537
 538 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 539
 540         * riscv-opc.c (riscv_opcodes): Change subset field
 541         to insn_class field for all instructions.
 542         (riscv_insn_types): Likewise.
 543
 544 2019-09-16  Phil Blundell  <pb@pbcl.net>
 545
 546         * configure: Regenerated.
 547
 548 2019-09-10  Miod Vallat  <miod@online.fr>
 549
 550         PR 24982
 551         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 552
 553 2019-09-09  Phil Blundell  <pb@pbcl.net>
 554
 555         binutils 2.33 branch created.
 556
 557 2019-09-03  Nick Clifton  <nickc@redhat.com>
 558
 559         PR 24961
 560         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 561         greater than zero before indexing via (bufcnt -1).
 562
 563 2019-09-03  Nick Clifton  <nickc@redhat.com>
 564
 565         PR 24958
 566         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 567         (MAX_SPEC_REG_NAME_LEN): Define.
 568         (struct mmix_dis_info): Use defined constants for array lengths.
 569         (get_reg_name): New function.
 570         (get_sprec_reg_name): New function.
 571         (print_insn_mmix): Use new functions.
 572
 573 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 574
 575         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 576         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 577         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 578
 579 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 580
 581         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 582         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 583         (aarch64_sys_reg_supported_p): Update checks for the above.
 584
 585 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 586
 587         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 588         cases MVE_SQRSHRL and MVE_UQRSHLL.
 589         (print_insn_mve): Add case for specifier 'k' to check
 590         specific bit of the instruction.
 591
 592 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 593
 594         PR 24854
 595         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 596         encountering an unknown machine type.
 597         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 598         cases return -1 rather than calling abort.
 599
 600 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 601
 602         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 603         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 604         IgnoreSize.
 605         * i386-tbl.h: Re-generate.
 606
 607 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 608
 609         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 610         instructions.
 611
 612 2019-07-30  Mel Chen <mel.chen@sifive.com>
 613
 614         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 615         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 616
 617         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 618         fscsr.
 619
 620 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 621
 622         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 623         and MPY class instructions.
 624         (parse_option): Add nps400 option.
 625         (print_arc_disassembler_options): Add nps400 info.
 626
 627 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 628
 629         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 630         (bspop): Likewise.
 631         (modapp): Likewise.
 632         * arc-opc.c (RAD_CHK): Add.
 633         * arc-tbl.h: Regenerate.
 634
 635 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 636
 637         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 638         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 639
 640 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 641
 642         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 643         instructions as UNPREDICTABLE.
 644
 645 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 646
 647         * bpf-desc.c: Regenerated.
 648
 649 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 650
 651         * i386-gen.c (static_assert): Define.
 652         (main): Use it.
 653         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 654         (Opcode_Modifier_Num): ... this.
 655         (Mem): Delete.
 656
 657 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 658
 659         * i386-gen.c (operand_types): Move RegMem ...
 660         (opcode_modifiers): ... here.
 661         * i386-opc.h (RegMem): Move to opcode modifer enum.
 662         (union i386_operand_type): Move regmem field ...
 663         (struct i386_opcode_modifier): ... here.
 664         * i386-opc.tbl (RegMem): Define.
 665         (mov, movq): Move RegMem on segment, control, debug, and test
 666         register flavors.
 667         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 668         to non-SSE2AVX flavor.
 669         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 670         Move RegMem on register only flavors. Drop IgnoreSize from
 671         legacy encoding flavors.
 672         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 673         flavors.
 674         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 675         register only flavors.
 676         (vmovd): Move RegMem and drop IgnoreSize on register only
 677         flavor. Change opcode and operand order to store form.
 678         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 679
 680 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 681
 682         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 683         entries.
 684         * i386-opc.h (SReg2, SReg3): Replace by ...
 685         (SReg): ... this.
 686         (union i386_operand_type): Replace sreg fields.
 687         * i386-opc.tbl (mov, ): Use SReg.
 688         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 689         register flavors.
 690         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 691         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 692
 693 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 694
 695         * bpf-desc.c: Regenerate.
 696         * bpf-opc.c: Likewise.
 697         * bpf-opc.h: Likewise.
 698
 699 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 700
 701         * bpf-desc.c: Regenerate.
 702         * bpf-opc.c: Likewise.
 703
 704 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 705
 706         * arm-dis.c (print_insn_coprocessor): Rename index to
 707         index_operand.
 708
 709 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 710
 711         * riscv-opc.c (riscv_insn_types): Add r4 type.
 712
 713         * riscv-opc.c (riscv_insn_types): Add b and j type.
 714
 715         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 716         format for sb type and correct s type.
 717
 718 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 719
 720         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 721         SVE FMOV alias of FCPY.
 722
 723 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 724
 725         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 726         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 727
 728 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 729
 730         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 731         registers in an instruction prefixed by MOVPRFX.
 732
 733 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 734
 735         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 736         sve_size_13 icode to account for variant behaviour of
 737         pmull{t,b}.
 738         * aarch64-dis-2.c: Regenerate.
 739         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 740         sve_size_13 icode to account for variant behaviour of
 741         pmull{t,b}.
 742         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 743         (OP_SVE_VVV_Q_D): Add new qualifier.
 744         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 745         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 746         AES and those not.
 747
 748 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 749
 750         * opcodes/i386-gen.c (operand_type_init): Remove
 751         OPERAND_TYPE_VEC_IMM4 entry.
 752         (operand_types): Remove Vec_Imm4.
 753         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 754         (union i386_operand_type): Remove vec_imm4.
 755         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 756         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 757
 758 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 759
 760         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 761         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 762         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 763         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 764         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 765         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 766         * i386-tbl.h: Re-generate.
 767
 768 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 769
 770         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 771         register operands.
 772         * i386-tbl.h: Re-generate.
 773
 774 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 775
 776         * i386-opc.tbl (C): New.
 777         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 778         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 779         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 780         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 781         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 782         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 783         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 784         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 785         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 786         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 787         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 788         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 789         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 790         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 791         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 792         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 793         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 794         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 795         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 796         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 797         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 798         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 799         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 800         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 801         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 802         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 803         flavors.
 804         * i386-tbl.h: Re-generate.
 805
 806 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 807
 808         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 809         register operands.
 810         * i386-tbl.h: Re-generate.
 811
 812 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 813
 814         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 815         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 816         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 817         * i386-tbl.h: Re-generate.
 818
 819 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 820
 821         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 822         Disp8MemShift from register only templates.
 823         * i386-tbl.h: Re-generate.
 824
 825 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 826
 827         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 828         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 829         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 830         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 831         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 832         EVEX_W_0F11_P_3_M_1): Delete.
 833         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 834         EVEX_W_0F11_P_3): New.
 835         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 836         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 837         MOD_EVEX_0F11_PREFIX_3 table entries.
 838         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 839         PREFIX_EVEX_0F11 table entries.
 840         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 841         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 842         EVEX_W_0F11_P_3_M_{0,1} table entries.
 843
 844 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 845
 846         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 847         Delete.
 848
 849 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 850
 851         PR binutils/24719
 852         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 853         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 854         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 855         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 856         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 857         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 858         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 859         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 860         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 861         PREFIX_EVEX_0F38C6_REG_6 entries.
 862         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 863         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 864         EVEX_W_0F38C7_R_6_P_2 entries.
 865         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 866         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 867         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 868         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 869         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 870         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 871         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 872
 873 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 874
 875         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 876         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 877         VEX_LEN_0F2D_P_3): Delete.
 878         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 879         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 880         (prefix_table): ... here.
 881
 882 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 883
 884         * i386-dis.c (Iq): Delete.
 885         (Id): New.
 886         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 887         TBM insns.
 888         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 889         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 890         (OP_E_memory): Also honor needindex when deciding whether an
 891         address size prefix needs printing.
 892         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 893
 894 2019-06-26  Jim Wilson  <jimw@sifive.com>
 895
 896         PR binutils/24739
 897         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 898         Set info->display_endian to info->endian_code.
 899
 900 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 901
 902         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 903         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 904         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 905         OPERAND_TYPE_ACC64 entries.
 906         * i386-init.h: Re-generate.
 907
 908 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 909
 910         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 911         Delete.
 912         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 913         of dqa_mode.
 914         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 915         entries here.
 916         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 917         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 918
 919 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 920
 921         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 922         variables.
 923
 924 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 925
 926         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 927         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 928         movnti.
 929         * i386-opc.tbl (movnti): Add IgnoreSize.
 930         * i386-tbl.h: Re-generate.
 931
 932 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 933
 934         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 935         * i386-tbl.h: Re-generate.
 936
 937 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 938
 939         * i386-dis-evex.h: Break into ...
 940         * i386-dis-evex-len.h: New file.
 941         * i386-dis-evex-mod.h: Likewise.
 942         * i386-dis-evex-prefix.h: Likewise.
 943         * i386-dis-evex-reg.h: Likewise.
 944         * i386-dis-evex-w.h: Likewise.
 945         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 946         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 947         i386-dis-evex-mod.h.
 948
 949 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 950
 951         PR binutils/24700
 952         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 953         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 954         EVEX_W_0F385B_P_2.
 955         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 956         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 957         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 958         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 959         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 960         EVEX_LEN_0F385B_P_2_W_1.
 961         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 962         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 963         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 964         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 965         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 966         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 967         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 968         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 969         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 970         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 971
 972 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 973
 974         PR binutils/24691
 975         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 976         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 977         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 978         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 979         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 980         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 981         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 982         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 983         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 984         EVEX_LEN_0F3A43_P_2_W_1.
 985         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 986         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 987         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 988         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 989         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 990         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 991         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 992         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 993         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 994         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 995         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 996         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 997
 998 2019-06-14  Nick Clifton  <nickc@redhat.com>
 999
1000         * po/fr.po; Updated French translation.
1001
1002 2019-06-13  Stafford Horne  <shorne@gmail.com>
1003
1004         * or1k-asm.c: Regenerated.
1005         * or1k-desc.c: Regenerated.
1006         * or1k-desc.h: Regenerated.
1007         * or1k-dis.c: Regenerated.
1008         * or1k-ibld.c: Regenerated.
1009         * or1k-opc.c: Regenerated.
1010         * or1k-opc.h: Regenerated.
1011         * or1k-opinst.c: Regenerated.
1012
1013 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1014
1015         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1016
1017 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1018
1019         PR binutils/24633
1020         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1021         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1022         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1023         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1024         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1025         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1026         EVEX_LEN_0F3A1B_P_2_W_1.
1027         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1028         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1029         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1030         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1031         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1032         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1033         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1034         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1035
1036 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1037
1038         PR binutils/24626
1039         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1040         EVEX.vvvv when disassembling VEX and EVEX instructions.
1041         (OP_VEX): Set vex.register_specifier to 0 after readding
1042         vex.register_specifier.
1043         (OP_Vex_2src_1): Likewise.
1044         (OP_Vex_2src_2): Likewise.
1045         (OP_LWP_E): Likewise.
1046         (OP_EX_Vex): Don't check vex.register_specifier.
1047         (OP_XMM_Vex): Likewise.
1048
1049 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1050             Lili Cui  <lili.cui@intel.com>
1051
1052         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1053         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1054         instructions.
1055         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1056         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1057         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1058         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1059         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1060         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1061         * i386-init.h: Regenerated.
1062         * i386-tbl.h: Likewise.
1063
1064 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1065             Lili Cui  <lili.cui@intel.com>
1066
1067         * doc/c-i386.texi: Document enqcmd.
1068         * testsuite/gas/i386/enqcmd-intel.d: New file.
1069         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1070         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1071         * testsuite/gas/i386/enqcmd.d: Likewise.
1072         * testsuite/gas/i386/enqcmd.s: Likewise.
1073         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1074         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1075         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1076         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1077         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1078         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1079         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1080         and x86-64-enqcmd.
1081
1082 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1083
1084         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1085
1086 2019-06-03  Alan Modra  <amodra@gmail.com>
1087
1088         * ppc-dis.c (prefix_opcd_indices): Correct size.
1089
1090 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1091
1092         PR gas/24625
1093         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1094         Disp8ShiftVL.
1095         * i386-tbl.h: Regenerated.
1096
1097 2019-05-24  Alan Modra  <amodra@gmail.com>
1098
1099         * po/POTFILES.in: Regenerate.
1100
1101 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1102             Alan Modra  <amodra@gmail.com>
1103
1104         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1105         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1106         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1107         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1108         XTOP>): Define and add entries.
1109         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1110         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1111         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1112         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1113
1114 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1115             Alan Modra  <amodra@gmail.com>
1116
1117         * ppc-dis.c (ppc_opts): Add "future" entry.
1118         (PREFIX_OPCD_SEGS): Define.
1119         (prefix_opcd_indices): New array.
1120         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1121         (lookup_prefix): New function.
1122         (print_insn_powerpc): Handle 64-bit prefix instructions.
1123         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1124         (PMRR, POWERXX): Define.
1125         (prefix_opcodes): New instruction table.
1126         (prefix_num_opcodes): New constant.
1127
1128 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1129
1130         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1131         * configure: Regenerated.
1132         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1133         and cpu/bpf.opc.
1134         (HFILES): Add bpf-desc.h and bpf-opc.h.
1135         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1136         bpf-ibld.c and bpf-opc.c.
1137         (BPF_DEPS): Define.
1138         * Makefile.in: Regenerated.
1139         * disassemble.c (ARCH_bpf): Define.
1140         (disassembler): Add case for bfd_arch_bpf.
1141         (disassemble_init_for_target): Likewise.
1142         (enum epbf_isa_attr): Define.
1143         * disassemble.h: extern print_insn_bpf.
1144         * bpf-asm.c: Generated.
1145         * bpf-opc.h: Likewise.
1146         * bpf-opc.c: Likewise.
1147         * bpf-ibld.c: Likewise.
1148         * bpf-dis.c: Likewise.
1149         * bpf-desc.h: Likewise.
1150         * bpf-desc.c: Likewise.
1151
1152 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1153
1154         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1155         and VMSR with the new operands.
1156
1157 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1158
1159         * arm-dis.c (enum mve_instructions): New enum
1160         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1161         and cneg.
1162         (mve_opcodes): New instructions as above.
1163         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1164         csneg and csel.
1165         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1166
1167 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1168
1169         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1170         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1171         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1172         uqshl, urshrl and urshr.
1173         (is_mve_okay_in_it): Add new instructions to TRUE list.
1174         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1175         (print_insn_mve): Updated to accept new %j,
1176         %<bitfield>m and %<bitfield>n patterns.
1177
1178 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1179
1180         * mips-opc.c (mips_builtin_opcodes): Change source register
1181         constraint for DAUI.
1182
1183 2019-05-20  Nick Clifton  <nickc@redhat.com>
1184
1185         * po/fr.po: Updated French translation.
1186
1187 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1188             Michael Collison <michael.collison@arm.com>
1189
1190         * arm-dis.c (thumb32_opcodes): Add new instructions.
1191         (enum mve_instructions): Likewise.
1192         (enum mve_undefined): Add new reasons.
1193         (is_mve_encoding_conflict): Handle new instructions.
1194         (is_mve_undefined): Likewise.
1195         (is_mve_unpredictable): Likewise.
1196         (print_mve_undefined): Likewise.
1197         (print_mve_size): Likewise.
1198
1199 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1200             Michael Collison <michael.collison@arm.com>
1201
1202         * arm-dis.c (thumb32_opcodes): Add new instructions.
1203         (enum mve_instructions): Likewise.
1204         (is_mve_encoding_conflict): Handle new instructions.
1205         (is_mve_undefined): Likewise.
1206         (is_mve_unpredictable): Likewise.
1207         (print_mve_size): Likewise.
1208
1209 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1210             Michael Collison <michael.collison@arm.com>
1211
1212         * arm-dis.c (thumb32_opcodes): Add new instructions.
1213         (enum mve_instructions): Likewise.
1214         (is_mve_encoding_conflict): Likewise.
1215         (is_mve_unpredictable): Likewise.
1216         (print_mve_size): Likewise.
1217
1218 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1219             Michael Collison <michael.collison@arm.com>
1220
1221         * arm-dis.c (thumb32_opcodes): Add new instructions.
1222         (enum mve_instructions): Likewise.
1223         (is_mve_encoding_conflict): Handle new instructions.
1224         (is_mve_undefined): Likewise.
1225         (is_mve_unpredictable): Likewise.
1226         (print_mve_size): Likewise.
1227
1228 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1229             Michael Collison <michael.collison@arm.com>
1230
1231         * arm-dis.c (thumb32_opcodes): Add new instructions.
1232         (enum mve_instructions): Likewise.
1233         (is_mve_encoding_conflict): Handle new instructions.
1234         (is_mve_undefined): Likewise.
1235         (is_mve_unpredictable): Likewise.
1236         (print_mve_size): Likewise.
1237         (print_insn_mve): Likewise.
1238
1239 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1240             Michael Collison <michael.collison@arm.com>
1241
1242         * arm-dis.c (thumb32_opcodes): Add new instructions.
1243         (print_insn_thumb32): Handle new instructions.
1244
1245 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1246             Michael Collison <michael.collison@arm.com>
1247
1248         * arm-dis.c (enum mve_instructions): Add new instructions.
1249         (enum mve_undefined): Add new reasons.
1250         (is_mve_encoding_conflict): Handle new instructions.
1251         (is_mve_undefined): Likewise.
1252         (is_mve_unpredictable): Likewise.
1253         (print_mve_undefined): Likewise.
1254         (print_mve_size): Likewise.
1255         (print_mve_shift_n): Likewise.
1256         (print_insn_mve): Likewise.
1257
1258 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1259             Michael Collison <michael.collison@arm.com>
1260
1261         * arm-dis.c (enum mve_instructions): Add new instructions.
1262         (is_mve_encoding_conflict): Handle new instructions.
1263         (is_mve_unpredictable): Likewise.
1264         (print_mve_rotate): Likewise.
1265         (print_mve_size): Likewise.
1266         (print_insn_mve): Likewise.
1267
1268 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1269             Michael Collison <michael.collison@arm.com>
1270
1271         * arm-dis.c (enum mve_instructions): Add new instructions.
1272         (is_mve_encoding_conflict): Handle new instructions.
1273         (is_mve_unpredictable): Likewise.
1274         (print_mve_size): Likewise.
1275         (print_insn_mve): Likewise.
1276
1277 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1278             Michael Collison <michael.collison@arm.com>
1279
1280         * arm-dis.c (enum mve_instructions): Add new instructions.
1281         (enum mve_undefined): Add new reasons.
1282         (is_mve_encoding_conflict): Handle new instructions.
1283         (is_mve_undefined): Likewise.
1284         (is_mve_unpredictable): Likewise.
1285         (print_mve_undefined): Likewise.
1286         (print_mve_size): Likewise.
1287         (print_insn_mve): Likewise.
1288
1289 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1290             Michael Collison <michael.collison@arm.com>
1291
1292         * arm-dis.c (enum mve_instructions): Add new instructions.
1293         (is_mve_encoding_conflict): Handle new instructions.
1294         (is_mve_undefined): Likewise.
1295         (is_mve_unpredictable): Likewise.
1296         (print_mve_size): Likewise.
1297         (print_insn_mve): Likewise.
1298
1299 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1300             Michael Collison <michael.collison@arm.com>
1301
1302         * arm-dis.c (enum mve_instructions): Add new instructions.
1303         (enum mve_unpredictable): Add new reasons.
1304         (enum mve_undefined): Likewise.
1305         (is_mve_okay_in_it): Handle new isntructions.
1306         (is_mve_encoding_conflict): Likewise.
1307         (is_mve_undefined): Likewise.
1308         (is_mve_unpredictable): Likewise.
1309         (print_mve_vmov_index): Likewise.
1310         (print_simd_imm8): Likewise.
1311         (print_mve_undefined): Likewise.
1312         (print_mve_unpredictable): Likewise.
1313         (print_mve_size): Likewise.
1314         (print_insn_mve): Likewise.
1315
1316 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1317             Michael Collison <michael.collison@arm.com>
1318
1319         * arm-dis.c (enum mve_instructions): Add new instructions.
1320         (enum mve_unpredictable): Add new reasons.
1321         (enum mve_undefined): Likewise.
1322         (is_mve_encoding_conflict): Handle new instructions.
1323         (is_mve_undefined): Likewise.
1324         (is_mve_unpredictable): Likewise.
1325         (print_mve_undefined): Likewise.
1326         (print_mve_unpredictable): Likewise.
1327         (print_mve_rounding_mode): Likewise.
1328         (print_mve_vcvt_size): Likewise.
1329         (print_mve_size): Likewise.
1330         (print_insn_mve): Likewise.
1331
1332 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1333             Michael Collison <michael.collison@arm.com>
1334
1335         * arm-dis.c (enum mve_instructions): Add new instructions.
1336         (enum mve_unpredictable): Add new reasons.
1337         (enum mve_undefined): Likewise.
1338         (is_mve_undefined): Handle new instructions.
1339         (is_mve_unpredictable): Likewise.
1340         (print_mve_undefined): Likewise.
1341         (print_mve_unpredictable): Likewise.
1342         (print_mve_size): Likewise.
1343         (print_insn_mve): Likewise.
1344
1345 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1346             Michael Collison <michael.collison@arm.com>
1347
1348         * arm-dis.c (enum mve_instructions): Add new instructions.
1349         (enum mve_undefined): Add new reasons.
1350         (insns): Add new instructions.
1351         (is_mve_encoding_conflict):
1352         (print_mve_vld_str_addr): New print function.
1353         (is_mve_undefined): Handle new instructions.
1354         (is_mve_unpredictable): Likewise.
1355         (print_mve_undefined): Likewise.
1356         (print_mve_size): Likewise.
1357         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1358         (print_insn_mve):  Handle new operands.
1359
1360 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1361             Michael Collison <michael.collison@arm.com>
1362
1363         * arm-dis.c (enum mve_instructions): Add new instructions.
1364         (enum mve_unpredictable): Add new reasons.
1365         (is_mve_encoding_conflict): Handle new instructions.
1366         (is_mve_unpredictable): Likewise.
1367         (mve_opcodes): Add new instructions.
1368         (print_mve_unpredictable): Handle new reasons.
1369         (print_mve_register_blocks): New print function.
1370         (print_mve_size): Handle new instructions.
1371         (print_insn_mve): Likewise.
1372
1373 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1374             Michael Collison <michael.collison@arm.com>
1375
1376         * arm-dis.c (enum mve_instructions): Add new instructions.
1377         (enum mve_unpredictable): Add new reasons.
1378         (enum mve_undefined): Likewise.
1379         (is_mve_encoding_conflict): Handle new instructions.
1380         (is_mve_undefined): Likewise.
1381         (is_mve_unpredictable): Likewise.
1382         (coprocessor_opcodes): Move NEON VDUP from here...
1383         (neon_opcodes): ... to here.
1384         (mve_opcodes): Add new instructions.
1385         (print_mve_undefined):  Handle new reasons.
1386         (print_mve_unpredictable): Likewise.
1387         (print_mve_size): Handle new instructions.
1388         (print_insn_neon): Handle vdup.
1389         (print_insn_mve): Handle new operands.
1390
1391 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1392             Michael Collison <michael.collison@arm.com>
1393
1394         * arm-dis.c (enum mve_instructions): Add new instructions.
1395         (enum mve_unpredictable): Add new values.
1396         (mve_opcodes): Add new instructions.
1397         (vec_condnames): New array with vector conditions.
1398         (mve_predicatenames): New array with predicate suffixes.
1399         (mve_vec_sizename): New array with vector sizes.
1400         (enum vpt_pred_state): New enum with vector predication states.
1401         (struct vpt_block): New struct type for vpt blocks.
1402         (vpt_block_state): Global struct to keep track of state.
1403         (mve_extract_pred_mask): New helper function.
1404         (num_instructions_vpt_block): Likewise.
1405         (mark_outside_vpt_block): Likewise.
1406         (mark_inside_vpt_block): Likewise.
1407         (invert_next_predicate_state): Likewise.
1408         (update_next_predicate_state): Likewise.
1409         (update_vpt_block_state): Likewise.
1410         (is_vpt_instruction): Likewise.
1411         (is_mve_encoding_conflict): Add entries for new instructions.
1412         (is_mve_unpredictable): Likewise.
1413         (print_mve_unpredictable): Handle new cases.
1414         (print_instruction_predicate): Likewise.
1415         (print_mve_size): New function.
1416         (print_vec_condition): New function.
1417         (print_insn_mve): Handle vpt blocks and new print operands.
1418
1419 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1420
1421         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1422         8, 14 and 15 for Armv8.1-M Mainline.
1423
1424 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1425             Michael Collison <michael.collison@arm.com>
1426
1427         * arm-dis.c (enum mve_instructions): New enum.
1428         (enum mve_unpredictable): Likewise.
1429         (enum mve_undefined): Likewise.
1430         (struct mopcode32): New struct.
1431         (is_mve_okay_in_it): New function.
1432         (is_mve_architecture): Likewise.
1433         (arm_decode_field): Likewise.
1434         (arm_decode_field_multiple): Likewise.
1435         (is_mve_encoding_conflict): Likewise.
1436         (is_mve_undefined): Likewise.
1437         (is_mve_unpredictable): Likewise.
1438         (print_mve_undefined): Likewise.
1439         (print_mve_unpredictable): Likewise.
1440         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1441         (print_insn_mve): New function.
1442         (print_insn_thumb32): Handle MVE architecture.
1443         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1444
1445 2019-05-10  Nick Clifton  <nickc@redhat.com>
1446
1447         PR 24538
1448         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1449         end of the table prematurely.
1450
1451 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1452
1453         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1454         macros for R6.
1455
1456 2019-05-11  Alan Modra  <amodra@gmail.com>
1457
1458         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1459         when -Mraw is in effect.
1460
1461 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1462
1463         * aarch64-dis-2.c: Regenerate.
1464         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1465         (OP_SVE_BBB): New variant set.
1466         (OP_SVE_DDDD): New variant set.
1467         (OP_SVE_HHH): New variant set.
1468         (OP_SVE_HHHU): New variant set.
1469         (OP_SVE_SSS): New variant set.
1470         (OP_SVE_SSSU): New variant set.
1471         (OP_SVE_SHH): New variant set.
1472         (OP_SVE_SBBU): New variant set.
1473         (OP_SVE_DSS): New variant set.
1474         (OP_SVE_DHHU): New variant set.
1475         (OP_SVE_VMV_HSD_BHS): New variant set.
1476         (OP_SVE_VVU_HSD_BHS): New variant set.
1477         (OP_SVE_VVVU_SD_BH): New variant set.
1478         (OP_SVE_VVVU_BHSD): New variant set.
1479         (OP_SVE_VVV_QHD_DBS): New variant set.
1480         (OP_SVE_VVV_HSD_BHS): New variant set.
1481         (OP_SVE_VVV_HSD_BHS2): New variant set.
1482         (OP_SVE_VVV_BHS_HSD): New variant set.
1483         (OP_SVE_VV_BHS_HSD): New variant set.
1484         (OP_SVE_VVV_SD): New variant set.
1485         (OP_SVE_VVU_BHS_HSD): New variant set.
1486         (OP_SVE_VZVV_SD): New variant set.
1487         (OP_SVE_VZVV_BH): New variant set.
1488         (OP_SVE_VZV_SD): New variant set.
1489         (aarch64_opcode_table): Add sve2 instructions.
1490
1491 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1492
1493         * aarch64-asm-2.c: Regenerated.
1494         * aarch64-dis-2.c: Regenerated.
1495         * aarch64-opc-2.c: Regenerated.
1496         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1497         for SVE_SHLIMM_UNPRED_22.
1498         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1499         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1500         operand.
1501
1502 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1503
1504         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1505         sve_size_tsz_bhs iclass encode.
1506         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1507         sve_size_tsz_bhs iclass decode.
1508
1509 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1510
1511         * aarch64-asm-2.c: Regenerated.
1512         * aarch64-dis-2.c: Regenerated.
1513         * aarch64-opc-2.c: Regenerated.
1514         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1515         for SVE_Zm4_11_INDEX.
1516         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1517         (fields): Handle SVE_i2h field.
1518         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1519         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1520
1521 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1522
1523         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1524         sve_shift_tsz_bhsd iclass encode.
1525         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1526         sve_shift_tsz_bhsd iclass decode.
1527
1528 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1529
1530         * aarch64-asm-2.c: Regenerated.
1531         * aarch64-dis-2.c: Regenerated.
1532         * aarch64-opc-2.c: Regenerated.
1533         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1534         (aarch64_encode_variant_using_iclass): Handle
1535         sve_shift_tsz_hsd iclass encode.
1536         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1537         sve_shift_tsz_hsd iclass decode.
1538         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1539         for SVE_SHRIMM_UNPRED_22.
1540         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1541         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1542         operand.
1543
1544 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1545
1546         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1547         sve_size_013 iclass encode.
1548         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1549         sve_size_013 iclass decode.
1550
1551 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1552
1553         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1554         sve_size_bh iclass encode.
1555         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1556         sve_size_bh iclass decode.
1557
1558 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1559
1560         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1561         sve_size_sd2 iclass encode.
1562         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1563         sve_size_sd2 iclass decode.
1564         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1565         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1566
1567 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1568
1569         * aarch64-asm-2.c: Regenerated.
1570         * aarch64-dis-2.c: Regenerated.
1571         * aarch64-opc-2.c: Regenerated.
1572         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1573         for SVE_ADDR_ZX.
1574         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1575         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1576
1577 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1578
1579         * aarch64-asm-2.c: Regenerated.
1580         * aarch64-dis-2.c: Regenerated.
1581         * aarch64-opc-2.c: Regenerated.
1582         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1583         for SVE_Zm3_11_INDEX.
1584         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1585         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1586         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1587         fields.
1588         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1589
1590 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1591
1592         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1593         sve_size_hsd2 iclass encode.
1594         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1595         sve_size_hsd2 iclass decode.
1596         * aarch64-opc.c (fields): Handle SVE_size field.
1597         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1598
1599 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1600
1601         * aarch64-asm-2.c: Regenerated.
1602         * aarch64-dis-2.c: Regenerated.
1603         * aarch64-opc-2.c: Regenerated.
1604         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1605         for SVE_IMM_ROT3.
1606         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1607         (fields): Handle SVE_rot3 field.
1608         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1609         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1610
1611 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1612
1613         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1614         instructions.
1615
1616 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1617
1618         * aarch64-tbl.h
1619         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1620         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1621         aarch64_feature_sve2bitperm): New feature sets.
1622         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1623         for feature set addresses.
1624         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1625         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1626
1627 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1628             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1629
1630         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1631         argument and set ASE_EVA_R6 appropriately.
1632         (set_default_mips_dis_options): Pass ISA to above.
1633         (parse_mips_dis_option): Likewise.
1634         * mips-opc.c (EVAR6): New macro.
1635         (mips_builtin_opcodes): Add llwpe, scwpe.
1636
1637 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1638
1639         * aarch64-asm-2.c: Regenerated.
1640         * aarch64-dis-2.c: Regenerated.
1641         * aarch64-opc-2.c: Regenerated.
1642         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1643         AARCH64_OPND_TME_UIMM16.
1644         (aarch64_print_operand): Likewise.
1645         * aarch64-tbl.h (QL_IMM_NIL): New.
1646         (TME): New.
1647         (_TME_INSN): New.
1648         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1649
1650 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1651
1652         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1653
1654 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1655             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1656
1657         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1658
1659 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1660
1661         * s12z-opc.h: Add extern "C" bracketing to help
1662         users who wish to use this interface in c++ code.
1663
1664 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1665
1666         * s12z-opc.c (bm_decode): Handle bit map operations with the
1667         "reserved0" mode.
1668
1669 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1670
1671         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1672         specifier.  Add entries for VLDR and VSTR of system registers.
1673         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1674         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1675         of %J and %K format specifier.
1676
1677 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1678
1679         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1680         Add new entries for VSCCLRM instruction.
1681         (print_insn_coprocessor): Handle new %C format control code.
1682
1683 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1684
1685         * arm-dis.c (enum isa): New enum.
1686         (struct sopcode32): New structure.
1687         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1688         set isa field of all current entries to ANY.
1689         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1690         Only match an entry if its isa field allows the current mode.
1691
1692 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1693
1694         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1695         CLRM.
1696         (print_insn_thumb32): Add logic to print %n CLRM register list.
1697
1698 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1699
1700         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1701         and %Q patterns.
1702
1703 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1704
1705         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1706         (print_insn_thumb32): Edit the switch case for %Z.
1707
1708 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1709
1710         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1711
1712 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1713
1714         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1715
1716 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1717
1718         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1719
1720 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1721
1722         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1723         Arm register with r13 and r15 unpredictable.
1724         (thumb32_opcodes): New instructions for bfx and bflx.
1725
1726 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1727
1728         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1729
1730 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1731
1732         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1733
1734 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1735
1736         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1737
1738 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1739
1740         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1741
1742 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1743
1744         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1745         "optr". ("operator" is a reserved word in c++).
1746
1747 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1748
1749         * aarch64-opc.c (aarch64_print_operand): Add case for
1750         AARCH64_OPND_Rt_SP.
1751         (verify_constraints): Likewise.
1752         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1753         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1754         to accept Rt|SP as first operand.
1755         (AARCH64_OPERANDS): Add new Rt_SP.
1756         * aarch64-asm-2.c: Regenerated.
1757         * aarch64-dis-2.c: Regenerated.
1758         * aarch64-opc-2.c: Regenerated.
1759
1760 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1761
1762         * aarch64-asm-2.c: Regenerated.
1763         * aarch64-dis-2.c: Likewise.
1764         * aarch64-opc-2.c: Likewise.
1765         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1766
1767 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1768
1769         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1770
1771 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1772
1773         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1774         * i386-init.h: Regenerated.
1775
1776 2019-04-07  Alan Modra  <amodra@gmail.com>
1777
1778         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1779         op_separator to control printing of spaces, comma and parens
1780         rather than need_comma, need_paren and spaces vars.
1781
1782 2019-04-07  Alan Modra  <amodra@gmail.com>
1783
1784         PR 24421
1785         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1786         (print_insn_neon, print_insn_arm): Likewise.
1787
1788 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1789
1790         * i386-dis-evex.h (evex_table): Updated to support BF16
1791         instructions.
1792         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1793         and EVEX_W_0F3872_P_3.
1794         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1795         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1796         * i386-opc.h (enum): Add CpuAVX512_BF16.
1797         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1798         * i386-opc.tbl: Add AVX512 BF16 instructions.
1799         * i386-init.h: Regenerated.
1800         * i386-tbl.h: Likewise.
1801
1802 2019-04-05  Alan Modra  <amodra@gmail.com>
1803
1804         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1805         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1806         to favour printing of "-" branch hint when using the "y" bit.
1807         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1808
1809 2019-04-05  Alan Modra  <amodra@gmail.com>
1810
1811         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1812         opcode until first operand is output.
1813
1814 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1815
1816         PR gas/24349
1817         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1818         (valid_bo_post_v2): Add support for 'at' branch hints.
1819         (insert_bo): Only error on branch on ctr.
1820         (get_bo_hint_mask): New function.
1821         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1822         for inserting 'at' branch hints.
1823         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1824         for extracting 'at' branch hints.
1825         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1826         (BOE): Delete operand.
1827         (BOM, BOP): New operands.
1828         (RM): Update value.
1829         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1830         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1831         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1832         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1833         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1834         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1835         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1836         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1837         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1838         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1839         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1840         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1841         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1842         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1843         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1844         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1845         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1846         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1847         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1848         bttarl+>: New extended mnemonics.
1849
1850 2019-03-28  Alan Modra  <amodra@gmail.com>
1851
1852         PR 24390
1853         * ppc-opc.c (BTF): Define.
1854         (powerpc_opcodes): Use for mtfsb*.
1855         * ppc-dis.c (print_insn_powerpc): Print fields with both
1856         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1857
1858 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1859
1860         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1861         (mapping_symbol_for_insn): Implement new algorithm.
1862         (print_insn): Remove duplicate code.
1863
1864 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1865
1866         * aarch64-dis.c (print_insn_aarch64):
1867         Implement override.
1868
1869 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1870
1871         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1872         order.
1873
1874 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1875
1876         * aarch64-dis.c (last_stop_offset): New.
1877         (print_insn_aarch64): Use stop_offset.
1878
1879 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1880
1881         PR gas/24359
1882         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1883         CPU_ANY_AVX2_FLAGS.
1884         * i386-init.h: Regenerated.
1885
1886 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1887
1888         PR gas/24348
1889         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1890         vmovdqu16, vmovdqu32 and vmovdqu64.
1891         * i386-tbl.h: Regenerated.
1892
1893 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1894
1895         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1896         from vstrszb, vstrszh, and vstrszf.
1897
1898 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1899
1900         * s390-opc.txt: Add instruction descriptions.
1901
1902 2019-02-08  Jim Wilson  <jimw@sifive.com>
1903
1904         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1905         <bne>: Likewise.
1906
1907 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1908
1909         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1910
1911 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1912
1913         PR binutils/23212
1914         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1915         * aarch64-opc.c (verify_elem_sd): New.
1916         (fields): Add FLD_sz entr.
1917         * aarch64-tbl.h (_SIMD_INSN): New.
1918         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1919         fmulx scalar and vector by element isns.
1920
1921 2019-02-07  Nick Clifton  <nickc@redhat.com>
1922
1923         * po/sv.po: Updated Swedish translation.
1924
1925 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1926
1927         * s390-mkopc.c (main): Accept arch13 as cpu string.
1928         * s390-opc.c: Add new instruction formats and instruction opcode
1929         masks.
1930         * s390-opc.txt: Add new arch13 instructions.
1931
1932 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1933
1934         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1935         (aarch64_opcode): Change encoding for stg, stzg
1936         st2g and st2zg.
1937         * aarch64-asm-2.c: Regenerated.
1938         * aarch64-dis-2.c: Regenerated.
1939         * aarch64-opc-2.c: Regenerated.
1940
1941 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1942
1943         * aarch64-asm-2.c: Regenerated.
1944         * aarch64-dis-2.c: Likewise.
1945         * aarch64-opc-2.c: Likewise.
1946         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1947
1948 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1949             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1950
1951         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1952         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1953         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1954         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1955         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1956         case for ldstgv_indexed.
1957         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1958         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1959         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1960         * aarch64-asm-2.c: Regenerated.
1961         * aarch64-dis-2.c: Regenerated.
1962         * aarch64-opc-2.c: Regenerated.
1963
1964 2019-01-23  Nick Clifton  <nickc@redhat.com>
1965
1966         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1967
1968 2019-01-21  Nick Clifton  <nickc@redhat.com>
1969
1970         * po/de.po: Updated German translation.
1971         * po/uk.po: Updated Ukranian translation.
1972
1973 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1974         * mips-dis.c (mips_arch_choices): Fix typo in
1975         gs464, gs464e and gs264e descriptors.
1976
1977 2019-01-19  Nick Clifton  <nickc@redhat.com>
1978
1979         * configure: Regenerate.
1980         * po/opcodes.pot: Regenerate.
1981
1982 2018-06-24  Nick Clifton  <nickc@redhat.com>
1983
1984         2.32 branch created.
1985
1986 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1987
1988         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1989         if it is null.
1990         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1991         zero.
1992
1993 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1994
1995         * configure: Regenerate.
1996
1997 2019-01-07  Alan Modra  <amodra@gmail.com>
1998
1999         * configure: Regenerate.
2000         * po/POTFILES.in: Regenerate.
2001
2002 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2003
2004         * s12z-opc.c: New file.
2005         * s12z-opc.h: New file.
2006         * s12z-dis.c: Removed all code not directly related to display
2007         of instructions.  Used the interface provided by the new files
2008         instead.
2009         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2010         * Makefile.in: Regenerate.
2011         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2012         * configure: Regenerate.
2013
2014 2019-01-01  Alan Modra  <amodra@gmail.com>
2015
2016         Update year range in copyright notice of all files.
2017
2018 For older changes see ChangeLog-2018
2019 \f
2020 Copyright (C) 2019 Free Software Foundation, Inc.
2021
2022 Copying and distribution of this file, with or without modification,
2023 are permitted in any medium without royalty provided the copyright
2024 notice and this notice are preserved.
2025
2026 Local Variables:
2027 mode: change-log
2028 left-margin: 8
2029 fill-column: 74
2030 version-control: never
2031 End: