1 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
4 * arm-dis.c (print_insn_coprocessor,
5 print_insn_generic_coprocessor): Create wrapper functions around
6 the implementation of the print_insn_coprocessor control codes.
7 (print_insn_coprocessor_1): Original print_insn_coprocessor
8 function that now takes which array to look at as an argument.
9 (print_insn_arm): Use both print_insn_coprocessor and
10 print_insn_generic_coprocessor.
11 (print_insn_thumb32): As above.
13 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
14 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
16 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
17 in reglane special case.
18 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
19 aarch64_find_next_opcode): Account for new instructions.
20 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
21 in reglane special case.
22 * aarch64-opc.c (struct operand_qualifier_data): Add data for
23 new AARCH64_OPND_QLF_S_2H qualifier.
24 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
25 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
26 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
28 (BFLOAT_SVE, BFLOAT): New feature set macros.
29 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
31 (aarch64_opcode_table): Define new instructions bfdot,
32 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
35 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
36 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
38 * aarch64-tbl.h (ARMV8_6): New macro.
40 2019-11-07 Jan Beulich <jbeulich@suse.com>
42 * i386-dis.c (prefix_table): Add mcommit.
43 (rm_table): Add rdpru.
44 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
45 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
46 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
47 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
48 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
49 * i386-opc.tbl (mcommit, rdpru): New.
50 * i386-init.h, i386-tbl.h: Re-generate.
52 2019-11-07 Jan Beulich <jbeulich@suse.com>
54 * i386-dis.c (OP_Mwait): Drop local variable "names", use
56 (OP_Monitor): Drop local variable "op1_names", re-purpose
57 "names" for it instead, and replace former "names" uses by
60 2019-11-07 Jan Beulich <jbeulich@suse.com>
63 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
65 * opcodes/i386-tbl.h: Re-generate.
67 2019-11-05 Jan Beulich <jbeulich@suse.com>
69 * i386-dis.c (OP_Mwaitx): Delete.
70 (prefix_table): Use OP_Mwait for mwaitx entry.
71 (OP_Mwait): Also handle mwaitx.
73 2019-11-05 Jan Beulich <jbeulich@suse.com>
75 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
76 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
77 (prefix_table): Add respective entries.
78 (rm_table): Link to those entries.
80 2019-11-05 Jan Beulich <jbeulich@suse.com>
82 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
83 (REG_0F1C_P_0_MOD_0): ... this.
84 (REG_0F1E_MOD_3): Rename to ...
85 (REG_0F1E_P_1_MOD_3): ... this.
86 (RM_0F01_REG_5): Rename to ...
87 (RM_0F01_REG_5_MOD_3): ... this.
88 (RM_0F01_REG_7): Rename to ...
89 (RM_0F01_REG_7_MOD_3): ... this.
90 (RM_0F1E_MOD_3_REG_7): Rename to ...
91 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
92 (RM_0FAE_REG_6): Rename to ...
93 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
94 (RM_0FAE_REG_7): Rename to ...
95 (RM_0FAE_REG_7_MOD_3): ... this.
96 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
97 (PREFIX_0F01_REG_5_MOD_0): ... this.
98 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
99 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
100 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
101 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
102 (PREFIX_0FAE_REG_0): Rename to ...
103 (PREFIX_0FAE_REG_0_MOD_3): ... this.
104 (PREFIX_0FAE_REG_1): Rename to ...
105 (PREFIX_0FAE_REG_1_MOD_3): ... this.
106 (PREFIX_0FAE_REG_2): Rename to ...
107 (PREFIX_0FAE_REG_2_MOD_3): ... this.
108 (PREFIX_0FAE_REG_3): Rename to ...
109 (PREFIX_0FAE_REG_3_MOD_3): ... this.
110 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
111 (PREFIX_0FAE_REG_4_MOD_0): ... this.
112 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
113 (PREFIX_0FAE_REG_4_MOD_3): ... this.
114 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
115 (PREFIX_0FAE_REG_5_MOD_0): ... this.
116 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
117 (PREFIX_0FAE_REG_5_MOD_3): ... this.
118 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
119 (PREFIX_0FAE_REG_6_MOD_0): ... this.
120 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
121 (PREFIX_0FAE_REG_6_MOD_3): ... this.
122 (PREFIX_0FAE_REG_7): Rename to ...
123 (PREFIX_0FAE_REG_7_MOD_0): ... this.
124 (PREFIX_MOD_0_0FC3): Rename to ...
125 (PREFIX_0FC3_MOD_0): ... this.
126 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
127 (PREFIX_0FC7_REG_6_MOD_0): ... this.
128 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
129 (PREFIX_0FC7_REG_6_MOD_3): ... this.
130 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
131 (PREFIX_0FC7_REG_7_MOD_3): ... this.
132 (reg_table, prefix_table, mod_table, rm_table): Adjust
135 2019-11-04 Nick Clifton <nickc@redhat.com>
137 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
138 of a v850 system register. Move the v850_sreg_names array into
140 (get_v850_reg_name): Likewise for ordinary register names.
141 (get_v850_vreg_name): Likewise for vector register names.
142 (get_v850_cc_name): Likewise for condition codes.
143 * get_v850_float_cc_name): Likewise for floating point condition
145 (get_v850_cacheop_name): Likewise for cache-ops.
146 (get_v850_prefop_name): Likewise for pref-ops.
147 (disassemble): Use the new accessor functions.
149 2019-10-30 Delia Burduv <delia.burduv@arm.com>
151 * aarch64-opc.c (print_immediate_offset_address): Don't print the
152 immediate for the writeback form of ldraa/ldrab if it is 0.
153 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
154 * aarch64-opc-2.c: Regenerated.
156 2019-10-30 Jan Beulich <jbeulich@suse.com>
158 * i386-gen.c (operand_type_shorthands): Delete.
159 (operand_type_init): Expand previous shorthands.
160 (set_bitfield_from_shorthand): Rename back to ...
161 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
162 of operand_type_init[].
163 (set_bitfield): Adjust call to the above function.
164 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
165 RegXMM, RegYMM, RegZMM): Define.
166 * i386-reg.tbl: Expand prior shorthands.
168 2019-10-30 Jan Beulich <jbeulich@suse.com>
170 * i386-gen.c (output_i386_opcode): Change order of fields
172 * i386-opc.h (struct insn_template): Move operands field.
173 Convert extension_opcode field to unsigned short.
174 * i386-tbl.h: Re-generate.
176 2019-10-30 Jan Beulich <jbeulich@suse.com>
178 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
180 * i386-opc.h (W): Extend comment.
181 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
182 general purpose variants not allowing for byte operands.
183 * i386-tbl.h: Re-generate.
185 2019-10-29 Nick Clifton <nickc@redhat.com>
187 * tic30-dis.c (print_branch): Correct size of operand array.
189 2019-10-29 Nick Clifton <nickc@redhat.com>
191 * d30v-dis.c (print_insn): Check that operand index is valid
192 before attempting to access the operands array.
194 2019-10-29 Nick Clifton <nickc@redhat.com>
196 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
197 locating the bit to be tested.
199 2019-10-29 Nick Clifton <nickc@redhat.com>
201 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
203 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
204 (print_insn_s12z): Check for illegal size values.
206 2019-10-28 Nick Clifton <nickc@redhat.com>
208 * csky-dis.c (csky_chars_to_number): Check for a negative
209 count. Use an unsigned integer to construct the return value.
211 2019-10-28 Nick Clifton <nickc@redhat.com>
213 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
214 operand buffer. Set value to 15 not 13.
215 (get_register_operand): Use OPERAND_BUFFER_LEN.
216 (get_indirect_operand): Likewise.
217 (print_two_operand): Likewise.
218 (print_three_operand): Likewise.
219 (print_oar_insn): Likewise.
221 2019-10-28 Nick Clifton <nickc@redhat.com>
223 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
224 (bit_extract_simple): Likewise.
225 (bit_copy): Likewise.
226 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
227 index_offset array are not accessed.
229 2019-10-28 Nick Clifton <nickc@redhat.com>
231 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
234 2019-10-25 Nick Clifton <nickc@redhat.com>
236 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
237 access to opcodes.op array element.
239 2019-10-23 Nick Clifton <nickc@redhat.com>
241 * rx-dis.c (get_register_name): Fix spelling typo in error
243 (get_condition_name, get_flag_name, get_double_register_name)
244 (get_double_register_high_name, get_double_register_low_name)
245 (get_double_control_register_name, get_double_condition_name)
246 (get_opsize_name, get_size_name): Likewise.
248 2019-10-22 Nick Clifton <nickc@redhat.com>
250 * rx-dis.c (get_size_name): New function. Provides safe
251 access to name array.
252 (get_opsize_name): Likewise.
253 (print_insn_rx): Use the accessor functions.
255 2019-10-16 Nick Clifton <nickc@redhat.com>
257 * rx-dis.c (get_register_name): New function. Provides safe
258 access to name array.
259 (get_condition_name, get_flag_name, get_double_register_name)
260 (get_double_register_high_name, get_double_register_low_name)
261 (get_double_control_register_name, get_double_condition_name):
263 (print_insn_rx): Use the accessor functions.
265 2019-10-09 Nick Clifton <nickc@redhat.com>
268 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
271 2019-10-07 Jan Beulich <jbeulich@suse.com>
273 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
274 (cmpsd): Likewise. Move EsSeg to other operand.
275 * opcodes/i386-tbl.h: Re-generate.
277 2019-09-23 Alan Modra <amodra@gmail.com>
279 * m68k-dis.c: Include cpu-m68k.h
281 2019-09-23 Alan Modra <amodra@gmail.com>
283 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
284 "elf/mips.h" earlier.
286 2018-09-20 Jan Beulich <jbeulich@suse.com>
289 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
291 * i386-tbl.h: Re-generate.
293 2019-09-18 Alan Modra <amodra@gmail.com>
295 * arc-ext.c: Update throughout for bfd section macro changes.
297 2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
299 * Makefile.in: Re-generate.
300 * configure: Re-generate.
302 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
304 * riscv-opc.c (riscv_opcodes): Change subset field
305 to insn_class field for all instructions.
306 (riscv_insn_types): Likewise.
308 2019-09-16 Phil Blundell <pb@pbcl.net>
310 * configure: Regenerated.
312 2019-09-10 Miod Vallat <miod@online.fr>
315 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
317 2019-09-09 Phil Blundell <pb@pbcl.net>
319 binutils 2.33 branch created.
321 2019-09-03 Nick Clifton <nickc@redhat.com>
324 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
325 greater than zero before indexing via (bufcnt -1).
327 2019-09-03 Nick Clifton <nickc@redhat.com>
330 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
331 (MAX_SPEC_REG_NAME_LEN): Define.
332 (struct mmix_dis_info): Use defined constants for array lengths.
333 (get_reg_name): New function.
334 (get_sprec_reg_name): New function.
335 (print_insn_mmix): Use new functions.
337 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
339 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
340 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
341 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
343 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
345 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
346 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
347 (aarch64_sys_reg_supported_p): Update checks for the above.
349 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
351 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
352 cases MVE_SQRSHRL and MVE_UQRSHLL.
353 (print_insn_mve): Add case for specifier 'k' to check
354 specific bit of the instruction.
356 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
359 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
360 encountering an unknown machine type.
361 (print_insn_arc): Handle arc_insn_length returning 0. In error
362 cases return -1 rather than calling abort.
364 2019-08-07 Jan Beulich <jbeulich@suse.com>
366 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
367 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
369 * i386-tbl.h: Re-generate.
371 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
373 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
376 2019-07-30 Mel Chen <mel.chen@sifive.com>
378 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
379 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
381 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
384 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
386 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
387 and MPY class instructions.
388 (parse_option): Add nps400 option.
389 (print_arc_disassembler_options): Add nps400 info.
391 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
393 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
396 * arc-opc.c (RAD_CHK): Add.
397 * arc-tbl.h: Regenerate.
399 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
401 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
402 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
404 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
406 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
407 instructions as UNPREDICTABLE.
409 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
411 * bpf-desc.c: Regenerated.
413 2019-07-17 Jan Beulich <jbeulich@suse.com>
415 * i386-gen.c (static_assert): Define.
417 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
418 (Opcode_Modifier_Num): ... this.
421 2019-07-16 Jan Beulich <jbeulich@suse.com>
423 * i386-gen.c (operand_types): Move RegMem ...
424 (opcode_modifiers): ... here.
425 * i386-opc.h (RegMem): Move to opcode modifer enum.
426 (union i386_operand_type): Move regmem field ...
427 (struct i386_opcode_modifier): ... here.
428 * i386-opc.tbl (RegMem): Define.
429 (mov, movq): Move RegMem on segment, control, debug, and test
431 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
432 to non-SSE2AVX flavor.
433 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
434 Move RegMem on register only flavors. Drop IgnoreSize from
435 legacy encoding flavors.
436 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
438 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
439 register only flavors.
440 (vmovd): Move RegMem and drop IgnoreSize on register only
441 flavor. Change opcode and operand order to store form.
442 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
444 2019-07-16 Jan Beulich <jbeulich@suse.com>
446 * i386-gen.c (operand_type_init, operand_types): Replace SReg
448 * i386-opc.h (SReg2, SReg3): Replace by ...
450 (union i386_operand_type): Replace sreg fields.
451 * i386-opc.tbl (mov, ): Use SReg.
452 (push, pop): Likewies. Drop i386 and x86-64 specific segment
454 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
455 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
457 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
459 * bpf-desc.c: Regenerate.
460 * bpf-opc.c: Likewise.
461 * bpf-opc.h: Likewise.
463 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
465 * bpf-desc.c: Regenerate.
466 * bpf-opc.c: Likewise.
468 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
470 * arm-dis.c (print_insn_coprocessor): Rename index to
473 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
475 * riscv-opc.c (riscv_insn_types): Add r4 type.
477 * riscv-opc.c (riscv_insn_types): Add b and j type.
479 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
480 format for sb type and correct s type.
482 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
484 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
485 SVE FMOV alias of FCPY.
487 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
489 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
490 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
492 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
494 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
495 registers in an instruction prefixed by MOVPRFX.
497 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
499 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
500 sve_size_13 icode to account for variant behaviour of
502 * aarch64-dis-2.c: Regenerate.
503 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
504 sve_size_13 icode to account for variant behaviour of
506 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
507 (OP_SVE_VVV_Q_D): Add new qualifier.
508 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
509 (struct aarch64_opcode): Split pmull{t,b} into those requiring
512 2019-07-01 Jan Beulich <jbeulich@suse.com>
514 * opcodes/i386-gen.c (operand_type_init): Remove
515 OPERAND_TYPE_VEC_IMM4 entry.
516 (operand_types): Remove Vec_Imm4.
517 * opcodes/i386-opc.h (Vec_Imm4): Delete.
518 (union i386_operand_type): Remove vec_imm4.
519 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
520 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
522 2019-07-01 Jan Beulich <jbeulich@suse.com>
524 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
525 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
526 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
527 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
528 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
529 monitorx, mwaitx): Drop ImmExt from operand-less forms.
530 * i386-tbl.h: Re-generate.
532 2019-07-01 Jan Beulich <jbeulich@suse.com>
534 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
536 * i386-tbl.h: Re-generate.
538 2019-07-01 Jan Beulich <jbeulich@suse.com>
540 * i386-opc.tbl (C): New.
541 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
542 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
543 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
544 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
545 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
546 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
547 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
548 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
549 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
550 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
551 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
552 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
553 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
554 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
555 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
556 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
557 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
558 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
559 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
560 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
561 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
562 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
563 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
564 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
565 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
566 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
568 * i386-tbl.h: Re-generate.
570 2019-07-01 Jan Beulich <jbeulich@suse.com>
572 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
574 * i386-tbl.h: Re-generate.
576 2019-07-01 Jan Beulich <jbeulich@suse.com>
578 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
579 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
580 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
581 * i386-tbl.h: Re-generate.
583 2019-07-01 Jan Beulich <jbeulich@suse.com>
585 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
586 Disp8MemShift from register only templates.
587 * i386-tbl.h: Re-generate.
589 2019-07-01 Jan Beulich <jbeulich@suse.com>
591 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
592 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
593 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
594 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
595 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
596 EVEX_W_0F11_P_3_M_1): Delete.
597 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
598 EVEX_W_0F11_P_3): New.
599 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
600 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
601 MOD_EVEX_0F11_PREFIX_3 table entries.
602 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
603 PREFIX_EVEX_0F11 table entries.
604 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
605 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
606 EVEX_W_0F11_P_3_M_{0,1} table entries.
608 2019-07-01 Jan Beulich <jbeulich@suse.com>
610 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
613 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
616 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
617 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
618 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
619 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
620 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
621 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
622 EVEX_LEN_0F38C7_R_6_P_2_W_1.
623 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
624 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
625 PREFIX_EVEX_0F38C6_REG_6 entries.
626 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
627 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
628 EVEX_W_0F38C7_R_6_P_2 entries.
629 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
630 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
631 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
632 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
633 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
634 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
635 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
637 2019-06-27 Jan Beulich <jbeulich@suse.com>
639 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
640 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
641 VEX_LEN_0F2D_P_3): Delete.
642 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
643 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
644 (prefix_table): ... here.
646 2019-06-27 Jan Beulich <jbeulich@suse.com>
648 * i386-dis.c (Iq): Delete.
650 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
652 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
653 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
654 (OP_E_memory): Also honor needindex when deciding whether an
655 address size prefix needs printing.
656 (OP_I): Remove handling of q_mode. Add handling of d_mode.
658 2019-06-26 Jim Wilson <jimw@sifive.com>
661 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
662 Set info->display_endian to info->endian_code.
664 2019-06-25 Jan Beulich <jbeulich@suse.com>
666 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
667 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
668 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
669 OPERAND_TYPE_ACC64 entries.
670 * i386-init.h: Re-generate.
672 2019-06-25 Jan Beulich <jbeulich@suse.com>
674 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
676 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
678 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
680 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
681 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
683 2019-06-25 Jan Beulich <jbeulich@suse.com>
685 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
688 2019-06-25 Jan Beulich <jbeulich@suse.com>
690 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
691 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
693 * i386-opc.tbl (movnti): Add IgnoreSize.
694 * i386-tbl.h: Re-generate.
696 2019-06-25 Jan Beulich <jbeulich@suse.com>
698 * i386-opc.tbl (and): Mark Imm8S form for optimization.
699 * i386-tbl.h: Re-generate.
701 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
703 * i386-dis-evex.h: Break into ...
704 * i386-dis-evex-len.h: New file.
705 * i386-dis-evex-mod.h: Likewise.
706 * i386-dis-evex-prefix.h: Likewise.
707 * i386-dis-evex-reg.h: Likewise.
708 * i386-dis-evex-w.h: Likewise.
709 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
710 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
713 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
716 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
717 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
719 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
720 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
721 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
722 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
723 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
724 EVEX_LEN_0F385B_P_2_W_1.
725 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
726 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
727 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
728 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
729 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
730 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
731 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
732 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
733 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
734 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
736 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
739 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
740 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
741 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
742 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
743 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
744 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
745 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
746 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
747 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
748 EVEX_LEN_0F3A43_P_2_W_1.
749 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
750 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
751 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
752 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
753 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
754 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
755 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
756 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
757 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
758 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
759 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
760 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
762 2019-06-14 Nick Clifton <nickc@redhat.com>
764 * po/fr.po; Updated French translation.
766 2019-06-13 Stafford Horne <shorne@gmail.com>
768 * or1k-asm.c: Regenerated.
769 * or1k-desc.c: Regenerated.
770 * or1k-desc.h: Regenerated.
771 * or1k-dis.c: Regenerated.
772 * or1k-ibld.c: Regenerated.
773 * or1k-opc.c: Regenerated.
774 * or1k-opc.h: Regenerated.
775 * or1k-opinst.c: Regenerated.
777 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
779 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
781 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
784 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
785 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
786 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
787 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
788 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
789 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
790 EVEX_LEN_0F3A1B_P_2_W_1.
791 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
792 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
793 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
794 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
795 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
796 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
797 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
798 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
800 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
803 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
804 EVEX.vvvv when disassembling VEX and EVEX instructions.
805 (OP_VEX): Set vex.register_specifier to 0 after readding
806 vex.register_specifier.
807 (OP_Vex_2src_1): Likewise.
808 (OP_Vex_2src_2): Likewise.
809 (OP_LWP_E): Likewise.
810 (OP_EX_Vex): Don't check vex.register_specifier.
811 (OP_XMM_Vex): Likewise.
813 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
814 Lili Cui <lili.cui@intel.com>
816 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
817 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
819 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
820 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
821 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
822 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
823 (i386_cpu_flags): Add cpuavx512_vp2intersect.
824 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
825 * i386-init.h: Regenerated.
826 * i386-tbl.h: Likewise.
828 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
829 Lili Cui <lili.cui@intel.com>
831 * doc/c-i386.texi: Document enqcmd.
832 * testsuite/gas/i386/enqcmd-intel.d: New file.
833 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
834 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
835 * testsuite/gas/i386/enqcmd.d: Likewise.
836 * testsuite/gas/i386/enqcmd.s: Likewise.
837 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
838 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
839 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
840 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
841 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
842 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
843 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
846 2019-06-04 Alan Hayward <alan.hayward@arm.com>
848 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
850 2019-06-03 Alan Modra <amodra@gmail.com>
852 * ppc-dis.c (prefix_opcd_indices): Correct size.
854 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
857 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
859 * i386-tbl.h: Regenerated.
861 2019-05-24 Alan Modra <amodra@gmail.com>
863 * po/POTFILES.in: Regenerate.
865 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
866 Alan Modra <amodra@gmail.com>
868 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
869 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
870 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
871 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
872 XTOP>): Define and add entries.
873 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
874 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
875 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
876 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
878 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
879 Alan Modra <amodra@gmail.com>
881 * ppc-dis.c (ppc_opts): Add "future" entry.
882 (PREFIX_OPCD_SEGS): Define.
883 (prefix_opcd_indices): New array.
884 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
885 (lookup_prefix): New function.
886 (print_insn_powerpc): Handle 64-bit prefix instructions.
887 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
888 (PMRR, POWERXX): Define.
889 (prefix_opcodes): New instruction table.
890 (prefix_num_opcodes): New constant.
892 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
894 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
895 * configure: Regenerated.
896 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
898 (HFILES): Add bpf-desc.h and bpf-opc.h.
899 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
900 bpf-ibld.c and bpf-opc.c.
902 * Makefile.in: Regenerated.
903 * disassemble.c (ARCH_bpf): Define.
904 (disassembler): Add case for bfd_arch_bpf.
905 (disassemble_init_for_target): Likewise.
906 (enum epbf_isa_attr): Define.
907 * disassemble.h: extern print_insn_bpf.
908 * bpf-asm.c: Generated.
909 * bpf-opc.h: Likewise.
910 * bpf-opc.c: Likewise.
911 * bpf-ibld.c: Likewise.
912 * bpf-dis.c: Likewise.
913 * bpf-desc.h: Likewise.
914 * bpf-desc.c: Likewise.
916 2019-05-21 Sudakshina Das <sudi.das@arm.com>
918 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
919 and VMSR with the new operands.
921 2019-05-21 Sudakshina Das <sudi.das@arm.com>
923 * arm-dis.c (enum mve_instructions): New enum
924 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
926 (mve_opcodes): New instructions as above.
927 (is_mve_encoding_conflict): Add cases for csinc, csinv,
929 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
931 2019-05-21 Sudakshina Das <sudi.das@arm.com>
933 * arm-dis.c (emun mve_instructions): Updated for new instructions.
934 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
935 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
936 uqshl, urshrl and urshr.
937 (is_mve_okay_in_it): Add new instructions to TRUE list.
938 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
939 (print_insn_mve): Updated to accept new %j,
940 %<bitfield>m and %<bitfield>n patterns.
942 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
944 * mips-opc.c (mips_builtin_opcodes): Change source register
947 2019-05-20 Nick Clifton <nickc@redhat.com>
949 * po/fr.po: Updated French translation.
951 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
952 Michael Collison <michael.collison@arm.com>
954 * arm-dis.c (thumb32_opcodes): Add new instructions.
955 (enum mve_instructions): Likewise.
956 (enum mve_undefined): Add new reasons.
957 (is_mve_encoding_conflict): Handle new instructions.
958 (is_mve_undefined): Likewise.
959 (is_mve_unpredictable): Likewise.
960 (print_mve_undefined): Likewise.
961 (print_mve_size): Likewise.
963 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
964 Michael Collison <michael.collison@arm.com>
966 * arm-dis.c (thumb32_opcodes): Add new instructions.
967 (enum mve_instructions): Likewise.
968 (is_mve_encoding_conflict): Handle new instructions.
969 (is_mve_undefined): Likewise.
970 (is_mve_unpredictable): Likewise.
971 (print_mve_size): Likewise.
973 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
974 Michael Collison <michael.collison@arm.com>
976 * arm-dis.c (thumb32_opcodes): Add new instructions.
977 (enum mve_instructions): Likewise.
978 (is_mve_encoding_conflict): Likewise.
979 (is_mve_unpredictable): Likewise.
980 (print_mve_size): Likewise.
982 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
983 Michael Collison <michael.collison@arm.com>
985 * arm-dis.c (thumb32_opcodes): Add new instructions.
986 (enum mve_instructions): Likewise.
987 (is_mve_encoding_conflict): Handle new instructions.
988 (is_mve_undefined): Likewise.
989 (is_mve_unpredictable): Likewise.
990 (print_mve_size): Likewise.
992 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
993 Michael Collison <michael.collison@arm.com>
995 * arm-dis.c (thumb32_opcodes): Add new instructions.
996 (enum mve_instructions): Likewise.
997 (is_mve_encoding_conflict): Handle new instructions.
998 (is_mve_undefined): Likewise.
999 (is_mve_unpredictable): Likewise.
1000 (print_mve_size): Likewise.
1001 (print_insn_mve): Likewise.
1003 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1004 Michael Collison <michael.collison@arm.com>
1006 * arm-dis.c (thumb32_opcodes): Add new instructions.
1007 (print_insn_thumb32): Handle new instructions.
1009 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1010 Michael Collison <michael.collison@arm.com>
1012 * arm-dis.c (enum mve_instructions): Add new instructions.
1013 (enum mve_undefined): Add new reasons.
1014 (is_mve_encoding_conflict): Handle new instructions.
1015 (is_mve_undefined): Likewise.
1016 (is_mve_unpredictable): Likewise.
1017 (print_mve_undefined): Likewise.
1018 (print_mve_size): Likewise.
1019 (print_mve_shift_n): Likewise.
1020 (print_insn_mve): Likewise.
1022 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1023 Michael Collison <michael.collison@arm.com>
1025 * arm-dis.c (enum mve_instructions): Add new instructions.
1026 (is_mve_encoding_conflict): Handle new instructions.
1027 (is_mve_unpredictable): Likewise.
1028 (print_mve_rotate): Likewise.
1029 (print_mve_size): Likewise.
1030 (print_insn_mve): Likewise.
1032 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1033 Michael Collison <michael.collison@arm.com>
1035 * arm-dis.c (enum mve_instructions): Add new instructions.
1036 (is_mve_encoding_conflict): Handle new instructions.
1037 (is_mve_unpredictable): Likewise.
1038 (print_mve_size): Likewise.
1039 (print_insn_mve): Likewise.
1041 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1042 Michael Collison <michael.collison@arm.com>
1044 * arm-dis.c (enum mve_instructions): Add new instructions.
1045 (enum mve_undefined): Add new reasons.
1046 (is_mve_encoding_conflict): Handle new instructions.
1047 (is_mve_undefined): Likewise.
1048 (is_mve_unpredictable): Likewise.
1049 (print_mve_undefined): Likewise.
1050 (print_mve_size): Likewise.
1051 (print_insn_mve): Likewise.
1053 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1054 Michael Collison <michael.collison@arm.com>
1056 * arm-dis.c (enum mve_instructions): Add new instructions.
1057 (is_mve_encoding_conflict): Handle new instructions.
1058 (is_mve_undefined): Likewise.
1059 (is_mve_unpredictable): Likewise.
1060 (print_mve_size): Likewise.
1061 (print_insn_mve): Likewise.
1063 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1064 Michael Collison <michael.collison@arm.com>
1066 * arm-dis.c (enum mve_instructions): Add new instructions.
1067 (enum mve_unpredictable): Add new reasons.
1068 (enum mve_undefined): Likewise.
1069 (is_mve_okay_in_it): Handle new isntructions.
1070 (is_mve_encoding_conflict): Likewise.
1071 (is_mve_undefined): Likewise.
1072 (is_mve_unpredictable): Likewise.
1073 (print_mve_vmov_index): Likewise.
1074 (print_simd_imm8): Likewise.
1075 (print_mve_undefined): Likewise.
1076 (print_mve_unpredictable): Likewise.
1077 (print_mve_size): Likewise.
1078 (print_insn_mve): Likewise.
1080 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1081 Michael Collison <michael.collison@arm.com>
1083 * arm-dis.c (enum mve_instructions): Add new instructions.
1084 (enum mve_unpredictable): Add new reasons.
1085 (enum mve_undefined): Likewise.
1086 (is_mve_encoding_conflict): Handle new instructions.
1087 (is_mve_undefined): Likewise.
1088 (is_mve_unpredictable): Likewise.
1089 (print_mve_undefined): Likewise.
1090 (print_mve_unpredictable): Likewise.
1091 (print_mve_rounding_mode): Likewise.
1092 (print_mve_vcvt_size): Likewise.
1093 (print_mve_size): Likewise.
1094 (print_insn_mve): Likewise.
1096 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1097 Michael Collison <michael.collison@arm.com>
1099 * arm-dis.c (enum mve_instructions): Add new instructions.
1100 (enum mve_unpredictable): Add new reasons.
1101 (enum mve_undefined): Likewise.
1102 (is_mve_undefined): Handle new instructions.
1103 (is_mve_unpredictable): Likewise.
1104 (print_mve_undefined): Likewise.
1105 (print_mve_unpredictable): Likewise.
1106 (print_mve_size): Likewise.
1107 (print_insn_mve): Likewise.
1109 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1110 Michael Collison <michael.collison@arm.com>
1112 * arm-dis.c (enum mve_instructions): Add new instructions.
1113 (enum mve_undefined): Add new reasons.
1114 (insns): Add new instructions.
1115 (is_mve_encoding_conflict):
1116 (print_mve_vld_str_addr): New print function.
1117 (is_mve_undefined): Handle new instructions.
1118 (is_mve_unpredictable): Likewise.
1119 (print_mve_undefined): Likewise.
1120 (print_mve_size): Likewise.
1121 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1122 (print_insn_mve): Handle new operands.
1124 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1125 Michael Collison <michael.collison@arm.com>
1127 * arm-dis.c (enum mve_instructions): Add new instructions.
1128 (enum mve_unpredictable): Add new reasons.
1129 (is_mve_encoding_conflict): Handle new instructions.
1130 (is_mve_unpredictable): Likewise.
1131 (mve_opcodes): Add new instructions.
1132 (print_mve_unpredictable): Handle new reasons.
1133 (print_mve_register_blocks): New print function.
1134 (print_mve_size): Handle new instructions.
1135 (print_insn_mve): Likewise.
1137 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1138 Michael Collison <michael.collison@arm.com>
1140 * arm-dis.c (enum mve_instructions): Add new instructions.
1141 (enum mve_unpredictable): Add new reasons.
1142 (enum mve_undefined): Likewise.
1143 (is_mve_encoding_conflict): Handle new instructions.
1144 (is_mve_undefined): Likewise.
1145 (is_mve_unpredictable): Likewise.
1146 (coprocessor_opcodes): Move NEON VDUP from here...
1147 (neon_opcodes): ... to here.
1148 (mve_opcodes): Add new instructions.
1149 (print_mve_undefined): Handle new reasons.
1150 (print_mve_unpredictable): Likewise.
1151 (print_mve_size): Handle new instructions.
1152 (print_insn_neon): Handle vdup.
1153 (print_insn_mve): Handle new operands.
1155 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1156 Michael Collison <michael.collison@arm.com>
1158 * arm-dis.c (enum mve_instructions): Add new instructions.
1159 (enum mve_unpredictable): Add new values.
1160 (mve_opcodes): Add new instructions.
1161 (vec_condnames): New array with vector conditions.
1162 (mve_predicatenames): New array with predicate suffixes.
1163 (mve_vec_sizename): New array with vector sizes.
1164 (enum vpt_pred_state): New enum with vector predication states.
1165 (struct vpt_block): New struct type for vpt blocks.
1166 (vpt_block_state): Global struct to keep track of state.
1167 (mve_extract_pred_mask): New helper function.
1168 (num_instructions_vpt_block): Likewise.
1169 (mark_outside_vpt_block): Likewise.
1170 (mark_inside_vpt_block): Likewise.
1171 (invert_next_predicate_state): Likewise.
1172 (update_next_predicate_state): Likewise.
1173 (update_vpt_block_state): Likewise.
1174 (is_vpt_instruction): Likewise.
1175 (is_mve_encoding_conflict): Add entries for new instructions.
1176 (is_mve_unpredictable): Likewise.
1177 (print_mve_unpredictable): Handle new cases.
1178 (print_instruction_predicate): Likewise.
1179 (print_mve_size): New function.
1180 (print_vec_condition): New function.
1181 (print_insn_mve): Handle vpt blocks and new print operands.
1183 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1185 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1186 8, 14 and 15 for Armv8.1-M Mainline.
1188 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1189 Michael Collison <michael.collison@arm.com>
1191 * arm-dis.c (enum mve_instructions): New enum.
1192 (enum mve_unpredictable): Likewise.
1193 (enum mve_undefined): Likewise.
1194 (struct mopcode32): New struct.
1195 (is_mve_okay_in_it): New function.
1196 (is_mve_architecture): Likewise.
1197 (arm_decode_field): Likewise.
1198 (arm_decode_field_multiple): Likewise.
1199 (is_mve_encoding_conflict): Likewise.
1200 (is_mve_undefined): Likewise.
1201 (is_mve_unpredictable): Likewise.
1202 (print_mve_undefined): Likewise.
1203 (print_mve_unpredictable): Likewise.
1204 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1205 (print_insn_mve): New function.
1206 (print_insn_thumb32): Handle MVE architecture.
1207 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1209 2019-05-10 Nick Clifton <nickc@redhat.com>
1212 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1213 end of the table prematurely.
1215 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1217 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1220 2019-05-11 Alan Modra <amodra@gmail.com>
1222 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1223 when -Mraw is in effect.
1225 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1227 * aarch64-dis-2.c: Regenerate.
1228 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1229 (OP_SVE_BBB): New variant set.
1230 (OP_SVE_DDDD): New variant set.
1231 (OP_SVE_HHH): New variant set.
1232 (OP_SVE_HHHU): New variant set.
1233 (OP_SVE_SSS): New variant set.
1234 (OP_SVE_SSSU): New variant set.
1235 (OP_SVE_SHH): New variant set.
1236 (OP_SVE_SBBU): New variant set.
1237 (OP_SVE_DSS): New variant set.
1238 (OP_SVE_DHHU): New variant set.
1239 (OP_SVE_VMV_HSD_BHS): New variant set.
1240 (OP_SVE_VVU_HSD_BHS): New variant set.
1241 (OP_SVE_VVVU_SD_BH): New variant set.
1242 (OP_SVE_VVVU_BHSD): New variant set.
1243 (OP_SVE_VVV_QHD_DBS): New variant set.
1244 (OP_SVE_VVV_HSD_BHS): New variant set.
1245 (OP_SVE_VVV_HSD_BHS2): New variant set.
1246 (OP_SVE_VVV_BHS_HSD): New variant set.
1247 (OP_SVE_VV_BHS_HSD): New variant set.
1248 (OP_SVE_VVV_SD): New variant set.
1249 (OP_SVE_VVU_BHS_HSD): New variant set.
1250 (OP_SVE_VZVV_SD): New variant set.
1251 (OP_SVE_VZVV_BH): New variant set.
1252 (OP_SVE_VZV_SD): New variant set.
1253 (aarch64_opcode_table): Add sve2 instructions.
1255 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1257 * aarch64-asm-2.c: Regenerated.
1258 * aarch64-dis-2.c: Regenerated.
1259 * aarch64-opc-2.c: Regenerated.
1260 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1261 for SVE_SHLIMM_UNPRED_22.
1262 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1263 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1266 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1268 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1269 sve_size_tsz_bhs iclass encode.
1270 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1271 sve_size_tsz_bhs iclass decode.
1273 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1275 * aarch64-asm-2.c: Regenerated.
1276 * aarch64-dis-2.c: Regenerated.
1277 * aarch64-opc-2.c: Regenerated.
1278 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1279 for SVE_Zm4_11_INDEX.
1280 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1281 (fields): Handle SVE_i2h field.
1282 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1283 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1285 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1287 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1288 sve_shift_tsz_bhsd iclass encode.
1289 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1290 sve_shift_tsz_bhsd iclass decode.
1292 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1294 * aarch64-asm-2.c: Regenerated.
1295 * aarch64-dis-2.c: Regenerated.
1296 * aarch64-opc-2.c: Regenerated.
1297 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1298 (aarch64_encode_variant_using_iclass): Handle
1299 sve_shift_tsz_hsd iclass encode.
1300 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1301 sve_shift_tsz_hsd iclass decode.
1302 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1303 for SVE_SHRIMM_UNPRED_22.
1304 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1305 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1308 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1310 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1311 sve_size_013 iclass encode.
1312 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1313 sve_size_013 iclass decode.
1315 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1317 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1318 sve_size_bh iclass encode.
1319 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1320 sve_size_bh iclass decode.
1322 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1324 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1325 sve_size_sd2 iclass encode.
1326 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1327 sve_size_sd2 iclass decode.
1328 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1329 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1331 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1333 * aarch64-asm-2.c: Regenerated.
1334 * aarch64-dis-2.c: Regenerated.
1335 * aarch64-opc-2.c: Regenerated.
1336 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1338 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1339 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1341 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1343 * aarch64-asm-2.c: Regenerated.
1344 * aarch64-dis-2.c: Regenerated.
1345 * aarch64-opc-2.c: Regenerated.
1346 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1347 for SVE_Zm3_11_INDEX.
1348 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1349 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1350 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1352 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1354 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1356 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1357 sve_size_hsd2 iclass encode.
1358 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1359 sve_size_hsd2 iclass decode.
1360 * aarch64-opc.c (fields): Handle SVE_size field.
1361 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1363 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1365 * aarch64-asm-2.c: Regenerated.
1366 * aarch64-dis-2.c: Regenerated.
1367 * aarch64-opc-2.c: Regenerated.
1368 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1370 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1371 (fields): Handle SVE_rot3 field.
1372 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1373 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1375 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1377 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1380 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1383 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1384 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1385 aarch64_feature_sve2bitperm): New feature sets.
1386 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1387 for feature set addresses.
1388 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1389 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1391 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1392 Faraz Shahbazker <fshahbazker@wavecomp.com>
1394 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1395 argument and set ASE_EVA_R6 appropriately.
1396 (set_default_mips_dis_options): Pass ISA to above.
1397 (parse_mips_dis_option): Likewise.
1398 * mips-opc.c (EVAR6): New macro.
1399 (mips_builtin_opcodes): Add llwpe, scwpe.
1401 2019-05-01 Sudakshina Das <sudi.das@arm.com>
1403 * aarch64-asm-2.c: Regenerated.
1404 * aarch64-dis-2.c: Regenerated.
1405 * aarch64-opc-2.c: Regenerated.
1406 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1407 AARCH64_OPND_TME_UIMM16.
1408 (aarch64_print_operand): Likewise.
1409 * aarch64-tbl.h (QL_IMM_NIL): New.
1412 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1414 2019-04-29 John Darrington <john@darrington.wattle.id.au>
1416 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1418 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1419 Faraz Shahbazker <fshahbazker@wavecomp.com>
1421 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1423 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1425 * s12z-opc.h: Add extern "C" bracketing to help
1426 users who wish to use this interface in c++ code.
1428 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1430 * s12z-opc.c (bm_decode): Handle bit map operations with the
1433 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1435 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1436 specifier. Add entries for VLDR and VSTR of system registers.
1437 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1438 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1439 of %J and %K format specifier.
1441 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1443 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1444 Add new entries for VSCCLRM instruction.
1445 (print_insn_coprocessor): Handle new %C format control code.
1447 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1449 * arm-dis.c (enum isa): New enum.
1450 (struct sopcode32): New structure.
1451 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1452 set isa field of all current entries to ANY.
1453 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1454 Only match an entry if its isa field allows the current mode.
1456 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1458 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1460 (print_insn_thumb32): Add logic to print %n CLRM register list.
1462 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1464 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1467 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1469 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1470 (print_insn_thumb32): Edit the switch case for %Z.
1472 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1474 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1476 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1478 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1480 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1482 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1484 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1486 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1487 Arm register with r13 and r15 unpredictable.
1488 (thumb32_opcodes): New instructions for bfx and bflx.
1490 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1492 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1494 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1496 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1498 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1500 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1502 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1504 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1506 2019-04-12 John Darrington <john@darrington.wattle.id.au>
1508 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1509 "optr". ("operator" is a reserved word in c++).
1511 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1513 * aarch64-opc.c (aarch64_print_operand): Add case for
1515 (verify_constraints): Likewise.
1516 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1517 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1518 to accept Rt|SP as first operand.
1519 (AARCH64_OPERANDS): Add new Rt_SP.
1520 * aarch64-asm-2.c: Regenerated.
1521 * aarch64-dis-2.c: Regenerated.
1522 * aarch64-opc-2.c: Regenerated.
1524 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1526 * aarch64-asm-2.c: Regenerated.
1527 * aarch64-dis-2.c: Likewise.
1528 * aarch64-opc-2.c: Likewise.
1529 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1531 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1533 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1535 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1537 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1538 * i386-init.h: Regenerated.
1540 2019-04-07 Alan Modra <amodra@gmail.com>
1542 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1543 op_separator to control printing of spaces, comma and parens
1544 rather than need_comma, need_paren and spaces vars.
1546 2019-04-07 Alan Modra <amodra@gmail.com>
1549 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1550 (print_insn_neon, print_insn_arm): Likewise.
1552 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1554 * i386-dis-evex.h (evex_table): Updated to support BF16
1556 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1557 and EVEX_W_0F3872_P_3.
1558 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1559 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1560 * i386-opc.h (enum): Add CpuAVX512_BF16.
1561 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1562 * i386-opc.tbl: Add AVX512 BF16 instructions.
1563 * i386-init.h: Regenerated.
1564 * i386-tbl.h: Likewise.
1566 2019-04-05 Alan Modra <amodra@gmail.com>
1568 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1569 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1570 to favour printing of "-" branch hint when using the "y" bit.
1571 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1573 2019-04-05 Alan Modra <amodra@gmail.com>
1575 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1576 opcode until first operand is output.
1578 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1581 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1582 (valid_bo_post_v2): Add support for 'at' branch hints.
1583 (insert_bo): Only error on branch on ctr.
1584 (get_bo_hint_mask): New function.
1585 (insert_boe): Add new 'branch_taken' formal argument. Add support
1586 for inserting 'at' branch hints.
1587 (extract_boe): Add new 'branch_taken' formal argument. Add support
1588 for extracting 'at' branch hints.
1589 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1590 (BOE): Delete operand.
1591 (BOM, BOP): New operands.
1593 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1594 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1595 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1596 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1597 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1598 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1599 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1600 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1601 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1602 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1603 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1604 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1605 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1606 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1607 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1608 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1609 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1610 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1611 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1612 bttarl+>: New extended mnemonics.
1614 2019-03-28 Alan Modra <amodra@gmail.com>
1617 * ppc-opc.c (BTF): Define.
1618 (powerpc_opcodes): Use for mtfsb*.
1619 * ppc-dis.c (print_insn_powerpc): Print fields with both
1620 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1622 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1624 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1625 (mapping_symbol_for_insn): Implement new algorithm.
1626 (print_insn): Remove duplicate code.
1628 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1630 * aarch64-dis.c (print_insn_aarch64):
1633 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1635 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1638 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1640 * aarch64-dis.c (last_stop_offset): New.
1641 (print_insn_aarch64): Use stop_offset.
1643 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1646 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1648 * i386-init.h: Regenerated.
1650 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1653 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1654 vmovdqu16, vmovdqu32 and vmovdqu64.
1655 * i386-tbl.h: Regenerated.
1657 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1659 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1660 from vstrszb, vstrszh, and vstrszf.
1662 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1664 * s390-opc.txt: Add instruction descriptions.
1666 2019-02-08 Jim Wilson <jimw@sifive.com>
1668 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1671 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1673 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1675 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1678 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1679 * aarch64-opc.c (verify_elem_sd): New.
1680 (fields): Add FLD_sz entr.
1681 * aarch64-tbl.h (_SIMD_INSN): New.
1682 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1683 fmulx scalar and vector by element isns.
1685 2019-02-07 Nick Clifton <nickc@redhat.com>
1687 * po/sv.po: Updated Swedish translation.
1689 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1691 * s390-mkopc.c (main): Accept arch13 as cpu string.
1692 * s390-opc.c: Add new instruction formats and instruction opcode
1694 * s390-opc.txt: Add new arch13 instructions.
1696 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1698 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1699 (aarch64_opcode): Change encoding for stg, stzg
1701 * aarch64-asm-2.c: Regenerated.
1702 * aarch64-dis-2.c: Regenerated.
1703 * aarch64-opc-2.c: Regenerated.
1705 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1707 * aarch64-asm-2.c: Regenerated.
1708 * aarch64-dis-2.c: Likewise.
1709 * aarch64-opc-2.c: Likewise.
1710 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1712 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1713 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1715 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1716 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1717 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1718 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1719 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1720 case for ldstgv_indexed.
1721 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1722 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1723 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1724 * aarch64-asm-2.c: Regenerated.
1725 * aarch64-dis-2.c: Regenerated.
1726 * aarch64-opc-2.c: Regenerated.
1728 2019-01-23 Nick Clifton <nickc@redhat.com>
1730 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1732 2019-01-21 Nick Clifton <nickc@redhat.com>
1734 * po/de.po: Updated German translation.
1735 * po/uk.po: Updated Ukranian translation.
1737 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1738 * mips-dis.c (mips_arch_choices): Fix typo in
1739 gs464, gs464e and gs264e descriptors.
1741 2019-01-19 Nick Clifton <nickc@redhat.com>
1743 * configure: Regenerate.
1744 * po/opcodes.pot: Regenerate.
1746 2018-06-24 Nick Clifton <nickc@redhat.com>
1748 2.32 branch created.
1750 2019-01-09 John Darrington <john@darrington.wattle.id.au>
1752 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1754 -dis.c (opr_emit_disassembly): Do not omit an index if it is
1757 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1759 * configure: Regenerate.
1761 2019-01-07 Alan Modra <amodra@gmail.com>
1763 * configure: Regenerate.
1764 * po/POTFILES.in: Regenerate.
1766 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1768 * s12z-opc.c: New file.
1769 * s12z-opc.h: New file.
1770 * s12z-dis.c: Removed all code not directly related to display
1771 of instructions. Used the interface provided by the new files
1773 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1774 * Makefile.in: Regenerate.
1775 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1776 * configure: Regenerate.
1778 2019-01-01 Alan Modra <amodra@gmail.com>
1780 Update year range in copyright notice of all files.
1782 For older changes see ChangeLog-2018
1784 Copyright (C) 2019 Free Software Foundation, Inc.
1786 Copying and distribution of this file, with or without modification,
1787 are permitted in any medium without royalty provided the copyright
1788 notice and this notice are preserved.
1794 version-control: never