opcodes/ChangeLog

   1 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
   4         * i386-opc.tbl: Likewise.
   5         * i386-tbl.h: Regenerated.
   6
   7 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
   8
   9         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
  10         and "jmp{&|}".
  11         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
  12         prefix.
  13
  14 2017-06-19  Nick Clifton  <nickc@redhat.com>
  15
  16         PR binutils/21614
  17         * score-dis.c (score_opcodes): Add sentinel.
  18
  19 2017-06-16  Alan Modra  <amodra@gmail.com>
  20
  21         * rx-decode.c: Regenerate.
  22
  23 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
  24
  25         PR binutils/21594
  26         * i386-dis.c (OP_E_register): Check valid bnd register.
  27         (OP_G): Likewise.
  28
  29 2017-06-15  Nick Clifton  <nickc@redhat.com>
  30
  31         PR binutils/21595
  32         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
  33         range value.
  34
  35 2017-06-15  Nick Clifton  <nickc@redhat.com>
  36
  37         PR binutils/21588
  38         * rl78-decode.opc (OP_BUF_LEN): Define.
  39         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
  40         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
  41         array.
  42         * rl78-decode.c: Regenerate.
  43
  44 2017-06-15  Nick Clifton  <nickc@redhat.com>
  45
  46         PR binutils/21586
  47         * bfin-dis.c (gregs): Clip index to prevent overflow.
  48         (regs): Likewise.
  49         (regs_lo): Likewise.
  50         (regs_hi): Likewise.
  51
  52 2017-06-14  Nick Clifton  <nickc@redhat.com>
  53
  54         PR binutils/21576
  55         * score7-dis.c (score_opcodes): Add sentinel.
  56
  57 2017-06-14  Yao Qi  <yao.qi@linaro.org>
  58
  59         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
  60         * arm-dis.c: Likewise.
  61         * ia64-dis.c: Likewise.
  62         * mips-dis.c: Likewise.
  63         * spu-dis.c: Likewise.
  64         * disassemble.h (print_insn_aarch64): New declaration, moved from
  65         include/dis-asm.h.
  66         (print_insn_big_arm, print_insn_big_mips): Likewise.
  67         (print_insn_i386, print_insn_ia64): Likewise.
  68         (print_insn_little_arm, print_insn_little_mips): Likewise.
  69
  70 2017-06-14  Nick Clifton  <nickc@redhat.com>
  71
  72         PR binutils/21587
  73         * rx-decode.opc: Include libiberty.h
  74         (GET_SCALE): New macro - validates access to SCALE array.
  75         (GET_PSCALE): New macro - validates access to PSCALE array.
  76         (DIs, SIs, S2Is, rx_disp): Use new macros.
  77         * rx-decode.c: Regenerate.
  78
  79 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  80
  81         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
  82
  83 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
  84
  85         * arc-dis.c (enforced_isa_mask): Declare.
  86         (cpu_types): Likewise.
  87         (parse_cpu_option): New function.
  88         (parse_disassembler_options): Use it.
  89         (print_insn_arc): Use enforced_isa_mask.
  90         (print_arc_disassembler_options): Document new options.
  91
  92 2017-05-24  Yao Qi  <yao.qi@linaro.org>
  93
  94         * alpha-dis.c: Include disassemble.h, don't include
  95         dis-asm.h.
  96         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
  97         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
  98         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
  99         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 100         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 101         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 102         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 103         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 104         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 105         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 106         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 107         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 108         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 109         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 110         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 111         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 112         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 113         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 114         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 115         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 116         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 117         * z80-dis.c, z8k-dis.c: Likewise.
 118         * disassemble.h: New file.
 119
 120 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 121
 122         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 123         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 124
 125 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 126
 127         * disassemble.c (disassembler): Add arguments a, big and mach.
 128         Use them.
 129
 130 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 131
 132         * i386-dis.c (NOTRACK_Fixup): New.
 133         (NOTRACK): Likewise.
 134         (NOTRACK_PREFIX): Likewise.
 135         (last_active_prefix): Likewise.
 136         (reg_table): Use NOTRACK on indirect call and jmp.
 137         (ckprefix): Set last_active_prefix.
 138         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 139         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 140         * i386-opc.h (NoTrackPrefixOk): New.
 141         (i386_opcode_modifier): Add notrackprefixok.
 142         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
 143         Add notrack.
 144         * i386-tbl.h: Regenerated.
 145
 146 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 147
 148         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
 149         (X_IMM2): Define.
 150         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
 151         bfd_mach_sparc_v9m8.
 152         (print_insn_sparc): Handle new operand types.
 153         * sparc-opc.c (MASK_M8): Define.
 154         (v6): Add MASK_M8.
 155         (v6notlet): Likewise.
 156         (v7): Likewise.
 157         (v8): Likewise.
 158         (v9): Likewise.
 159         (v9a): Likewise.
 160         (v9b): Likewise.
 161         (v9c): Likewise.
 162         (v9d): Likewise.
 163         (v9e): Likewise.
 164         (v9v): Likewise.
 165         (v9m): Likewise.
 166         (v9andleon): Likewise.
 167         (m8): Define.
 168         (HWS_VM8): Define.
 169         (HWS2_VM8): Likewise.
 170         (sparc_opcode_archs): Add entry for "m8".
 171         (sparc_opcodes): Add OSA2017 and M8 instructions
 172         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
 173         fpx{ll,ra,rl}64x,
 174         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
 175         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
 176         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
 177         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
 178         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
 179         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
 180         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
 181         ASI_CORE_SELECT_COMMIT_NHT.
 182
 183 2017-05-18  Alan Modra  <amodra@gmail.com>
 184
 185         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
 186         * aarch64-dis.c: Likewise.
 187         * aarch64-gen.c: Likewise.
 188         * aarch64-opc.c: Likewise.
 189
 190 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 191             Matthew Fortune  <matthew.fortune@imgtec.com>
 192
 193         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
 194         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
 195         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
 196         (print_insn_arg) <OP_REG28>: Add handler.
 197         (validate_insn_args) <OP_REG28>: Handle.
 198         (print_mips16_insn_arg): Handle MIPS16 instructions that require
 199         32-bit encoding and 9-bit immediates.
 200         (print_insn_mips16): Handle MIPS16 instructions that require
 201         32-bit encoding and MFC0/MTC0 operand decoding.
 202         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
 203         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
 204         (RD_C0, WR_C0, E2, E2MT): New macros.
 205         (mips16_opcodes): Add entries for MIPS16e2 instructions:
 206         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
 207         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
 208         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
 209         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
 210         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
 211         instructions, "swl", "swr", "sync" and its "sync_acquire",
 212         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
 213         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
 214         regular/extended entries for original MIPS16 ISA revision
 215         instructions whose extended forms are subdecoded in the MIPS16e2
 216         ISA revision: "li", "sll" and "srl".
 217
 218 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 219
 220         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
 221         reference in CP0 move operand decoding.
 222
 223 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
 224
 225         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
 226         type to hexadecimal.
 227         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
 228
 229 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
 230
 231         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
 232         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
 233         "sync_rmb" and "sync_wmb" as aliases.
 234         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
 235         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
 236
 237 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
 238
 239         * arc-dis.c (parse_option): Update quarkse_em option..
 240         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
 241         QUARKSE1.
 242         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
 243
 244 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
 245
 246         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
 247
 248 2017-05-01  Michael Clark  <michaeljclark@mac.com>
 249
 250         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
 251         register.
 252
 253 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
 254
 255         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
 256         and branches and not synthetic data instructions.
 257
 258 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
 259
 260         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
 261
 262 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 263
 264         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
 265         * arc-opc.c (insert_r13el): New function.
 266         (R13_EL): Define.
 267         * arc-tbl.h: Add new enter/leave variants.
 268
 269 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 270
 271         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
 272
 273 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 274
 275         * mips-dis.c (print_mips_disassembler_options): Add
 276         `no-aliases'.
 277
 278 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 279
 280         * mips16-opc.c (AL): New macro.
 281         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
 282         of "ld" and "lw" as aliases.
 283
 284 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
 285
 286         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
 287         arguments.
 288
 289 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
 290             Alan Modra  <amodra@gmail.com>
 291
 292         * ppc-opc.c (ELEV): Define.
 293         (vle_opcodes): Add se_rfgi and e_sc.
 294         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
 295         for E200Z4.
 296
 297 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
 298
 299         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
 300
 301 2017-04-21  Nick Clifton  <nickc@redhat.com>
 302
 303         PR binutils/21380
 304         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
 305         LD3R and LD4R.
 306
 307 2017-04-13  Alan Modra  <amodra@gmail.com>
 308
 309         * epiphany-desc.c: Regenerate.
 310         * fr30-desc.c: Regenerate.
 311         * frv-desc.c: Regenerate.
 312         * ip2k-desc.c: Regenerate.
 313         * iq2000-desc.c: Regenerate.
 314         * lm32-desc.c: Regenerate.
 315         * m32c-desc.c: Regenerate.
 316         * m32r-desc.c: Regenerate.
 317         * mep-desc.c: Regenerate.
 318         * mt-desc.c: Regenerate.
 319         * or1k-desc.c: Regenerate.
 320         * xc16x-desc.c: Regenerate.
 321         * xstormy16-desc.c: Regenerate.
 322
 323 2017-04-11  Alan Modra  <amodra@gmail.com>
 324
 325         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
 326         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
 327         PPC_OPCODE_TMR for e6500.
 328         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
 329         (PPCVEC3): Define as PPC_OPCODE_POWER9.
 330         (PPCVSX2): Define as PPC_OPCODE_POWER8.
 331         (PPCVSX3): Define as PPC_OPCODE_POWER9.
 332         (PPCHTM): Define as PPC_OPCODE_POWER8.
 333         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
 334
 335 2017-04-10  Alan Modra  <amodra@gmail.com>
 336
 337         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
 338         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
 339         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
 340         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
 341
 342 2017-04-09  Pip Cet  <pipcet@gmail.com>
 343
 344         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
 345         appropriate floating-point precision directly.
 346
 347 2017-04-07  Alan Modra  <amodra@gmail.com>
 348
 349         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
 350         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
 351         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
 352         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
 353         vector instructions with E6500 not PPCVEC2.
 354
 355 2017-04-06  Pip Cet  <pipcet@gmail.com>
 356
 357         * Makefile.am: Add wasm32-dis.c.
 358         * configure.ac: Add wasm32-dis.c to wasm32 target.
 359         * disassemble.c: Add wasm32 disassembler code.
 360         * wasm32-dis.c: New file.
 361         * Makefile.in: Regenerate.
 362         * configure: Regenerate.
 363         * po/POTFILES.in: Regenerate.
 364         * po/opcodes.pot: Regenerate.
 365
 366 2017-04-05  Pedro Alves  <palves@redhat.com>
 367
 368         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
 369         * arm-dis.c (parse_arm_disassembler_options): Constify.
 370         * ppc-dis.c (powerpc_init_dialect): Constify local.
 371         * vax-dis.c (parse_disassembler_options): Constify.
 372
 373 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
 374
 375         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
 376         RISCV_GP_SYMBOL.
 377
 378 2017-03-30  Pip Cet  <pipcet@gmail.com>
 379
 380         * configure.ac: Add (empty) bfd_wasm32_arch target.
 381         * configure: Regenerate
 382         * po/opcodes.pot: Regenerate.
 383
 384 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
 385
 386         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
 387         OSA2015.
 388         * opcodes/sparc-opc.c (asi_table): New ASIs.
 389
 390 2017-03-29  Alan Modra  <amodra@gmail.com>
 391
 392         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
 393         "raw" option.
 394         (lookup_powerpc): Don't special case -1 dialect.  Handle
 395         PPC_OPCODE_RAW.
 396         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
 397         lookup_powerpc call, pass it on second.
 398
 399 2017-03-27  Alan Modra  <amodra@gmail.com>
 400
 401         PR 21303
 402         * ppc-dis.c (struct ppc_mopt): Comment.
 403         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
 404
 405 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
 406
 407         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
 408         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
 409         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
 410         (insert_nps_misc_imm_offset): New function.
 411         (extract_nps_misc imm_offset): New function.
 412         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
 413         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
 414
 415 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 416
 417         * s390-mkopc.c (main): Remove vx2 check.
 418         * s390-opc.txt: Remove vx2 instruction flags.
 419
 420 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
 421
 422         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
 423         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
 424         (insert_nps_imm_offset): New function.
 425         (extract_nps_imm_offset): New function.
 426         (insert_nps_imm_entry): New function.
 427         (extract_nps_imm_entry): New function.
 428
 429 2017-03-17  Alan Modra  <amodra@gmail.com>
 430
 431         PR 21248
 432         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
 433         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
 434         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
 435
 436 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 437
 438         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
 439         <c.andi>: Likewise.
 440         <c.addiw> Likewise.
 441
 442 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 443
 444         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
 445
 446 2017-03-13  Andrew Waterman  <andrew@sifive.com>
 447
 448         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
 449         <srl> Likewise.
 450         <srai> Likewise.
 451         <sra> Likewise.
 452
 453 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 454
 455         * i386-gen.c (opcode_modifiers): Replace S with Load.
 456         * i386-opc.h (S): Removed.
 457         (Load): New.
 458         (i386_opcode_modifier): Replace s with load.
 459         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
 460         and {evex}.  Replace S with Load.
 461         * i386-tbl.h: Regenerated.
 462
 463 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 464
 465         * i386-opc.tbl: Use CpuCET on rdsspq.
 466         * i386-tbl.h: Regenerated.
 467
 468 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 469
 470         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
 471         <vsx>: Do not use PPC_OPCODE_VSX3;
 472
 473 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 474
 475         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
 476
 477 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
 478
 479         * i386-dis.c (REG_0F1E_MOD_3): New enum.
 480         (MOD_0F1E_PREFIX_1): Likewise.
 481         (MOD_0F38F5_PREFIX_2): Likewise.
 482         (MOD_0F38F6_PREFIX_0): Likewise.
 483         (RM_0F1E_MOD_3_REG_7): Likewise.
 484         (PREFIX_MOD_0_0F01_REG_5): Likewise.
 485         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 486         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
 487         (PREFIX_0F1E): Likewise.
 488         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
 489         (PREFIX_0F38F5): Likewise.
 490         (dis386_twobyte): Use PREFIX_0F1E.
 491         (reg_table): Add REG_0F1E_MOD_3.
 492         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
 493         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
 494         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
 495         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
 496         (three_byte_table): Use PREFIX_0F38F5.
 497         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
 498         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
 499         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
 500         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
 501         PREFIX_MOD_3_0F01_REG_5_RM_2.
 502         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
 503         (cpu_flags): Add CpuCET.
 504         * i386-opc.h (CpuCET): New enum.
 505         (CpuUnused): Commented out.
 506         (i386_cpu_flags): Add cpucet.
 507         * i386-opc.tbl: Add Intel CET instructions.
 508         * i386-init.h: Regenerated.
 509         * i386-tbl.h: Likewise.
 510
 511 2017-03-06  Alan Modra  <amodra@gmail.com>
 512
 513         PR 21124
 514         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
 515         (extract_raq, extract_ras, extract_rbx): New functions.
 516         (powerpc_operands): Use opposite corresponding insert function.
 517         (Q_MASK): Define.
 518         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
 519         register restriction.
 520
 521 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
 522
 523         * disassemble.c Include "safe-ctype.h".
 524         (disassemble_init_for_target): Handle s390 init.
 525         (remove_whitespace_and_extra_commas): New function.
 526         (disassembler_options_cmp): Likewise.
 527         * arm-dis.c: Include "libiberty.h".
 528         (NUM_ELEM): Delete.
 529         (regnames): Use long disassembler style names.
 530         Add force-thumb and no-force-thumb options.
 531         (NUM_ARM_REGNAMES): Rename from this...
 532         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
 533         (get_arm_regname_num_options): Delete.
 534         (set_arm_regname_option): Likewise.
 535         (get_arm_regnames): Likewise.
 536         (parse_disassembler_options): Likewise.
 537         (parse_arm_disassembler_option): Rename from this...
 538         (parse_arm_disassembler_options): ...to this.  Make static.
 539         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
 540         (print_insn): Use parse_arm_disassembler_options.
 541         (disassembler_options_arm): New function.
 542         (print_arm_disassembler_options): Handle updated regnames.
 543         * ppc-dis.c: Include "libiberty.h".
 544         (ppc_opts): Add "32" and "64" entries.
 545         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 546         (powerpc_init_dialect): Add break to switch statement.
 547         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 548         (disassembler_options_powerpc): New function.
 549         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 550         Remove printing of "32" and "64".
 551         * s390-dis.c: Include "libiberty.h".
 552         (init_flag): Remove unneeded variable.
 553         (struct s390_options_t): New structure type.
 554         (options): New structure.
 555         (init_disasm): Rename from this...
 556         (disassemble_init_s390): ...to this.  Add initializations for
 557         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 558         (print_insn_s390): Delete call to init_disasm.
 559         (disassembler_options_s390): New function.
 560         (print_s390_disassembler_options): Print using information from
 561         struct 'options'.
 562         * po/opcodes.pot: Regenerate.
 563
 564 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 565
 566         * i386-dis.c (PCMPESTR_Fixup): New.
 567         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 568         (prefix_table): Use PCMPESTR_Fixup.
 569         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 570         PCMPESTR_Fixup.
 571         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 572         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 573         Split 64-bit and non-64-bit variants.
 574         * opcodes/i386-tbl.h: Re-generate.
 575
 576 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 577
 578         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 579         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 580         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 581         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 582         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 583         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 584         (OP_SVE_V_HSD): New macros.
 585         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 586         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 587         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 588         (aarch64_opcode_table): Add new SVE instructions.
 589         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 590         for rotation operands.  Add new SVE operands.
 591         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 592         (ins_sve_quad_index): Likewise.
 593         (ins_imm_rotate): Split into...
 594         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 595         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 596         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 597         functions.
 598         (aarch64_ins_sve_addr_ri_s4): New function.
 599         (aarch64_ins_sve_quad_index): Likewise.
 600         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 601         * aarch64-asm-2.c: Regenerate.
 602         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 603         (ext_sve_quad_index): Likewise.
 604         (ext_imm_rotate): Split into...
 605         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 606         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 607         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 608         functions.
 609         (aarch64_ext_sve_addr_ri_s4): New function.
 610         (aarch64_ext_sve_quad_index): Likewise.
 611         (aarch64_ext_sve_index): Allow quad indices.
 612         (do_misc_decoding): Likewise.
 613         * aarch64-dis-2.c: Regenerate.
 614         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 615         aarch64_field_kinds.
 616         (OPD_F_OD_MASK): Widen by one bit.
 617         (OPD_F_NO_ZR): Bump accordingly.
 618         (get_operand_field_width): New function.
 619         * aarch64-opc.c (fields): Add new SVE fields.
 620         (operand_general_constraint_met_p): Handle new SVE operands.
 621         (aarch64_print_operand): Likewise.
 622         * aarch64-opc-2.c: Regenerate.
 623
 624 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 625
 626         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 627         (aarch64_feature_compnum): ...this.
 628         (SIMD_V8_3): Replace with...
 629         (COMPNUM): ...this.
 630         (CNUM_INSN): New macro.
 631         (aarch64_opcode_table): Use it for the complex number instructions.
 632
 633 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 634
 635         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 636
 637 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 638
 639         Add support for associating SPARC ASIs with an architecture level.
 640         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 641         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 642         decoding of SPARC ASIs.
 643
 644 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 645
 646         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 647         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 648
 649 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 650
 651         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 652         1 (instead of to itself). Correct typo.
 653
 654 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 655
 656         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 657         pseudoinstructions.
 658
 659 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 660
 661         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 662         (aarch64_sys_reg_supported_p): Handle them.
 663
 664 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 665
 666         * arc-opc.c (UIMM6_20R): Define.
 667         (SIMM12_20): Use above.
 668         (SIMM12_20R): Define.
 669         (SIMM3_5_S): Use above.
 670         (UIMM7_A32_11R_S): Define.
 671         (UIMM7_9_S): Use above.
 672         (UIMM3_13R_S): Define.
 673         (SIMM11_A32_7_S): Use above.
 674         (SIMM9_8R): Define.
 675         (UIMM10_A32_8_S): Use above.
 676         (UIMM8_8R_S): Define.
 677         (W6): Use above.
 678         (arc_relax_opcodes): Use all above defines.
 679
 680 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 681
 682         * arc-regs.h: Distinguish some of the registers different on
 683         ARC700 and HS38 cpus.
 684
 685 2017-02-14  Alan Modra  <amodra@gmail.com>
 686
 687         PR 21118
 688         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 689         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 690
 691 2017-02-11  Stafford Horne  <shorne@gmail.com>
 692             Alan Modra  <amodra@gmail.com>
 693
 694         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 695         Use insn_bytes_value and insn_int_value directly instead.  Don't
 696         free allocated memory until function exit.
 697
 698 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 699
 700         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 701
 702 2017-02-03  Nick Clifton  <nickc@redhat.com>
 703
 704         PR 21096
 705         * aarch64-opc.c (print_register_list): Ensure that the register
 706         list index will fir into the tb buffer.
 707         (print_register_offset_address): Likewise.
 708         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 709
 710 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 711
 712         PR 21056
 713         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 714         instructions when the previous fetch packet ends with a 32-bit
 715         instruction.
 716
 717 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 718
 719         * pru-opc.c: Remove vague reference to a future GDB port.
 720
 721 2017-01-20  Nick Clifton  <nickc@redhat.com>
 722
 723         * po/ga.po: Updated Irish translation.
 724
 725 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 726
 727         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 728
 729 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 730
 731         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 732         if FETCH_DATA returns 0.
 733         (m68k_scan_mask): Likewise.
 734         (print_insn_m68k): Update code to handle -1 return value.
 735
 736 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 737
 738         * m68k-dis.c (enum print_insn_arg_error): New.
 739         (NEXTBYTE): Replace -3 with
 740         PRINT_INSN_ARG_MEMORY_ERROR.
 741         (NEXTULONG): Likewise.
 742         (NEXTSINGLE): Likewise.
 743         (NEXTDOUBLE): Likewise.
 744         (NEXTDOUBLE): Likewise.
 745         (NEXTPACKED): Likewise.
 746         (FETCH_ARG): Likewise.
 747         (FETCH_DATA): Update comments.
 748         (print_insn_arg): Update comments. Replace magic numbers with
 749         enum.
 750         (match_insn_m68k): Likewise.
 751
 752 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 753
 754         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 755         * i386-dis-evex.h (evex_table): Updated.
 756         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 757         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 758         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 759         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 760         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 761         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 762         * i386-init.h: Regenerate.
 763         * i386-tbl.h: Ditto.
 764
 765 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 766
 767         * msp430-dis.c (msp430_singleoperand): Return -1 if
 768         msp430dis_opcode_signed returns false.
 769         (msp430_doubleoperand): Likewise.
 770         (msp430_branchinstr): Return -1 if
 771         msp430dis_opcode_unsigned returns false.
 772         (msp430x_calla_instr): Likewise.
 773         (print_insn_msp430): Likewise.
 774
 775 2017-01-05  Nick Clifton  <nickc@redhat.com>
 776
 777         PR 20946
 778         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 779         could not be matched.
 780         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 781         NULL.
 782
 783 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 784
 785         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 786         (aarch64_opcode_table): Use RCPC_INSN.
 787
 788 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 789
 790         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 791         extension.
 792         * riscv-opcodes/all-opcodes: Likewise.
 793
 794 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 795
 796         * riscv-dis.c (print_insn_args): Add fall through comment.
 797
 798 2017-01-03  Nick Clifton  <nickc@redhat.com>
 799
 800         * po/sr.po: New Serbian translation.
 801         * configure.ac (ALL_LINGUAS): Add sr.
 802         * configure: Regenerate.
 803
 804 2017-01-02  Alan Modra  <amodra@gmail.com>
 805
 806         * epiphany-desc.h: Regenerate.
 807         * epiphany-opc.h: Regenerate.
 808         * fr30-desc.h: Regenerate.
 809         * fr30-opc.h: Regenerate.
 810         * frv-desc.h: Regenerate.
 811         * frv-opc.h: Regenerate.
 812         * ip2k-desc.h: Regenerate.
 813         * ip2k-opc.h: Regenerate.
 814         * iq2000-desc.h: Regenerate.
 815         * iq2000-opc.h: Regenerate.
 816         * lm32-desc.h: Regenerate.
 817         * lm32-opc.h: Regenerate.
 818         * m32c-desc.h: Regenerate.
 819         * m32c-opc.h: Regenerate.
 820         * m32r-desc.h: Regenerate.
 821         * m32r-opc.h: Regenerate.
 822         * mep-desc.h: Regenerate.
 823         * mep-opc.h: Regenerate.
 824         * mt-desc.h: Regenerate.
 825         * mt-opc.h: Regenerate.
 826         * or1k-desc.h: Regenerate.
 827         * or1k-opc.h: Regenerate.
 828         * xc16x-desc.h: Regenerate.
 829         * xc16x-opc.h: Regenerate.
 830         * xstormy16-desc.h: Regenerate.
 831         * xstormy16-opc.h: Regenerate.
 832
 833 2017-01-02  Alan Modra  <amodra@gmail.com>
 834
 835         Update year range in copyright notice of all files.
 836
 837 For older changes see ChangeLog-2016
 838 \f
 839 Copyright (C) 2017 Free Software Foundation, Inc.
 840
 841 Copying and distribution of this file, with or without modification,
 842 are permitted in any medium without royalty provided the copyright
 843 notice and this notice are preserved.
 844
 845 Local Variables:
 846 mode: change-log
 847 left-margin: 8
 848 fill-column: 74
 849 version-control: never
 850 End: