1 2018-10-03 Tamar Christina <tamar.christina@arm.com>
3 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
4 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
5 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
6 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
9 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
11 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
13 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
14 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
15 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
16 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
17 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
18 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
19 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
21 2018-10-02 Palmer Dabbelt <palmer@sifive.com>
23 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
25 2018-09-23 Sandra Loosemore <sandra@codesourcery.com>
27 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
28 are used when extracting signed fields and converting them to
29 potentially 64-bit types.
31 2018-09-21 Simon Marchi <simon.marchi@ericsson.com>
33 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
34 * Makefile.in: Re-generate.
35 * aclocal.m4: Re-generate.
36 * configure: Re-generate.
37 * configure.ac: Remove check for -Wno-missing-field-initializers.
38 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
39 (csky_v2_opcodes): Likewise.
41 2018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
43 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
45 2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
47 * nds32-asm.c (operand_fields): Remove the unused fields.
48 (nds32_opcodes): Remove the unused instructions.
49 * nds32-dis.c (nds32_ex9_info): Removed.
50 (nds32_parse_opcode): Updated.
51 (print_insn_nds32): Likewise.
52 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
53 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
54 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
55 build_opcode_hash_table): New functions.
56 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
57 nds32_opcode_table): New.
58 (hw_ktabs): Declare it to a pointer rather than an array.
59 (build_hash_table): Removed.
60 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
61 SYN_ROPT and upadte HW_GPR and HW_INT.
62 * nds32-dis.c (keywords): Remove const.
63 (match_field): New function.
64 (nds32_parse_opcode): Updated.
65 * disassemble.c (disassemble_init_for_target):
66 Add disassemble_init_nds32.
67 * nds32-dis.c (eum map_type): New.
68 (nds32_private_data): Likewise.
69 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
70 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
71 (print_insn_nds32): Updated.
72 * nds32-asm.c (parse_aext_reg): Add new parameter.
73 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
76 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
77 (operand_fields): Add new fields.
78 (nds32_opcodes): Add new instructions.
79 (keyword_aridxi_mx): New keyword.
80 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
82 (ALU2_1, ALU2_2, ALU2_3): New macros.
83 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
85 2018-09-17 Kito Cheng <kito@andestech.com>
87 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
89 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
92 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
93 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
94 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
95 (EVEX_LEN_0F7E_P_1): Likewise.
96 (EVEX_LEN_0F7E_P_2): Likewise.
97 (EVEX_LEN_0FD6_P_2): Likewise.
98 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
99 (EVEX_LEN_TABLE): Likewise.
100 (EVEX_LEN_0F6E_P_2): New enum.
101 (EVEX_LEN_0F7E_P_1): Likewise.
102 (EVEX_LEN_0F7E_P_2): Likewise.
103 (EVEX_LEN_0FD6_P_2): Likewise.
104 (evex_len_table): New.
105 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
106 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
107 * i386-tbl.h: Regenerated.
109 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
112 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
113 VEX_LEN_0F7E_P_2 entries.
114 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
115 * i386-tbl.h: Regenerated.
117 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
119 * i386-dis.c (VZERO_Fixup): Removed.
121 (VEX_LEN_0F10_P_1): Likewise.
122 (VEX_LEN_0F10_P_3): Likewise.
123 (VEX_LEN_0F11_P_1): Likewise.
124 (VEX_LEN_0F11_P_3): Likewise.
125 (VEX_LEN_0F2E_P_0): Likewise.
126 (VEX_LEN_0F2E_P_2): Likewise.
127 (VEX_LEN_0F2F_P_0): Likewise.
128 (VEX_LEN_0F2F_P_2): Likewise.
129 (VEX_LEN_0F51_P_1): Likewise.
130 (VEX_LEN_0F51_P_3): Likewise.
131 (VEX_LEN_0F52_P_1): Likewise.
132 (VEX_LEN_0F53_P_1): Likewise.
133 (VEX_LEN_0F58_P_1): Likewise.
134 (VEX_LEN_0F58_P_3): Likewise.
135 (VEX_LEN_0F59_P_1): Likewise.
136 (VEX_LEN_0F59_P_3): Likewise.
137 (VEX_LEN_0F5A_P_1): Likewise.
138 (VEX_LEN_0F5A_P_3): Likewise.
139 (VEX_LEN_0F5C_P_1): Likewise.
140 (VEX_LEN_0F5C_P_3): Likewise.
141 (VEX_LEN_0F5D_P_1): Likewise.
142 (VEX_LEN_0F5D_P_3): Likewise.
143 (VEX_LEN_0F5E_P_1): Likewise.
144 (VEX_LEN_0F5E_P_3): Likewise.
145 (VEX_LEN_0F5F_P_1): Likewise.
146 (VEX_LEN_0F5F_P_3): Likewise.
147 (VEX_LEN_0FC2_P_1): Likewise.
148 (VEX_LEN_0FC2_P_3): Likewise.
149 (VEX_LEN_0F3A0A_P_2): Likewise.
150 (VEX_LEN_0F3A0B_P_2): Likewise.
151 (VEX_W_0F10_P_0): Likewise.
152 (VEX_W_0F10_P_1): Likewise.
153 (VEX_W_0F10_P_2): Likewise.
154 (VEX_W_0F10_P_3): Likewise.
155 (VEX_W_0F11_P_0): Likewise.
156 (VEX_W_0F11_P_1): Likewise.
157 (VEX_W_0F11_P_2): Likewise.
158 (VEX_W_0F11_P_3): Likewise.
159 (VEX_W_0F12_P_0_M_0): Likewise.
160 (VEX_W_0F12_P_0_M_1): Likewise.
161 (VEX_W_0F12_P_1): Likewise.
162 (VEX_W_0F12_P_2): Likewise.
163 (VEX_W_0F12_P_3): Likewise.
164 (VEX_W_0F13_M_0): Likewise.
165 (VEX_W_0F14): Likewise.
166 (VEX_W_0F15): Likewise.
167 (VEX_W_0F16_P_0_M_0): Likewise.
168 (VEX_W_0F16_P_0_M_1): Likewise.
169 (VEX_W_0F16_P_1): Likewise.
170 (VEX_W_0F16_P_2): Likewise.
171 (VEX_W_0F17_M_0): Likewise.
172 (VEX_W_0F28): Likewise.
173 (VEX_W_0F29): Likewise.
174 (VEX_W_0F2B_M_0): Likewise.
175 (VEX_W_0F2E_P_0): Likewise.
176 (VEX_W_0F2E_P_2): Likewise.
177 (VEX_W_0F2F_P_0): Likewise.
178 (VEX_W_0F2F_P_2): Likewise.
179 (VEX_W_0F50_M_0): Likewise.
180 (VEX_W_0F51_P_0): Likewise.
181 (VEX_W_0F51_P_1): Likewise.
182 (VEX_W_0F51_P_2): Likewise.
183 (VEX_W_0F51_P_3): Likewise.
184 (VEX_W_0F52_P_0): Likewise.
185 (VEX_W_0F52_P_1): Likewise.
186 (VEX_W_0F53_P_0): Likewise.
187 (VEX_W_0F53_P_1): Likewise.
188 (VEX_W_0F58_P_0): Likewise.
189 (VEX_W_0F58_P_1): Likewise.
190 (VEX_W_0F58_P_2): Likewise.
191 (VEX_W_0F58_P_3): Likewise.
192 (VEX_W_0F59_P_0): Likewise.
193 (VEX_W_0F59_P_1): Likewise.
194 (VEX_W_0F59_P_2): Likewise.
195 (VEX_W_0F59_P_3): Likewise.
196 (VEX_W_0F5A_P_0): Likewise.
197 (VEX_W_0F5A_P_1): Likewise.
198 (VEX_W_0F5A_P_3): Likewise.
199 (VEX_W_0F5B_P_0): Likewise.
200 (VEX_W_0F5B_P_1): Likewise.
201 (VEX_W_0F5B_P_2): Likewise.
202 (VEX_W_0F5C_P_0): Likewise.
203 (VEX_W_0F5C_P_1): Likewise.
204 (VEX_W_0F5C_P_2): Likewise.
205 (VEX_W_0F5C_P_3): Likewise.
206 (VEX_W_0F5D_P_0): Likewise.
207 (VEX_W_0F5D_P_1): Likewise.
208 (VEX_W_0F5D_P_2): Likewise.
209 (VEX_W_0F5D_P_3): Likewise.
210 (VEX_W_0F5E_P_0): Likewise.
211 (VEX_W_0F5E_P_1): Likewise.
212 (VEX_W_0F5E_P_2): Likewise.
213 (VEX_W_0F5E_P_3): Likewise.
214 (VEX_W_0F5F_P_0): Likewise.
215 (VEX_W_0F5F_P_1): Likewise.
216 (VEX_W_0F5F_P_2): Likewise.
217 (VEX_W_0F5F_P_3): Likewise.
218 (VEX_W_0F60_P_2): Likewise.
219 (VEX_W_0F61_P_2): Likewise.
220 (VEX_W_0F62_P_2): Likewise.
221 (VEX_W_0F63_P_2): Likewise.
222 (VEX_W_0F64_P_2): Likewise.
223 (VEX_W_0F65_P_2): Likewise.
224 (VEX_W_0F66_P_2): Likewise.
225 (VEX_W_0F67_P_2): Likewise.
226 (VEX_W_0F68_P_2): Likewise.
227 (VEX_W_0F69_P_2): Likewise.
228 (VEX_W_0F6A_P_2): Likewise.
229 (VEX_W_0F6B_P_2): Likewise.
230 (VEX_W_0F6C_P_2): Likewise.
231 (VEX_W_0F6D_P_2): Likewise.
232 (VEX_W_0F6F_P_1): Likewise.
233 (VEX_W_0F6F_P_2): Likewise.
234 (VEX_W_0F70_P_1): Likewise.
235 (VEX_W_0F70_P_2): Likewise.
236 (VEX_W_0F70_P_3): Likewise.
237 (VEX_W_0F71_R_2_P_2): Likewise.
238 (VEX_W_0F71_R_4_P_2): Likewise.
239 (VEX_W_0F71_R_6_P_2): Likewise.
240 (VEX_W_0F72_R_2_P_2): Likewise.
241 (VEX_W_0F72_R_4_P_2): Likewise.
242 (VEX_W_0F72_R_6_P_2): Likewise.
243 (VEX_W_0F73_R_2_P_2): Likewise.
244 (VEX_W_0F73_R_3_P_2): Likewise.
245 (VEX_W_0F73_R_6_P_2): Likewise.
246 (VEX_W_0F73_R_7_P_2): Likewise.
247 (VEX_W_0F74_P_2): Likewise.
248 (VEX_W_0F75_P_2): Likewise.
249 (VEX_W_0F76_P_2): Likewise.
250 (VEX_W_0F77_P_0): Likewise.
251 (VEX_W_0F7C_P_2): Likewise.
252 (VEX_W_0F7C_P_3): Likewise.
253 (VEX_W_0F7D_P_2): Likewise.
254 (VEX_W_0F7D_P_3): Likewise.
255 (VEX_W_0F7E_P_1): Likewise.
256 (VEX_W_0F7F_P_1): Likewise.
257 (VEX_W_0F7F_P_2): Likewise.
258 (VEX_W_0FAE_R_2_M_0): Likewise.
259 (VEX_W_0FAE_R_3_M_0): Likewise.
260 (VEX_W_0FC2_P_0): Likewise.
261 (VEX_W_0FC2_P_1): Likewise.
262 (VEX_W_0FC2_P_2): Likewise.
263 (VEX_W_0FC2_P_3): Likewise.
264 (VEX_W_0FD0_P_2): Likewise.
265 (VEX_W_0FD0_P_3): Likewise.
266 (VEX_W_0FD1_P_2): Likewise.
267 (VEX_W_0FD2_P_2): Likewise.
268 (VEX_W_0FD3_P_2): Likewise.
269 (VEX_W_0FD4_P_2): Likewise.
270 (VEX_W_0FD5_P_2): Likewise.
271 (VEX_W_0FD6_P_2): Likewise.
272 (VEX_W_0FD7_P_2_M_1): Likewise.
273 (VEX_W_0FD8_P_2): Likewise.
274 (VEX_W_0FD9_P_2): Likewise.
275 (VEX_W_0FDA_P_2): Likewise.
276 (VEX_W_0FDB_P_2): Likewise.
277 (VEX_W_0FDC_P_2): Likewise.
278 (VEX_W_0FDD_P_2): Likewise.
279 (VEX_W_0FDE_P_2): Likewise.
280 (VEX_W_0FDF_P_2): Likewise.
281 (VEX_W_0FE0_P_2): Likewise.
282 (VEX_W_0FE1_P_2): Likewise.
283 (VEX_W_0FE2_P_2): Likewise.
284 (VEX_W_0FE3_P_2): Likewise.
285 (VEX_W_0FE4_P_2): Likewise.
286 (VEX_W_0FE5_P_2): Likewise.
287 (VEX_W_0FE6_P_1): Likewise.
288 (VEX_W_0FE6_P_2): Likewise.
289 (VEX_W_0FE6_P_3): Likewise.
290 (VEX_W_0FE7_P_2_M_0): Likewise.
291 (VEX_W_0FE8_P_2): Likewise.
292 (VEX_W_0FE9_P_2): Likewise.
293 (VEX_W_0FEA_P_2): Likewise.
294 (VEX_W_0FEB_P_2): Likewise.
295 (VEX_W_0FEC_P_2): Likewise.
296 (VEX_W_0FED_P_2): Likewise.
297 (VEX_W_0FEE_P_2): Likewise.
298 (VEX_W_0FEF_P_2): Likewise.
299 (VEX_W_0FF0_P_3_M_0): Likewise.
300 (VEX_W_0FF1_P_2): Likewise.
301 (VEX_W_0FF2_P_2): Likewise.
302 (VEX_W_0FF3_P_2): Likewise.
303 (VEX_W_0FF4_P_2): Likewise.
304 (VEX_W_0FF5_P_2): Likewise.
305 (VEX_W_0FF6_P_2): Likewise.
306 (VEX_W_0FF7_P_2): Likewise.
307 (VEX_W_0FF8_P_2): Likewise.
308 (VEX_W_0FF9_P_2): Likewise.
309 (VEX_W_0FFA_P_2): Likewise.
310 (VEX_W_0FFB_P_2): Likewise.
311 (VEX_W_0FFC_P_2): Likewise.
312 (VEX_W_0FFD_P_2): Likewise.
313 (VEX_W_0FFE_P_2): Likewise.
314 (VEX_W_0F3800_P_2): Likewise.
315 (VEX_W_0F3801_P_2): Likewise.
316 (VEX_W_0F3802_P_2): Likewise.
317 (VEX_W_0F3803_P_2): Likewise.
318 (VEX_W_0F3804_P_2): Likewise.
319 (VEX_W_0F3805_P_2): Likewise.
320 (VEX_W_0F3806_P_2): Likewise.
321 (VEX_W_0F3807_P_2): Likewise.
322 (VEX_W_0F3808_P_2): Likewise.
323 (VEX_W_0F3809_P_2): Likewise.
324 (VEX_W_0F380A_P_2): Likewise.
325 (VEX_W_0F380B_P_2): Likewise.
326 (VEX_W_0F3817_P_2): Likewise.
327 (VEX_W_0F381C_P_2): Likewise.
328 (VEX_W_0F381D_P_2): Likewise.
329 (VEX_W_0F381E_P_2): Likewise.
330 (VEX_W_0F3820_P_2): Likewise.
331 (VEX_W_0F3821_P_2): Likewise.
332 (VEX_W_0F3822_P_2): Likewise.
333 (VEX_W_0F3823_P_2): Likewise.
334 (VEX_W_0F3824_P_2): Likewise.
335 (VEX_W_0F3825_P_2): Likewise.
336 (VEX_W_0F3828_P_2): Likewise.
337 (VEX_W_0F3829_P_2): Likewise.
338 (VEX_W_0F382A_P_2_M_0): Likewise.
339 (VEX_W_0F382B_P_2): Likewise.
340 (VEX_W_0F3830_P_2): Likewise.
341 (VEX_W_0F3831_P_2): Likewise.
342 (VEX_W_0F3832_P_2): Likewise.
343 (VEX_W_0F3833_P_2): Likewise.
344 (VEX_W_0F3834_P_2): Likewise.
345 (VEX_W_0F3835_P_2): Likewise.
346 (VEX_W_0F3837_P_2): Likewise.
347 (VEX_W_0F3838_P_2): Likewise.
348 (VEX_W_0F3839_P_2): Likewise.
349 (VEX_W_0F383A_P_2): Likewise.
350 (VEX_W_0F383B_P_2): Likewise.
351 (VEX_W_0F383C_P_2): Likewise.
352 (VEX_W_0F383D_P_2): Likewise.
353 (VEX_W_0F383E_P_2): Likewise.
354 (VEX_W_0F383F_P_2): Likewise.
355 (VEX_W_0F3840_P_2): Likewise.
356 (VEX_W_0F3841_P_2): Likewise.
357 (VEX_W_0F38DB_P_2): Likewise.
358 (VEX_W_0F3A08_P_2): Likewise.
359 (VEX_W_0F3A09_P_2): Likewise.
360 (VEX_W_0F3A0A_P_2): Likewise.
361 (VEX_W_0F3A0B_P_2): Likewise.
362 (VEX_W_0F3A0C_P_2): Likewise.
363 (VEX_W_0F3A0D_P_2): Likewise.
364 (VEX_W_0F3A0E_P_2): Likewise.
365 (VEX_W_0F3A0F_P_2): Likewise.
366 (VEX_W_0F3A21_P_2): Likewise.
367 (VEX_W_0F3A40_P_2): Likewise.
368 (VEX_W_0F3A41_P_2): Likewise.
369 (VEX_W_0F3A42_P_2): Likewise.
370 (VEX_W_0F3A62_P_2): Likewise.
371 (VEX_W_0F3A63_P_2): Likewise.
372 (VEX_W_0F3ADF_P_2): Likewise.
373 (VEX_LEN_0F77_P_0): New.
374 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
375 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
376 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
377 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
378 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
379 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
380 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
381 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
382 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
383 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
384 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
385 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
386 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
387 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
388 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
389 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
390 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
391 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
392 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
393 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
394 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
395 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
396 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
397 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
398 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
399 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
400 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
401 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
402 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
403 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
404 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
405 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
406 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
407 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
408 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
409 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
410 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
411 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
412 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
413 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
414 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
415 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
416 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
417 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
418 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
419 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
420 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
421 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
422 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
423 (vex_table): Update VEX 0F28 and 0F29 entries.
424 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
425 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
426 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
427 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
428 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
429 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
430 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
431 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
432 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
433 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
434 VEX_LEN_0F3A0B_P_2 entries.
435 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
436 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
437 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
438 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
439 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
440 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
441 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
442 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
443 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
444 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
445 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
446 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
447 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
448 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
449 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
450 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
451 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
452 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
453 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
454 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
455 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
456 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
457 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
458 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
459 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
460 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
461 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
462 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
463 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
464 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
465 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
466 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
467 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
468 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
469 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
470 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
471 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
472 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
473 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
474 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
475 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
476 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
477 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
478 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
479 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
480 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
481 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
482 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
483 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
484 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
485 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
486 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
487 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
488 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
489 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
490 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
491 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
492 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
493 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
494 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
495 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
496 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
497 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
498 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
499 VEX_W_0F3ADF_P_2 entries.
500 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
501 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
502 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
504 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
506 * i386-opc.tbl (VexWIG): New.
507 Replace VexW=3 with VexWIG.
509 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
511 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
512 * i386-tbl.h: Regenerated.
514 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
517 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
518 VEX_LEN_0FD6_P_2 entries.
519 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
520 * i386-tbl.h: Regenerated.
522 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
525 * i386-opc.h (VEXWIG): New.
526 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
527 * i386-tbl.h: Regenerated.
529 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
532 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
533 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
534 * i386-dis.c (EXxEVexR64): New.
535 (evex_rounding_64_mode): Likewise.
536 (OP_Rounding): Handle evex_rounding_64_mode.
538 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
541 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
542 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
543 * i386-dis.c (Edqa): New.
544 (dqa_mode): Likewise.
545 (intel_operand_size): Handle dqa_mode as m_mode.
546 (OP_E_register): Handle dqa_mode as dq_mode.
547 (OP_E_memory): Set shift for dqa_mode based on address_mode.
549 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
551 * i386-dis.c (OP_E_memory): Reformat.
553 2018-09-14 Jan Beulich <jbeulich@suse.com>
555 * i386-opc.tbl (crc32): Fold byte and word forms.
556 * i386-tbl.h: Re-generate.
558 2018-09-13 H.J. Lu <hongjiu.lu@intel.com>
560 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
561 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
562 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
563 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
564 * i386-tbl.h: Regenerated.
566 2018-09-13 Jan Beulich <jbeulich@suse.com>
568 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
570 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
571 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
572 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
573 * i386-tbl.h: Re-generate.
575 2018-09-13 Jan Beulich <jbeulich@suse.com>
577 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
579 * i386-tbl.h: Re-generate.
581 2018-09-13 Jan Beulich <jbeulich@suse.com>
583 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
585 * i386-tbl.h: Re-generate.
587 2018-09-13 Jan Beulich <jbeulich@suse.com>
589 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
591 * i386-tbl.h: Re-generate.
593 2018-09-13 Jan Beulich <jbeulich@suse.com>
595 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
597 * i386-tbl.h: Re-generate.
599 2018-09-13 Jan Beulich <jbeulich@suse.com>
601 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
603 * i386-tbl.h: Re-generate.
605 2018-09-13 Jan Beulich <jbeulich@suse.com>
607 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
609 * i386-tbl.h: Re-generate.
611 2018-09-13 Jan Beulich <jbeulich@suse.com>
613 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
614 * i386-tbl.h: Re-generate.
616 2018-09-13 Jan Beulich <jbeulich@suse.com>
618 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
619 * i386-tbl.h: Re-generate.
621 2018-09-13 Jan Beulich <jbeulich@suse.com>
623 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
625 * i386-tbl.h: Re-generate.
627 2018-09-13 Jan Beulich <jbeulich@suse.com>
629 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
631 * i386-tbl.h: Re-generate.
633 2018-09-13 Jan Beulich <jbeulich@suse.com>
635 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
636 * i386-tbl.h: Re-generate.
638 2018-09-13 Jan Beulich <jbeulich@suse.com>
640 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
641 * i386-tbl.h: Re-generate.
643 2018-09-13 Jan Beulich <jbeulich@suse.com>
645 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
646 * i386-tbl.h: Re-generate.
648 2018-09-13 Jan Beulich <jbeulich@suse.com>
650 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
652 * i386-tbl.h: Re-generate.
654 2018-09-13 Jan Beulich <jbeulich@suse.com>
656 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
658 * i386-tbl.h: Re-generate.
660 2018-09-13 Jan Beulich <jbeulich@suse.com>
662 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
664 * i386-tbl.h: Re-generate.
666 2018-09-13 Jan Beulich <jbeulich@suse.com>
668 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
669 * i386-tbl.h: Re-generate.
671 2018-09-13 Jan Beulich <jbeulich@suse.com>
673 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
674 * i386-tbl.h: Re-generate.
676 2018-09-13 Jan Beulich <jbeulich@suse.com>
678 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
679 * i386-tbl.h: Re-generate.
681 2018-09-13 Jan Beulich <jbeulich@suse.com>
683 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
684 (vpbroadcastw, rdpid): Drop NoRex64.
685 * i386-tbl.h: Re-generate.
687 2018-09-13 Jan Beulich <jbeulich@suse.com>
689 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
690 store templates, adding D.
691 * i386-tbl.h: Re-generate.
693 2018-09-13 Jan Beulich <jbeulich@suse.com>
695 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
696 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
697 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
698 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
699 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
700 Fold load and store templates where possible, adding D. Drop
701 IgnoreSize where it was pointlessly present. Drop redundant
703 * i386-tbl.h: Re-generate.
705 2018-09-13 Jan Beulich <jbeulich@suse.com>
707 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
708 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
709 (intel_operand_size): Handle v_bndmk_mode.
710 (OP_E_memory): Likewise. Produce (bad) when also riprel.
712 2018-09-08 John Darrington <john@darrington.wattle.id.au>
714 * disassemble.c (ARCH_s12z): Define if ARCH_all.
716 2018-08-31 Kito Cheng <kito@andestech.com>
718 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
719 compressed floating point instructions.
721 2018-08-30 Kito Cheng <kito@andestech.com>
723 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
724 riscv_opcode.xlen_requirement.
725 * riscv-opc.c (riscv_opcodes): Update for struct change.
727 2018-08-29 Martin Aberg <maberg@gaisler.com>
729 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
730 psr (PWRPSR) instruction.
732 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
734 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
736 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
738 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
740 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
742 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
743 loongson3a as an alias of gs464 for compatibility.
744 * mips-opc.c (mips_opcodes): Change Comments.
746 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
748 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
750 (print_mips_disassembler_options): Document -M loongson-ext.
751 * mips-opc.c (LEXT2): New macro.
752 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
754 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
756 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
758 (parse_mips_ase_option): Handle -M loongson-ext option.
759 (print_mips_disassembler_options): Document -M loongson-ext.
760 * mips-opc.c (IL3A): Delete.
761 * mips-opc.c (LEXT): New macro.
762 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
765 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
767 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
769 (parse_mips_ase_option): Handle -M loongson-cam option.
770 (print_mips_disassembler_options): Document -M loongson-cam.
771 * mips-opc.c (LCAM): New macro.
772 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
775 2018-08-21 Alan Modra <amodra@gmail.com>
777 * ppc-dis.c (operand_value_powerpc): Init "invalid".
778 (skip_optional_operands): Count optional operands, and update
779 ppc_optional_operand_value call.
780 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
781 (extract_vlensi): Likewise.
782 (extract_fxm): Return default value for missing optional operand.
783 (extract_ls, extract_raq, extract_tbr): Likewise.
784 (insert_sxl, extract_sxl): New functions.
785 (insert_esync, extract_esync): Remove Power9 handling and simplify.
786 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
787 flag and extra entry.
788 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
791 2018-08-20 Alan Modra <amodra@gmail.com>
793 * sh-opc.h (MASK): Simplify.
795 2018-08-18 John Darrington <john@darrington.wattle.id.au>
797 * s12z-dis.c (bm_decode): Deal with cases where the mode is
798 BM_RESERVED0 or BM_RESERVED1
799 (bm_rel_decode, bm_n_bytes): Ditto.
801 2018-08-18 John Darrington <john@darrington.wattle.id.au>
805 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
807 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
808 address with the addr32 prefix and without base nor index
811 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
813 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
814 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
815 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
816 (cpu_flags): Add CpuCMOV and CpuFXSR.
817 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
818 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
819 * i386-init.h: Regenerated.
820 * i386-tbl.h: Likewise.
822 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
824 * arc-regs.h: Update auxiliary registers.
826 2018-08-06 Jan Beulich <jbeulich@suse.com>
828 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
829 (RegIP, RegIZ): Define.
830 * i386-reg.tbl: Adjust comments.
831 (rip): Use Qword instead of BaseIndex. Use RegIP.
832 (eip): Use Dword instead of BaseIndex. Use RegIP.
833 (riz): Add Qword. Use RegIZ.
834 (eiz): Add Dword. Use RegIZ.
835 * i386-tbl.h: Re-generate.
837 2018-08-03 Jan Beulich <jbeulich@suse.com>
839 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
840 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
841 vpmovzxdq, vpmovzxwd): Remove NoRex64.
842 * i386-tbl.h: Re-generate.
844 2018-08-03 Jan Beulich <jbeulich@suse.com>
846 * i386-gen.c (operand_types): Remove Mem field.
847 * i386-opc.h (union i386_operand_type): Remove mem field.
848 * i386-init.h, i386-tbl.h: Re-generate.
850 2018-08-01 Alan Modra <amodra@gmail.com>
852 * po/POTFILES.in: Regenerate.
854 2018-07-31 Nick Clifton <nickc@redhat.com>
856 * po/sv.po: Updated Swedish translation.
858 2018-07-31 Jan Beulich <jbeulich@suse.com>
860 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
861 * i386-init.h, i386-tbl.h: Re-generate.
863 2018-07-31 Jan Beulich <jbeulich@suse.com>
865 * i386-opc.h (ZEROING_MASKING) Rename to ...
866 (DYNAMIC_MASKING): ... this. Adjust comment.
867 * i386-opc.tbl (MaskingMorZ): Define.
868 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
869 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
870 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
871 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
872 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
873 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
874 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
875 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
876 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
878 2018-07-31 Jan Beulich <jbeulich@suse.com>
880 * i386-opc.tbl: Use element rather than vector size for AVX512*
881 scatter/gather insns.
882 * i386-tbl.h: Re-generate.
884 2018-07-31 Jan Beulich <jbeulich@suse.com>
886 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
887 (cpu_flags): Drop CpuVREX.
888 * i386-opc.h (CpuVREX): Delete.
889 (union i386_cpu_flags): Remove cpuvrex.
890 * i386-init.h, i386-tbl.h: Re-generate.
892 2018-07-30 Jim Wilson <jimw@sifive.com>
894 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
896 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
898 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
900 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
901 * Makefile.in: Regenerated.
902 * configure.ac: Add C-SKY.
903 * configure: Regenerated.
904 * csky-dis.c: New file.
905 * csky-opc.h: New file.
906 * disassemble.c (ARCH_csky): Define.
907 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
908 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
910 2018-07-27 Alan Modra <amodra@gmail.com>
912 * ppc-opc.c (insert_sprbat): Correct function parameter and
914 (extract_sprbat): Likewise, variable too.
916 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
917 Alan Modra <amodra@gmail.com>
919 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
920 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
921 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
922 support disjointed BAT.
923 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
924 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
925 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
927 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
928 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
930 * i386-gen.c (adjust_broadcast_modifier): New function.
931 (process_i386_opcode_modifier): Add an argument for operands.
932 Adjust the Broadcast value based on operands.
933 (output_i386_opcode): Pass operand_types to
934 process_i386_opcode_modifier.
935 (process_i386_opcodes): Pass NULL as operands to
936 process_i386_opcode_modifier.
937 * i386-opc.h (BYTE_BROADCAST): New.
938 (WORD_BROADCAST): Likewise.
939 (DWORD_BROADCAST): Likewise.
940 (QWORD_BROADCAST): Likewise.
941 (i386_opcode_modifier): Expand broadcast to 3 bits.
942 * i386-tbl.h: Regenerated.
944 2018-07-24 Alan Modra <amodra@gmail.com>
947 * or1k-desc.h: Regenerate.
949 2018-07-24 Jan Beulich <jbeulich@suse.com>
951 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
952 vcvtusi2ss, and vcvtusi2sd.
953 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
954 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
955 * i386-tbl.h: Re-generate.
957 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
959 * arc-opc.c (extract_w6): Fix extending the sign.
961 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
963 * arc-tbl.h (vewt): Allow it for ARC EM family.
965 2018-07-23 Alan Modra <amodra@gmail.com>
968 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
969 opcode variants for mtspr/mfspr encodings.
971 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
972 Maciej W. Rozycki <macro@mips.com>
974 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
975 loongson3a descriptors.
976 (parse_mips_ase_option): Handle -M loongson-mmi option.
977 (print_mips_disassembler_options): Document -M loongson-mmi.
978 * mips-opc.c (LMMI): New macro.
979 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
982 2018-07-19 Jan Beulich <jbeulich@suse.com>
984 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
985 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
986 IgnoreSize and [XYZ]MMword where applicable.
987 * i386-tbl.h: Re-generate.
989 2018-07-19 Jan Beulich <jbeulich@suse.com>
991 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
992 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
993 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
994 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
995 * i386-tbl.h: Re-generate.
997 2018-07-19 Jan Beulich <jbeulich@suse.com>
999 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1000 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1001 VPCLMULQDQ templates into their respective AVX512VL counterparts
1002 where possible, using Disp8ShiftVL and CheckRegSize instead of
1003 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1004 * i386-tbl.h: Re-generate.
1006 2018-07-19 Jan Beulich <jbeulich@suse.com>
1008 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1009 AVX512VL counterparts where possible, using Disp8ShiftVL and
1010 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1011 IgnoreSize) as appropriate.
1012 * i386-tbl.h: Re-generate.
1014 2018-07-19 Jan Beulich <jbeulich@suse.com>
1016 * i386-opc.tbl: Fold AVX512BW templates into their respective
1017 AVX512VL counterparts where possible, using Disp8ShiftVL and
1018 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1019 IgnoreSize) as appropriate.
1020 * i386-tbl.h: Re-generate.
1022 2018-07-19 Jan Beulich <jbeulich@suse.com>
1024 * i386-opc.tbl: Fold AVX512CD templates into their respective
1025 AVX512VL counterparts where possible, using Disp8ShiftVL and
1026 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1027 IgnoreSize) as appropriate.
1028 * i386-tbl.h: Re-generate.
1030 2018-07-19 Jan Beulich <jbeulich@suse.com>
1032 * i386-opc.h (DISP8_SHIFT_VL): New.
1033 * i386-opc.tbl (Disp8ShiftVL): Define.
1034 (various): Fold AVX512VL templates into their respective
1035 AVX512F counterparts where possible, using Disp8ShiftVL and
1036 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1037 IgnoreSize) as appropriate.
1038 * i386-tbl.h: Re-generate.
1040 2018-07-19 Jan Beulich <jbeulich@suse.com>
1042 * Makefile.am: Change dependencies and rule for
1043 $(srcdir)/i386-init.h.
1044 * Makefile.in: Re-generate.
1045 * i386-gen.c (process_i386_opcodes): New local variable
1046 "marker". Drop opening of input file. Recognize marker and line
1048 * i386-opc.tbl (OPCODE_I386_H): Define.
1049 (i386-opc.h): Include it.
1052 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1055 * i386-opc.h (Byte): Update comments.
1061 (Xmmword): Likewise.
1062 (Ymmword): Likewise.
1063 (Zmmword): Likewise.
1064 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1066 * i386-tbl.h: Regenerated.
1068 2018-07-12 Sudakshina Das <sudi.das@arm.com>
1070 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1071 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1072 * aarch64-asm-2.c: Regenerate.
1073 * aarch64-dis-2.c: Regenerate.
1074 * aarch64-opc-2.c: Regenerate.
1076 2018-07-12 Tamar Christina <tamar.christina@arm.com>
1079 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1080 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1081 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1082 sqdmulh, sqrdmulh): Use Em16.
1084 2018-07-11 Sudakshina Das <sudi.das@arm.com>
1086 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1087 csdb together with them.
1088 (thumb32_opcodes): Likewise.
1090 2018-07-11 Jan Beulich <jbeulich@suse.com>
1092 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1093 requiring 32-bit registers as operands 2 and 3. Improve
1095 (mwait, mwaitx): Fold templates. Improve comments.
1096 OPERAND_TYPE_INOUTPORTREG.
1097 * i386-tbl.h: Re-generate.
1099 2018-07-11 Jan Beulich <jbeulich@suse.com>
1101 * i386-gen.c (operand_type_init): Remove
1102 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1103 OPERAND_TYPE_INOUTPORTREG.
1104 * i386-init.h: Re-generate.
1106 2018-07-11 Jan Beulich <jbeulich@suse.com>
1108 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1109 (wrssq, wrussq): Add Qword.
1110 * i386-tbl.h: Re-generate.
1112 2018-07-11 Jan Beulich <jbeulich@suse.com>
1114 * i386-opc.h: Rename OTMax to OTNum.
1115 (OTNumOfUints): Adjust calculation.
1116 (OTUnused): Directly alias to OTNum.
1118 2018-07-09 Maciej W. Rozycki <macro@mips.com>
1120 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1122 (lea_reg_xys): Likewise.
1123 (print_insn_loop_primitive): Rename `reg' local variable to
1126 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1129 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1131 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1134 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1135 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1137 2018-07-02 Maciej W. Rozycki <macro@mips.com>
1140 * mips-dis.c (mips_option_arg_t): New enumeration.
1141 (mips_options): New variable.
1142 (disassembler_options_mips): New function.
1143 (print_mips_disassembler_options): Reimplement in terms of
1144 `disassembler_options_mips'.
1145 * arm-dis.c (disassembler_options_arm): Adapt to using the
1146 `disasm_options_and_args_t' structure.
1147 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1148 * s390-dis.c (disassembler_options_s390): Likewise.
1150 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1152 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1154 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1155 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1156 * testsuite/ld-arm/tls-longplt.d: Likewise.
1158 2018-06-29 Tamar Christina <tamar.christina@arm.com>
1161 * aarch64-asm-2.c: Regenerate.
1162 * aarch64-dis-2.c: Likewise.
1163 * aarch64-opc-2.c: Likewise.
1164 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1165 * aarch64-opc.c (operand_general_constraint_met_p,
1166 aarch64_print_operand): Likewise.
1167 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1168 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1170 (AARCH64_OPERANDS): Add Em2.
1172 2018-06-26 Nick Clifton <nickc@redhat.com>
1174 * po/uk.po: Updated Ukranian translation.
1175 * po/de.po: Updated German translation.
1176 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1178 2018-06-26 Nick Clifton <nickc@redhat.com>
1180 * nfp-dis.c: Fix spelling mistake.
1182 2018-06-24 Nick Clifton <nickc@redhat.com>
1184 * configure: Regenerate.
1185 * po/opcodes.pot: Regenerate.
1187 2018-06-24 Nick Clifton <nickc@redhat.com>
1189 2.31 branch created.
1191 2018-06-19 Tamar Christina <tamar.christina@arm.com>
1193 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1194 * aarch64-asm-2.c: Regenerate.
1195 * aarch64-dis-2.c: Likewise.
1197 2018-06-21 Maciej W. Rozycki <macro@mips.com>
1199 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1200 `-M ginv' option description.
1202 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1205 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1208 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1210 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1211 * configure.ac: Remove AC_PREREQ.
1212 * Makefile.in: Re-generate.
1213 * aclocal.m4: Re-generate.
1214 * configure: Re-generate.
1216 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1218 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1219 mips64r6 descriptors.
1220 (parse_mips_ase_option): Handle -Mginv option.
1221 (print_mips_disassembler_options): Document -Mginv.
1222 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1224 (mips_opcodes): Define ginvi and ginvt.
1226 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1227 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1229 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1230 * mips-opc.c (CRC, CRC64): New macros.
1231 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1232 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1235 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1238 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1239 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1241 2018-06-06 Alan Modra <amodra@gmail.com>
1243 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1244 setjmp. Move init for some other vars later too.
1246 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1248 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1249 (dis_private): Add new fields for property section tracking.
1250 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1251 (xtensa_instruction_fits): New functions.
1252 (fetch_data): Bump minimal fetch size to 4.
1253 (print_insn_xtensa): Make struct dis_private static.
1254 Load and prepare property table on section change.
1255 Don't disassemble literals. Don't disassemble instructions that
1256 cross property table boundaries.
1258 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1260 * configure: Regenerated.
1262 2018-06-01 Jan Beulich <jbeulich@suse.com>
1264 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1265 * i386-tbl.h: Re-generate.
1267 2018-06-01 Jan Beulich <jbeulich@suse.com>
1269 * i386-opc.tbl (sldt, str): Add NoRex64.
1270 * i386-tbl.h: Re-generate.
1272 2018-06-01 Jan Beulich <jbeulich@suse.com>
1274 * i386-opc.tbl (invpcid): Add Oword.
1275 * i386-tbl.h: Re-generate.
1277 2018-06-01 Alan Modra <amodra@gmail.com>
1279 * sysdep.h (_bfd_error_handler): Don't declare.
1280 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1281 * rl78-decode.opc: Likewise.
1282 * msp430-decode.c: Regenerate.
1283 * rl78-decode.c: Regenerate.
1285 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1287 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1288 * i386-init.h : Regenerated.
1290 2018-05-25 Alan Modra <amodra@gmail.com>
1292 * Makefile.in: Regenerate.
1293 * po/POTFILES.in: Regenerate.
1295 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1297 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1298 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1299 (insert_bab, extract_bab, insert_btab, extract_btab,
1300 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1301 (BAT, BBA VBA RBS XB6S): Delete macros.
1302 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1303 (BB, BD, RBX, XC6): Update for new macros.
1304 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1305 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1306 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1307 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1309 2018-05-18 John Darrington <john@darrington.wattle.id.au>
1311 * Makefile.am: Add support for s12z architecture.
1312 * configure.ac: Likewise.
1313 * disassemble.c: Likewise.
1314 * disassemble.h: Likewise.
1315 * Makefile.in: Regenerate.
1316 * configure: Regenerate.
1317 * s12z-dis.c: New file.
1320 2018-05-18 Alan Modra <amodra@gmail.com>
1322 * nfp-dis.c: Don't #include libbfd.h.
1323 (init_nfp3200_priv): Use bfd_get_section_contents.
1324 (nit_nfp6000_mecsr_sec): Likewise.
1326 2018-05-17 Nick Clifton <nickc@redhat.com>
1328 * po/zh_CN.po: Updated simplified Chinese translation.
1330 2018-05-16 Tamar Christina <tamar.christina@arm.com>
1333 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1334 * aarch64-dis-2.c: Regenerate.
1336 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1339 * aarch64-asm.c (opintl.h): Include.
1340 (aarch64_ins_sysreg): Enforce read/write constraints.
1341 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1342 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1343 (F_REG_READ, F_REG_WRITE): New.
1344 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1345 AARCH64_OPND_SYSREG.
1346 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1347 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1348 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1349 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1350 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1351 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1352 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1353 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1354 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1355 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1356 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1357 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1358 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1359 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1360 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1361 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1362 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1364 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1367 * aarch64-dis.c (no_notes: New.
1368 (parse_aarch64_dis_option): Support notes.
1369 (aarch64_decode_insn, print_operands): Likewise.
1370 (print_aarch64_disassembler_options): Document notes.
1371 * aarch64-opc.c (aarch64_print_operand): Support notes.
1373 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1376 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1377 and take error struct.
1378 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1379 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1380 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1381 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1382 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1383 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1384 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1385 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1386 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1387 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1388 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1389 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1390 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1391 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1392 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1393 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1394 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1395 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1396 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1397 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1398 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1399 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1400 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1401 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1402 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1403 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1404 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1405 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1406 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1407 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1408 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1409 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1410 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1411 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1412 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1413 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1414 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1415 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1416 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1417 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1418 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1419 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1420 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1421 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1422 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1423 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1424 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1425 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1426 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1427 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1428 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1429 (determine_disassembling_preference, aarch64_decode_insn,
1430 print_insn_aarch64_word, print_insn_data): Take errors struct.
1431 (print_insn_aarch64): Use errors.
1432 * aarch64-asm-2.c: Regenerate.
1433 * aarch64-dis-2.c: Regenerate.
1434 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1435 boolean in aarch64_insert_operan.
1436 (print_operand_extractor): Likewise.
1437 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1439 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
1441 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1443 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1445 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1447 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1449 * cr16-opc.c (cr16_instruction): Comment typo fix.
1450 * hppa-dis.c (print_insn_hppa): Likewise.
1452 2018-05-08 Jim Wilson <jimw@sifive.com>
1454 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1455 (match_c_slli64, match_srxi_as_c_srxi): New.
1456 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1457 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1458 <c.slli, c.srli, c.srai>: Use match_s_slli.
1459 <c.slli64, c.srli64, c.srai64>: New.
1461 2018-05-08 Alan Modra <amodra@gmail.com>
1463 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1464 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1465 partition opcode space for index lookup.
1467 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1469 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1470 <insn_length>: ...with this. Update usage.
1471 Remove duplicate call to *info->memory_error_func.
1473 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1474 H.J. Lu <hongjiu.lu@intel.com>
1476 * i386-dis.c (Gva): New.
1477 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1478 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1479 (prefix_table): New instructions (see prefix above).
1480 (mod_table): New instructions (see prefix above).
1481 (OP_G): Handle va_mode.
1482 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1483 CPU_MOVDIR64B_FLAGS.
1484 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1485 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1486 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1487 * i386-opc.tbl: Add movidir{i,64b}.
1488 * i386-init.h: Regenerated.
1489 * i386-tbl.h: Likewise.
1491 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1493 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1495 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1496 (AddrPrefixOpReg): This.
1497 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1498 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1500 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1502 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1503 (vle_num_opcodes): Likewise.
1504 (spe2_num_opcodes): Likewise.
1505 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1506 initialization loop.
1507 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1508 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1511 2018-05-01 Tamar Christina <tamar.christina@arm.com>
1513 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1515 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
1517 Makefile.am: Added nfp-dis.c.
1518 configure.ac: Added bfd_nfp_arch.
1519 disassemble.h: Added print_insn_nfp prototype.
1520 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1521 nfp-dis.c: New, for NFP support.
1522 po/POTFILES.in: Added nfp-dis.c to the list.
1523 Makefile.in: Regenerate.
1524 configure: Regenerate.
1526 2018-04-26 Jan Beulich <jbeulich@suse.com>
1528 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1529 templates into their base ones.
1530 * i386-tlb.h: Re-generate.
1532 2018-04-26 Jan Beulich <jbeulich@suse.com>
1534 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1535 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1536 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1537 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1538 * i386-init.h: Re-generate.
1540 2018-04-26 Jan Beulich <jbeulich@suse.com>
1542 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1543 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1544 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1545 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1547 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1549 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1551 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1552 cpuregzmm, and cpuregmask.
1553 * i386-init.h: Re-generate.
1554 * i386-tbl.h: Re-generate.
1556 2018-04-26 Jan Beulich <jbeulich@suse.com>
1558 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1559 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1560 * i386-init.h: Re-generate.
1562 2018-04-26 Jan Beulich <jbeulich@suse.com>
1564 * i386-gen.c (VexImmExt): Delete.
1565 * i386-opc.h (VexImmExt, veximmext): Delete.
1566 * i386-opc.tbl: Drop all VexImmExt uses.
1567 * i386-tlb.h: Re-generate.
1569 2018-04-25 Jan Beulich <jbeulich@suse.com>
1571 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1572 register-only forms.
1573 * i386-tlb.h: Re-generate.
1575 2018-04-25 Tamar Christina <tamar.christina@arm.com>
1577 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1579 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1581 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1583 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1584 (cpu_flags): Add CpuCLDEMOTE.
1585 * i386-init.h: Regenerate.
1586 * i386-opc.h (enum): Add CpuCLDEMOTE,
1587 (i386_cpu_flags): Add cpucldemote.
1588 * i386-opc.tbl: Add cldemote.
1589 * i386-tbl.h: Regenerate.
1591 2018-04-16 Alan Modra <amodra@gmail.com>
1593 * Makefile.am: Remove sh5 and sh64 support.
1594 * configure.ac: Likewise.
1595 * disassemble.c: Likewise.
1596 * disassemble.h: Likewise.
1597 * sh-dis.c: Likewise.
1598 * sh64-dis.c: Delete.
1599 * sh64-opc.c: Delete.
1600 * sh64-opc.h: Delete.
1601 * Makefile.in: Regenerate.
1602 * configure: Regenerate.
1603 * po/POTFILES.in: Regenerate.
1605 2018-04-16 Alan Modra <amodra@gmail.com>
1607 * Makefile.am: Remove w65 support.
1608 * configure.ac: Likewise.
1609 * disassemble.c: Likewise.
1610 * disassemble.h: Likewise.
1611 * w65-dis.c: Delete.
1612 * w65-opc.h: Delete.
1613 * Makefile.in: Regenerate.
1614 * configure: Regenerate.
1615 * po/POTFILES.in: Regenerate.
1617 2018-04-16 Alan Modra <amodra@gmail.com>
1619 * configure.ac: Remove we32k support.
1620 * configure: Regenerate.
1622 2018-04-16 Alan Modra <amodra@gmail.com>
1624 * Makefile.am: Remove m88k support.
1625 * configure.ac: Likewise.
1626 * disassemble.c: Likewise.
1627 * disassemble.h: Likewise.
1628 * m88k-dis.c: Delete.
1629 * Makefile.in: Regenerate.
1630 * configure: Regenerate.
1631 * po/POTFILES.in: Regenerate.
1633 2018-04-16 Alan Modra <amodra@gmail.com>
1635 * Makefile.am: Remove i370 support.
1636 * configure.ac: Likewise.
1637 * disassemble.c: Likewise.
1638 * disassemble.h: Likewise.
1639 * i370-dis.c: Delete.
1640 * i370-opc.c: Delete.
1641 * Makefile.in: Regenerate.
1642 * configure: Regenerate.
1643 * po/POTFILES.in: Regenerate.
1645 2018-04-16 Alan Modra <amodra@gmail.com>
1647 * Makefile.am: Remove h8500 support.
1648 * configure.ac: Likewise.
1649 * disassemble.c: Likewise.
1650 * disassemble.h: Likewise.
1651 * h8500-dis.c: Delete.
1652 * h8500-opc.h: Delete.
1653 * Makefile.in: Regenerate.
1654 * configure: Regenerate.
1655 * po/POTFILES.in: Regenerate.
1657 2018-04-16 Alan Modra <amodra@gmail.com>
1659 * configure.ac: Remove tahoe support.
1660 * configure: Regenerate.
1662 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1664 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1666 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1668 * i386-tbl.h: Regenerated.
1670 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1672 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1673 PREFIX_MOD_1_0FAE_REG_6.
1675 (OP_E_register): Use va_mode.
1676 * i386-dis-evex.h (prefix_table):
1677 New instructions (see prefixes above).
1678 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1679 (cpu_flags): Likewise.
1680 * i386-opc.h (enum): Likewise.
1681 (i386_cpu_flags): Likewise.
1682 * i386-opc.tbl: Add umonitor, umwait, tpause.
1683 * i386-init.h: Regenerate.
1684 * i386-tbl.h: Likewise.
1686 2018-04-11 Alan Modra <amodra@gmail.com>
1688 * opcodes/i860-dis.c: Delete.
1689 * opcodes/i960-dis.c: Delete.
1690 * Makefile.am: Remove i860 and i960 support.
1691 * configure.ac: Likewise.
1692 * disassemble.c: Likewise.
1693 * disassemble.h: Likewise.
1694 * Makefile.in: Regenerate.
1695 * configure: Regenerate.
1696 * po/POTFILES.in: Regenerate.
1698 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1701 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1703 (print_insn): Clear vex instead of vex.evex.
1705 2018-04-04 Nick Clifton <nickc@redhat.com>
1707 * po/es.po: Updated Spanish translation.
1709 2018-03-28 Jan Beulich <jbeulich@suse.com>
1711 * i386-gen.c (opcode_modifiers): Delete VecESize.
1712 * i386-opc.h (VecESize): Delete.
1713 (struct i386_opcode_modifier): Delete vecesize.
1714 * i386-opc.tbl: Drop VecESize.
1715 * i386-tlb.h: Re-generate.
1717 2018-03-28 Jan Beulich <jbeulich@suse.com>
1719 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1720 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1721 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1722 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1723 * i386-tlb.h: Re-generate.
1725 2018-03-28 Jan Beulich <jbeulich@suse.com>
1727 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1729 * i386-tlb.h: Re-generate.
1731 2018-03-28 Jan Beulich <jbeulich@suse.com>
1733 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1734 (vex_len_table): Drop Y for vcvt*2si.
1735 (putop): Replace plain 'Y' handling by abort().
1737 2018-03-28 Nick Clifton <nickc@redhat.com>
1740 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1741 instructions with only a base address register.
1742 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1743 handle AARHC64_OPND_SVE_ADDR_R.
1744 (aarch64_print_operand): Likewise.
1745 * aarch64-asm-2.c: Regenerate.
1746 * aarch64_dis-2.c: Regenerate.
1747 * aarch64-opc-2.c: Regenerate.
1749 2018-03-22 Jan Beulich <jbeulich@suse.com>
1751 * i386-opc.tbl: Drop VecESize from register only insn forms and
1752 memory forms not allowing broadcast.
1753 * i386-tlb.h: Re-generate.
1755 2018-03-22 Jan Beulich <jbeulich@suse.com>
1757 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1758 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1759 sha256*): Drop Disp<N>.
1761 2018-03-22 Jan Beulich <jbeulich@suse.com>
1763 * i386-dis.c (EbndS, bnd_swap_mode): New.
1764 (prefix_table): Use EbndS.
1765 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1766 * i386-opc.tbl (bndmov): Move misplaced Load.
1767 * i386-tlb.h: Re-generate.
1769 2018-03-22 Jan Beulich <jbeulich@suse.com>
1771 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1772 templates allowing memory operands and folded ones for register
1774 * i386-tlb.h: Re-generate.
1776 2018-03-22 Jan Beulich <jbeulich@suse.com>
1778 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1779 256-bit templates. Drop redundant leftover Disp<N>.
1780 * i386-tlb.h: Re-generate.
1782 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1784 * riscv-opc.c (riscv_insn_types): New.
1786 2018-03-13 Nick Clifton <nickc@redhat.com>
1788 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1790 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1792 * i386-opc.tbl: Add Optimize to clr.
1793 * i386-tbl.h: Regenerated.
1795 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1797 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1798 * i386-opc.h (OldGcc): Removed.
1799 (i386_opcode_modifier): Remove oldgcc.
1800 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1801 instructions for old (<= 2.8.1) versions of gcc.
1802 * i386-tbl.h: Regenerated.
1804 2018-03-08 Jan Beulich <jbeulich@suse.com>
1806 * i386-opc.h (EVEXDYN): New.
1807 * i386-opc.tbl: Fold various AVX512VL templates.
1808 * i386-tlb.h: Re-generate.
1810 2018-03-08 Jan Beulich <jbeulich@suse.com>
1812 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1813 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1814 vpexpandd, vpexpandq): Fold AFX512VF templates.
1815 * i386-tlb.h: Re-generate.
1817 2018-03-08 Jan Beulich <jbeulich@suse.com>
1819 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1820 Fold 128- and 256-bit VEX-encoded templates.
1821 * i386-tlb.h: Re-generate.
1823 2018-03-08 Jan Beulich <jbeulich@suse.com>
1825 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1826 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1827 vpexpandd, vpexpandq): Fold AVX512F templates.
1828 * i386-tlb.h: Re-generate.
1830 2018-03-08 Jan Beulich <jbeulich@suse.com>
1832 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1833 64-bit templates. Drop Disp<N>.
1834 * i386-tlb.h: Re-generate.
1836 2018-03-08 Jan Beulich <jbeulich@suse.com>
1838 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1839 and 256-bit templates.
1840 * i386-tlb.h: Re-generate.
1842 2018-03-08 Jan Beulich <jbeulich@suse.com>
1844 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1845 * i386-tlb.h: Re-generate.
1847 2018-03-08 Jan Beulich <jbeulich@suse.com>
1849 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1851 * i386-tlb.h: Re-generate.
1853 2018-03-08 Jan Beulich <jbeulich@suse.com>
1855 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1856 * i386-tlb.h: Re-generate.
1858 2018-03-08 Jan Beulich <jbeulich@suse.com>
1860 * i386-gen.c (opcode_modifiers): Delete FloatD.
1861 * i386-opc.h (FloatD): Delete.
1862 (struct i386_opcode_modifier): Delete floatd.
1863 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1865 * i386-tlb.h: Re-generate.
1867 2018-03-08 Jan Beulich <jbeulich@suse.com>
1869 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1871 2018-03-08 Jan Beulich <jbeulich@suse.com>
1873 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1874 * i386-tlb.h: Re-generate.
1876 2018-03-08 Jan Beulich <jbeulich@suse.com>
1878 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1880 * i386-tlb.h: Re-generate.
1882 2018-03-07 Alan Modra <amodra@gmail.com>
1884 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1886 * disassemble.h (print_insn_rs6000): Delete.
1887 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1888 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1889 (print_insn_rs6000): Delete.
1891 2018-03-03 Alan Modra <amodra@gmail.com>
1893 * sysdep.h (opcodes_error_handler): Define.
1894 (_bfd_error_handler): Declare.
1895 * Makefile.am: Remove stray #.
1896 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1898 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1899 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1900 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1901 opcodes_error_handler to print errors. Standardize error messages.
1902 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1903 and include opintl.h.
1904 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1905 * i386-gen.c: Standardize error messages.
1906 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1907 * Makefile.in: Regenerate.
1908 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1909 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1910 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1911 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1912 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1913 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1914 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1915 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1916 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1917 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1918 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1919 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1920 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1922 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1924 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1925 vpsub[bwdq] instructions.
1926 * i386-tbl.h: Regenerated.
1928 2018-03-01 Alan Modra <amodra@gmail.com>
1930 * configure.ac (ALL_LINGUAS): Sort.
1931 * configure: Regenerate.
1933 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1935 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1936 macro by assignements.
1938 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1941 * i386-gen.c (opcode_modifiers): Add Optimize.
1942 * i386-opc.h (Optimize): New enum.
1943 (i386_opcode_modifier): Add optimize.
1944 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1945 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1946 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1947 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1948 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1950 * i386-tbl.h: Regenerated.
1952 2018-02-26 Alan Modra <amodra@gmail.com>
1954 * crx-dis.c (getregliststring): Allocate a large enough buffer
1955 to silence false positive gcc8 warning.
1957 2018-02-22 Shea Levy <shea@shealevy.com>
1959 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1961 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1963 * i386-opc.tbl: Add {rex},
1964 * i386-tbl.h: Regenerated.
1966 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1968 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1969 (mips16_opcodes): Replace `M' with `m' for "restore".
1971 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1973 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1975 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1977 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1978 variable to `function_index'.
1980 2018-02-13 Nick Clifton <nickc@redhat.com>
1983 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1984 about truncation of printing.
1986 2018-02-12 Henry Wong <henry@stuffedcow.net>
1988 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1990 2018-02-05 Nick Clifton <nickc@redhat.com>
1992 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1994 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1996 * i386-dis.c (enum): Add pconfig.
1997 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1998 (cpu_flags): Add CpuPCONFIG.
1999 * i386-opc.h (enum): Add CpuPCONFIG.
2000 (i386_cpu_flags): Add cpupconfig.
2001 * i386-opc.tbl: Add PCONFIG instruction.
2002 * i386-init.h: Regenerate.
2003 * i386-tbl.h: Likewise.
2005 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2007 * i386-dis.c (enum): Add PREFIX_0F09.
2008 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2009 (cpu_flags): Add CpuWBNOINVD.
2010 * i386-opc.h (enum): Add CpuWBNOINVD.
2011 (i386_cpu_flags): Add cpuwbnoinvd.
2012 * i386-opc.tbl: Add WBNOINVD instruction.
2013 * i386-init.h: Regenerate.
2014 * i386-tbl.h: Likewise.
2016 2018-01-17 Jim Wilson <jimw@sifive.com>
2018 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2020 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2022 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2023 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2024 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2025 (cpu_flags): Add CpuIBT, CpuSHSTK.
2026 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2027 (i386_cpu_flags): Add cpuibt, cpushstk.
2028 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2029 * i386-init.h: Regenerate.
2030 * i386-tbl.h: Likewise.
2032 2018-01-16 Nick Clifton <nickc@redhat.com>
2034 * po/pt_BR.po: Updated Brazilian Portugese translation.
2035 * po/de.po: Updated German translation.
2037 2018-01-15 Jim Wilson <jimw@sifive.com>
2039 * riscv-opc.c (match_c_nop): New.
2040 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2042 2018-01-15 Nick Clifton <nickc@redhat.com>
2044 * po/uk.po: Updated Ukranian translation.
2046 2018-01-13 Nick Clifton <nickc@redhat.com>
2048 * po/opcodes.pot: Regenerated.
2050 2018-01-13 Nick Clifton <nickc@redhat.com>
2052 * configure: Regenerate.
2054 2018-01-13 Nick Clifton <nickc@redhat.com>
2056 2.30 branch created.
2058 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2060 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2061 * i386-tbl.h: Regenerate.
2063 2018-01-10 Jan Beulich <jbeulich@suse.com>
2065 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2066 * i386-tbl.h: Re-generate.
2068 2018-01-10 Jan Beulich <jbeulich@suse.com>
2070 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2071 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2072 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2073 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2074 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2075 Disp8MemShift of AVX512VL forms.
2076 * i386-tbl.h: Re-generate.
2078 2018-01-09 Jim Wilson <jimw@sifive.com>
2080 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2081 then the hi_addr value is zero.
2083 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2085 * arm-dis.c (arm_opcodes): Add csdb.
2086 (thumb32_opcodes): Add csdb.
2088 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2090 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2091 * aarch64-asm-2.c: Regenerate.
2092 * aarch64-dis-2.c: Regenerate.
2093 * aarch64-opc-2.c: Regenerate.
2095 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2098 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2099 Remove AVX512 vmovd with 64-bit operands.
2100 * i386-tbl.h: Regenerated.
2102 2018-01-05 Jim Wilson <jimw@sifive.com>
2104 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2107 2018-01-03 Alan Modra <amodra@gmail.com>
2109 Update year range in copyright notice of all files.
2111 2018-01-02 Jan Beulich <jbeulich@suse.com>
2113 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2114 and OPERAND_TYPE_REGZMM entries.
2116 For older changes see ChangeLog-2017
2118 Copyright (C) 2018 Free Software Foundation, Inc.
2120 Copying and distribution of this file, with or without modification,
2121 are permitted in any medium without royalty provided the copyright
2122 notice and this notice are preserved.
2128 version-control: never