opcodes/ChangeLog

   1 2016-12-20  Alan Modra  <amodra@gmail.com>
   2
   3         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
   4         * Makefile.in: Regenerate.
   5         * po/POTFILES.in: Regenerate.
   6
   7 2016-12-19  Maciej W. Rozycki  <macro@imgtec.com>
   8
   9         * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
  10         Only examine ELF file structures here.
  11
  12 2016-12-19  Maciej W. Rozycki  <macro@imgtec.com>
  13
  14         * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
  15         `bfd_mips_elf_get_abiflags' here.
  16
  17 2016-12-16  Nick Clifton  <nickc@redhat.com>
  18
  19         * arm-dis.c (print_insn_thumb32): Fix compile time warning
  20         computing value_in_comment.
  21
  22 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  23
  24         * mips-dis.c (mips_convert_abiflags_ases): New function.
  25         (set_default_mips_dis_options): Also infer ASE flags from ELF
  26         file structures.
  27
  28 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  29
  30         * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
  31         header flag interpretation code.
  32
  33 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  34
  35         * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
  36         `pinfo2' with SP-relative "sd" entries.
  37
  38 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  39
  40         * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
  41         compact jumps.
  42
  43 2016-12-13 Renlin Li <renlin.li@arm.com>
  44
  45         * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
  46         qualifier.
  47         (operand_general_constraint_met_p): Remove case for CP_REG.
  48         (aarch64_print_operand): Print CRn, CRm operand using imm field.
  49         * aarch64-tbl.h (QL_SYS): Use CR qualifier.
  50         (QL_SYSL): Likewise.
  51         (aarch64_opcode_table): Change CRn, CRm operand class and type.
  52         * aarch64-opc-2.c : Regenerate.
  53         * aarch64-asm-2.c : Likewise.
  54         * aarch64-dis-2.c : Likewise.
  55
  56 2016-12-12  Yao Qi  <yao.qi@linaro.org>
  57
  58         * rx-dis.c: Include <setjmp.h>
  59         (struct private): New.
  60         (rx_get_byte): Check return value of read_memory_func, and
  61         call memory_error_func and OPCODES_SIGLONGJMP on error.
  62         (print_insn_rx): Call OPCODES_SIGSETJMP.
  63
  64 2016-12-12  Yao Qi  <yao.qi@linaro.org>
  65
  66         * rl78-dis.c: Include <setjmp.h>.
  67         (struct private): New.
  68         (rl78_get_byte): Check return value of read_memory_func, and
  69         call memory_error_func and OPCODES_SIGLONGJMP on error.
  70         (print_insn_rl78_common): Call OPCODES_SIGJMP.
  71
  72 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
  73
  74         * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
  75
  76 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
  77
  78         * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
  79         than UINT.
  80
  81 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
  82
  83         * mips-dis.c (print_insn_mips16): Use a tab rather than a space
  84         to separate `extend' and its uninterpreted argument output.
  85         Separate hexadecimal halves of undecoded extended instructions
  86         output.
  87
  88 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
  89
  90         * mips-dis.c (print_mips16_insn_arg): Remove extraneous
  91         indentation space across.
  92
  93 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
  94
  95         * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
  96         adjustment for PC-relative operations following MIPS16e compact
  97         jumps or undefined RR/J(AL)R(C) encodings.
  98
  99 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
 100
 101         * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
 102         variable to `reglane_index'.
 103
 104 2016-12-08  Luis Machado  <lgustavo@codesourcery.com>
 105
 106         * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
 107
 108 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 109
 110         * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
 111
 112 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 113
 114         * mips16-opc.c (mips16_opcodes): Update comment naming structure
 115         members.
 116
 117 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 118
 119         * mips-dis.c (print_mips_disassembler_options): Reformat output.
 120
 121 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 122
 123         * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
 124         (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
 125
 126 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 127
 128         * arm-dis.c (coprocessor_opcodes): Add vjcvt.
 129
 130 2016-12-01  Nick Clifton  <nickc@redhat.com>
 131
 132         PR binutils/20893
 133         * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
 134         opcode designator.
 135
 136 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
 137
 138         * arc-opc.c (insert_ra_chk): New function.
 139         (insert_rb_chk): Likewise.
 140         (insert_rad): Update text error message.
 141         (insert_rcd): Likewise.
 142         (insert_rhv2): Likewise.
 143         (insert_r0): Likewise.
 144         (insert_r1): Likewise.
 145         (insert_r2): Likewise.
 146         (insert_r3): Likewise.
 147         (insert_sp): Likewise.
 148         (insert_gp): Likewise.
 149         (insert_pcl): Likewise.
 150         (insert_blink): Likewise.
 151         (insert_ilink1): Likewise.
 152         (insert_ilink2): Likewise.
 153         (insert_ras): Likewise.
 154         (insert_rbs): Likewise.
 155         (insert_rcs): Likewise.
 156         (insert_simm3s): Likewise.
 157         (insert_rrange): Likewise.
 158         (insert_fpel): Likewise.
 159         (insert_blinkel): Likewise.
 160         (insert_pcel): Likewise.
 161         (insert_nps_3bit_dst): Likewise.
 162         (insert_nps_3bit_dst_short): Likewise.
 163         (insert_nps_3bit_src2_short): Likewise.
 164         (insert_nps_bitop_size_2b): Likewise.
 165         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
 166         (RA_CHK): Define.
 167         (RB): Adjust.
 168         (RB_CHK): Define.
 169         (RC): Adjust.
 170         * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
 171         * arc-tbl.h (div, divu): All instructions are DIVREM class.
 172         Change first insn argument to check for LP_COUNT usage.
 173         (rem): Likewise.
 174         (ld, ldd): All instructions are LOAD class.  Change first insn
 175         argument to check for LP_COUNT usage.
 176         (st, std): All instructions are STORE class.
 177         (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
 178         Change first insn argument to check for LP_COUNT usage.
 179         (mov): All instructions are MOVE class.  Change first insn
 180         argument to check for LP_COUNT usage.
 181
 182 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
 183
 184         * arc-dis.c (is_compatible_p): Remove function.
 185         (skip_this_opcode): Don't add any decoding class to decode list.
 186         Remove warning.
 187         (find_format_from_table): Go through all opcodes, and warn if we
 188         use a guessed mnemonic.
 189
 190 2016-11-28  Ramiro Polla  <ramiro@hex-rays.com>
 191             Amit Pawar  <amit.pawar@amd.com>
 192
 193         PR binutils/20637
 194         * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
 195         instructions.
 196
 197 2016-11-22  Ambrogino Modigliani  <ambrogino.modigliani@gmail.com>
 198
 199         * configure: Regenerate.
 200
 201 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 202
 203         * sparc-opc.c (HWS_V8): Definition moved from
 204         gas/config/tc-sparc.c.
 205         (HWS_V9): Likewise.
 206         (HWS_VA): Likewise.
 207         (HWS_VB): Likewise.
 208         (HWS_VC): Likewise.
 209         (HWS_VD): Likewise.
 210         (HWS_VE): Likewise.
 211         (HWS_VV): Likewise.
 212         (HWS_VM): Likewise.
 213         (HWS2_VM): Likewise.
 214         (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
 215         existing entries.
 216
 217 2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
 218
 219         * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
 220         instructions.
 221
 222 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 223
 224         * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
 225         (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
 226         (aarch64_opcode_table): Add fcmla and fcadd.
 227         (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
 228         * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
 229         * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
 230         * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
 231         * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
 232         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
 233         * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
 234         (operand_general_constraint_met_p): Rotate and index range check.
 235         (aarch64_print_operand): Handle rotate operand.
 236         * aarch64-asm-2.c: Regenerate.
 237         * aarch64-dis-2.c: Likewise.
 238         * aarch64-opc-2.c: Likewise.
 239
 240 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 241
 242         * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
 243         * aarch64-asm-2.c: Regenerate.
 244         * aarch64-dis-2.c: Regenerate.
 245         * aarch64-opc-2.c: Regenerate.
 246
 247 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 248
 249         * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
 250         (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
 251         * aarch64-asm-2.c: Regenerate.
 252         * aarch64-dis-2.c: Regenerate.
 253         * aarch64-opc-2.c: Regenerate.
 254
 255 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 256
 257         * aarch64-tbl.h (QL_X1NIL): New.
 258         (arch64_opcode_table): Add ldraa, ldrab.
 259         (AARCH64_OPERANDS): Add "ADDR_SIMM10".
 260         * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
 261         * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
 262         * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
 263         * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
 264         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
 265         * aarch64-opc.c (fields): Add data for FLD_S_simm10.
 266         (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
 267         (aarch64_print_operand): Likewise.
 268         * aarch64-asm-2.c: Regenerate.
 269         * aarch64-dis-2.c: Regenerate.
 270         * aarch64-opc-2.c: Regenerate.
 271
 272 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 273
 274         * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
 275         brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
 276         * aarch64-asm-2.c: Regenerate.
 277         * aarch64-dis-2.c: Regenerate.
 278         * aarch64-opc-2.c: Regenerate.
 279
 280 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 281
 282         * aarch64-tbl.h (arch64_opcode_table): Add pacga.
 283         (AARCH64_OPERANDS): Add Rm_SP.
 284         * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
 285         * aarch64-asm-2.c: Regenerate.
 286         * aarch64-dis-2.c: Regenerate.
 287         * aarch64-opc-2.c: Regenerate.
 288
 289 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 290
 291         * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
 292         autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
 293         autdzb, xpaci, xpacd.
 294         * aarch64-asm-2.c: Regenerate.
 295         * aarch64-dis-2.c: Regenerate.
 296         * aarch64-opc-2.c: Regenerate.
 297
 298 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 299
 300         * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
 301         apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
 302         apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
 303         (aarch64_sys_reg_supported_p): Add feature test for new registers.
 304
 305 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 306
 307         * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
 308         (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
 309         autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
 310         autibsp.
 311         * aarch64-asm-2.c: Regenerate.
 312         * aarch64-dis-2.c: Regenerate.
 313
 314 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 315
 316         * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
 317
 318 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 319
 320         PR binutils/20799
 321         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
 322         * i386-dis.c (EdqwS): Removed.
 323         (dqw_swap_mode): Likewise.
 324         (intel_operand_size): Don't check dqw_swap_mode.
 325         (OP_E_register): Likewise.
 326         (OP_E_memory): Likewise.
 327         (OP_G): Likewise.
 328         (OP_EX): Likewise.
 329         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
 330         * i386-tbl.h: Regerated.
 331
 332 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 333
 334         * i386-opc.tbl: Merge AVX512F vmovq.
 335         * i386-tbl.h: Regerated.
 336
 337 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 338
 339         PR binutils/20701
 340         * i386-dis.c (THREE_BYTE_0F7A): Removed.
 341         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
 342         (three_byte_table): Remove THREE_BYTE_0F7A.
 343
 344 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
 345
 346         PR binutils/20775
 347         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
 348         (FGRPd9_4): Replace 1 with 2.
 349         (FGRPd9_5): Replace 2 with 3.
 350         (FGRPd9_6): Replace 3 with 4.
 351         (FGRPd9_7): Replace 4 with 5.
 352         (FGRPda_5): Replace 5 with 6.
 353         (FGRPdb_4): Replace 6 with 7.
 354         (FGRPde_3): Replace 7 with 8.
 355         (FGRPdf_4): Replace 8 with 9.
 356         (fgrps): Add an entry for Bad_Opcode.
 357
 358 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
 359
 360         * arc-opc.c (arc_flag_operands): Add F_DI14.
 361         (arc_flag_classes): Add C_DI14.
 362         * arc-nps400-tbl.h: Add new exc instructions.
 363
 364 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 365
 366         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
 367         major opcode 0xa.
 368         * arc-nps-400-tbl.h: Add dcmac instruction.
 369         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
 370         (insert_nps_rbdouble_64): Added.
 371         (extract_nps_rbdouble_64): Added.
 372         (insert_nps_proto_size): Added.
 373         (extract_nps_proto_size): Added.
 374
 375 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 376
 377         * arc-dis.c (struct arc_operand_iterator): Remove all fields
 378         relating to long instruction processing, add new limm field.
 379         (OPCODE): Rename to...
 380         (OPCODE_32BIT_INSN): ...this.
 381         (OPCODE_AC): Delete.
 382         (skip_this_opcode): Handle different instruction lengths, update
 383         macro name.
 384         (special_flag_p): Update parameter type.
 385         (find_format_from_table): Update for more instruction lengths.
 386         (find_format_long_instructions): Delete.
 387         (find_format): Update for more instruction lengths.
 388         (arc_insn_length): Likewise.
 389         (extract_operand_value): Update for more instruction lengths.
 390         (operand_iterator_next): Remove code relating to long
 391         instructions.
 392         (arc_opcode_to_insn_type): New function.
 393         (print_insn_arc):Update for more instructions lengths.
 394         * arc-ext.c (extInstruction_t): Change argument type.
 395         * arc-ext.h (extInstruction_t): Change argument type.
 396         * arc-fxi.h: Change type unsigned to unsigned long long
 397         extensively throughout.
 398         * arc-nps400-tbl.h: Add long instructions taken from
 399         arc_long_opcodes table in arc-opc.c.
 400         * arc-opc.c: Update parameter types on insert/extract handlers.
 401         (arc_long_opcodes): Delete.
 402         (arc_num_long_opcodes): Delete.
 403         (arc_opcode_len): Update for more instruction lengths.
 404
 405 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 406
 407         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
 408
 409 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 410
 411         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
 412         with arc_opcode_len.
 413         (find_format_long_instructions): Likewise.
 414         * arc-opc.c (arc_opcode_len): New function.
 415
 416 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 417
 418         * arc-nps400-tbl.h: Fix some instruction masks.
 419
 420 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 421
 422         * i386-dis.c (REG_82): Removed.
 423         (X86_64_82_REG_0): Likewise.
 424         (X86_64_82_REG_1): Likewise.
 425         (X86_64_82_REG_2): Likewise.
 426         (X86_64_82_REG_3): Likewise.
 427         (X86_64_82_REG_4): Likewise.
 428         (X86_64_82_REG_5): Likewise.
 429         (X86_64_82_REG_6): Likewise.
 430         (X86_64_82_REG_7): Likewise.
 431         (X86_64_82): New.
 432         (dis386): Use X86_64_82 instead of REG_82.
 433         (reg_table): Remove REG_82.
 434         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 435         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 436         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 437         X86_64_82_REG_7.
 438
 439 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 440
 441         PR binutils/20754
 442         * i386-dis.c (REG_82): New.
 443         (X86_64_82_REG_0): Likewise.
 444         (X86_64_82_REG_1): Likewise.
 445         (X86_64_82_REG_2): Likewise.
 446         (X86_64_82_REG_3): Likewise.
 447         (X86_64_82_REG_4): Likewise.
 448         (X86_64_82_REG_5): Likewise.
 449         (X86_64_82_REG_6): Likewise.
 450         (X86_64_82_REG_7): Likewise.
 451         (dis386): Use REG_82.
 452         (reg_table): Add REG_82.
 453         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 454         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 455         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 456
 457 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 458
 459         * i386-dis.c (REG_82): Renamed to ...
 460         (REG_83): This.
 461         (dis386): Updated.
 462         (reg_table): Likewise.
 463
 464 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 465
 466         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 467         * i386-dis-evex.h (evex_table): Updated.
 468         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 469         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 470         (cpu_flags): Add CpuAVX512_4VNNIW.
 471         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 472         (i386_cpu_flags): Add cpuavx512_4vnniw.
 473         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 474         * i386-init.h: Regenerate.
 475         * i386-tbl.h: Ditto.
 476
 477 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 478
 479         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 480         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 481         * i386-dis-evex.h (evex_table): Updated.
 482         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 483         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 484         (cpu_flags): Add CpuAVX512_4FMAPS.
 485         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 486         * i386-opc.h (AVX512_4FMAP): New.
 487         (i386_cpu_flags): Add cpuavx512_4fmaps.
 488         (ImplicitQuadGroup): New.
 489         (i386_opcode_modifier): Add implicitquadgroup.
 490         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 491         * i386-init.h: Regenerate.
 492         * i386-tbl.h: Ditto.
 493
 494 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 495             Andrew Waterman <andrew@sifive.com>
 496
 497         Add support for RISC-V architecture.
 498         * configure.ac: Add entry for bfd_riscv_arch.
 499         * configure: Regenerate.
 500         * disassemble.c (disassembler): Add support for riscv.
 501         (disassembler_usage): Likewise.
 502         * riscv-dis.c: New file.
 503         * riscv-opc.c: New file.
 504
 505 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 506
 507         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 508         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 509         (rm_table): Update the RM_0FAE_REG_7 entry.
 510         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 511         (cpu_flags): Remove CpuPCOMMIT.
 512         * i386-opc.h (CpuPCOMMIT): Removed.
 513         (i386_cpu_flags): Remove cpupcommit.
 514         * i386-opc.tbl: Remove pcommit.
 515         * i386-init.h: Regenerated.
 516         * i386-tbl.h: Likewise.
 517
 518 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 519
 520         PR binutis/20705
 521         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 522         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 523         32-bit mode.  Don't check vex.register_specifier in 32-bit
 524         mode.
 525         (OP_VEX): Check for invalid mask registers.
 526
 527 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 528
 529         PR binutis/20699
 530         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 531         sizeflag.
 532
 533 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 534
 535         PR binutis/20704
 536         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 537
 538 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 539
 540         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 541         local variable to `index_regno'.
 542
 543 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 544
 545         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 546
 547 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 548
 549         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 550         usage on ISA basis.
 551
 552 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 553
 554         PR target/20666
 555         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 556
 557 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 558
 559         PR target/20667
 560         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 561         available.
 562
 563 2016-10-07  Alan Modra  <amodra@gmail.com>
 564
 565         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 566
 567 2016-10-06  Alan Modra  <amodra@gmail.com>
 568
 569         * aarch64-opc.c: Spell fall through comments consistently.
 570         * i386-dis.c: Likewise.
 571         * aarch64-dis.c: Add missing fall through comments.
 572         * aarch64-opc.c: Likewise.
 573         * arc-dis.c: Likewise.
 574         * arm-dis.c: Likewise.
 575         * i386-dis.c: Likewise.
 576         * m68k-dis.c: Likewise.
 577         * mep-asm.c: Likewise.
 578         * ns32k-dis.c: Likewise.
 579         * sh-dis.c: Likewise.
 580         * tic4x-dis.c: Likewise.
 581         * tic6x-dis.c: Likewise.
 582         * vax-dis.c: Likewise.
 583
 584 2016-10-06  Alan Modra  <amodra@gmail.com>
 585
 586         * arc-ext.c (create_map): Add missing break.
 587         * msp430-decode.opc (encode_as): Likewise.
 588         * msp430-decode.c: Regenerate.
 589
 590 2016-10-06  Alan Modra  <amodra@gmail.com>
 591
 592         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 593         * crx-dis.c (print_insn_crx): Likewise.
 594
 595 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 596
 597         PR binutils/20657
 598         * i386-dis.c (putop): Don't assign alt twice.
 599
 600 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 601
 602         PR target/20553
 603         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 604
 605 2016-09-29  Alan Modra  <amodra@gmail.com>
 606
 607         * ppc-opc.c (L): Make compulsory.
 608         (LOPT): New, optional form of L.
 609         (HTM_R): Define as LOPT.
 610         (L0, L1): Delete.
 611         (L32OPT): New, optional for 32-bit L.
 612         (L2OPT): New, 2-bit L for dcbf.
 613         (SVC_LEC): Update.
 614         (L2): Define.
 615         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 616         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 617         <dcbf>: Use L2OPT.
 618         <tlbiel, tlbie>: Use LOPT.
 619         <wclr, wclrall>: Use L2.
 620
 621 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 622
 623         * Makefile.in: Regenerate.
 624         * configure: Likewise.
 625
 626 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 627
 628         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 629         (EXTINSN2OP): Use EXTINSN2OPF.
 630         (bspeekm, bspop, modapp): New extension instructions.
 631         * arc-opc.c (F_DNZ_ND): Define.
 632         (F_DNZ_D): Likewise.
 633         (F_SIZEB1): Changed.
 634         (C_DNZ_D): Define.
 635         (C_HARD): Changed.
 636         * arc-tbl.h (dbnz): New instruction.
 637         (prealloc): Allow it for ARC EM.
 638         (xbfu): Likewise.
 639
 640 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 641
 642         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 643         after commas in addresses.
 644         (aarch64_print_operand): Likewise.
 645
 646 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 647
 648         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 649         rather than "should be" or "expected to be" in error messages.
 650
 651 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 652
 653         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 654         (print_mnemonic_name): ...here.
 655         (print_comment): New function.
 656         (print_aarch64_insn): Call it.
 657         * aarch64-opc.c (aarch64_conds): Add SVE names.
 658         (aarch64_print_operand): Print alternative condition names in
 659         a comment.
 660
 661 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 662
 663         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 664         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 665         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 666         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 667         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 668         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 669         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 670         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 671         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 672         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 673         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 674         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 675         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 676         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 677         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 678         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 679         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 680         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 681         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 682         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 683         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 684         (aarch64_feature_sve): New variable.
 685         (SVE): New macro.
 686         (_SVE_INSN): Likewise.
 687         (aarch64_opcode_table): Add SVE instructions.
 688         * aarch64-opc.h (extract_fields): Declare.
 689         * aarch64-opc-2.c: Regenerate.
 690         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 691         * aarch64-asm-2.c: Regenerate.
 692         * aarch64-dis.c (extract_fields): Make global.
 693         (do_misc_decoding): Handle the new SVE aarch64_ops.
 694         * aarch64-dis-2.c: Regenerate.
 695
 696 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 697
 698         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 699         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 700         aarch64_field_kinds.
 701         * aarch64-opc.c (fields): Add corresponding entries.
 702         * aarch64-asm.c (aarch64_get_variant): New function.
 703         (aarch64_encode_variant_using_iclass): Likewise.
 704         (aarch64_opcode_encode): Call it.
 705         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 706         (aarch64_opcode_decode): Call it.
 707
 708 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 709
 710         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 711         and FP register operands.
 712         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 713         (FLD_SVE_Vn): New aarch64_field_kinds.
 714         * aarch64-opc.c (fields): Add corresponding entries.
 715         (aarch64_print_operand): Handle the new SVE core and FP register
 716         operands.
 717         * aarch64-opc-2.c: Regenerate.
 718         * aarch64-asm-2.c: Likewise.
 719         * aarch64-dis-2.c: Likewise.
 720
 721 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 722
 723         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 724         immediate operands.
 725         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 726         * aarch64-opc.c (fields): Add corresponding entry.
 727         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 728         operands.
 729         (aarch64_print_operand): Likewise.
 730         * aarch64-opc-2.c: Regenerate.
 731         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 732         (ins_sve_float_zero_one): New inserters.
 733         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 734         (aarch64_ins_sve_float_half_two): Likewise.
 735         (aarch64_ins_sve_float_zero_one): Likewise.
 736         * aarch64-asm-2.c: Regenerate.
 737         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 738         (ext_sve_float_zero_one): New extractors.
 739         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 740         (aarch64_ext_sve_float_half_two): Likewise.
 741         (aarch64_ext_sve_float_zero_one): Likewise.
 742         * aarch64-dis-2.c: Regenerate.
 743
 744 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 745
 746         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 747         integer immediate operands.
 748         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 749         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 750         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 751         * aarch64-opc.c (fields): Add corresponding entries.
 752         (operand_general_constraint_met_p): Handle the new SVE integer
 753         immediate operands.
 754         (aarch64_print_operand): Likewise.
 755         (aarch64_sve_dupm_mov_immediate_p): New function.
 756         * aarch64-opc-2.c: Regenerate.
 757         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 758         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 759         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 760         (aarch64_ins_limm): ...here.
 761         (aarch64_ins_inv_limm): New function.
 762         (aarch64_ins_sve_aimm): Likewise.
 763         (aarch64_ins_sve_asimm): Likewise.
 764         (aarch64_ins_sve_limm_mov): Likewise.
 765         (aarch64_ins_sve_shlimm): Likewise.
 766         (aarch64_ins_sve_shrimm): Likewise.
 767         * aarch64-asm-2.c: Regenerate.
 768         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 769         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 770         * aarch64-dis.c (decode_limm): New function, split out from...
 771         (aarch64_ext_limm): ...here.
 772         (aarch64_ext_inv_limm): New function.
 773         (decode_sve_aimm): Likewise.
 774         (aarch64_ext_sve_aimm): Likewise.
 775         (aarch64_ext_sve_asimm): Likewise.
 776         (aarch64_ext_sve_limm_mov): Likewise.
 777         (aarch64_top_bit): Likewise.
 778         (aarch64_ext_sve_shlimm): Likewise.
 779         (aarch64_ext_sve_shrimm): Likewise.
 780         * aarch64-dis-2.c: Regenerate.
 781
 782 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 783
 784         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 785         operands.
 786         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 787         the AARCH64_MOD_MUL_VL entry.
 788         (value_aligned_p): Cope with non-power-of-two alignments.
 789         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 790         (print_immediate_offset_address): Likewise.
 791         (aarch64_print_operand): Likewise.
 792         * aarch64-opc-2.c: Regenerate.
 793         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 794         (ins_sve_addr_ri_s9xvl): New inserters.
 795         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 796         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 797         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 798         * aarch64-asm-2.c: Regenerate.
 799         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 800         (ext_sve_addr_ri_s9xvl): New extractors.
 801         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 802         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 803         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 804         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 805         * aarch64-dis-2.c: Regenerate.
 806
 807 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 808
 809         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 810         address operands.
 811         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 812         (FLD_SVE_xs_22): New aarch64_field_kinds.
 813         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 814         (get_operand_specific_data): New function.
 815         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 816         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 817         (operand_general_constraint_met_p): Handle the new SVE address
 818         operands.
 819         (sve_reg): New array.
 820         (get_addr_sve_reg_name): New function.
 821         (aarch64_print_operand): Handle the new SVE address operands.
 822         * aarch64-opc-2.c: Regenerate.
 823         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 824         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 825         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 826         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 827         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 828         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 829         (aarch64_ins_sve_addr_zi_u5): Likewise.
 830         (aarch64_ins_sve_addr_zz): Likewise.
 831         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 832         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 833         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 834         * aarch64-asm-2.c: Regenerate.
 835         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 836         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 837         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 838         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 839         (aarch64_ext_sve_addr_ri_u6): Likewise.
 840         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 841         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 842         (aarch64_ext_sve_addr_zi_u5): Likewise.
 843         (aarch64_ext_sve_addr_zz): Likewise.
 844         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 845         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 846         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 847         * aarch64-dis-2.c: Regenerate.
 848
 849 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 850
 851         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 852         AARCH64_OPND_SVE_PATTERN_SCALED.
 853         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 854         * aarch64-opc.c (fields): Add a corresponding entry.
 855         (set_multiplier_out_of_range_error): New function.
 856         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 857         (operand_general_constraint_met_p): Handle
 858         AARCH64_OPND_SVE_PATTERN_SCALED.
 859         (print_register_offset_address): Use PRIi64 to print the
 860         shift amount.
 861         (aarch64_print_operand): Likewise.  Handle
 862         AARCH64_OPND_SVE_PATTERN_SCALED.
 863         * aarch64-opc-2.c: Regenerate.
 864         * aarch64-asm.h (ins_sve_scale): New inserter.
 865         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 866         * aarch64-asm-2.c: Regenerate.
 867         * aarch64-dis.h (ext_sve_scale): New inserter.
 868         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 869         * aarch64-dis-2.c: Regenerate.
 870
 871 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 872
 873         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 874         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 875         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 876         (FLD_SVE_prfop): Likewise.
 877         * aarch64-opc.c: Include libiberty.h.
 878         (aarch64_sve_pattern_array): New variable.
 879         (aarch64_sve_prfop_array): Likewise.
 880         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 881         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 882         AARCH64_OPND_SVE_PRFOP.
 883         * aarch64-asm-2.c: Regenerate.
 884         * aarch64-dis-2.c: Likewise.
 885         * aarch64-opc-2.c: Likewise.
 886
 887 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 888
 889         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 890         AARCH64_OPND_QLF_P_[ZM].
 891         (aarch64_print_operand): Print /z and /m where appropriate.
 892
 893 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 894
 895         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 896         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 897         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 898         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 899         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 900         * aarch64-opc.c (fields): Add corresponding entries here.
 901         (operand_general_constraint_met_p): Check that SVE register lists
 902         have the correct length.  Check the ranges of SVE index registers.
 903         Check for cases where p8-p15 are used in 3-bit predicate fields.
 904         (aarch64_print_operand): Handle the new SVE operands.
 905         * aarch64-opc-2.c: Regenerate.
 906         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 907         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 908         (aarch64_ins_sve_reglist): Likewise.
 909         * aarch64-asm-2.c: Regenerate.
 910         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 911         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 912         (aarch64_ext_sve_reglist): Likewise.
 913         * aarch64-dis-2.c: Regenerate.
 914
 915 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 916
 917         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 918         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 919         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 920         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 921         tied operands.
 922
 923 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 924
 925         * aarch64-opc.c (get_offset_int_reg_name): New function.
 926         (print_immediate_offset_address): Likewise.
 927         (print_register_offset_address): Take the base and offset
 928         registers as parameters.
 929         (aarch64_print_operand): Update caller accordingly.  Use
 930         print_immediate_offset_address.
 931
 932 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 933
 934         * aarch64-opc.c (BANK): New macro.
 935         (R32, R64): Take a register number as argument
 936         (int_reg): Use BANK.
 937
 938 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 939
 940         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 941         (aarch64_print_operand): Update accordingly.
 942
 943 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 944
 945         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 946         for FPIMM.
 947         * aarch64-asm.h (ins_fpimm): New inserter.
 948         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 949         * aarch64-asm-2.c: Regenerate.
 950         * aarch64-dis.h (ext_fpimm): New extractor.
 951         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 952         (aarch64_ext_fpimm): New function.
 953         * aarch64-dis-2.c: Regenerate.
 954
 955 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 956
 957         * aarch64-asm.c: Include libiberty.h.
 958         (insert_fields): New function.
 959         (aarch64_ins_imm): Use it.
 960         * aarch64-dis.c (extract_fields): New function.
 961         (aarch64_ext_imm): Use it.
 962
 963 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 964
 965         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 966         with an esize parameter.
 967         (operand_general_constraint_met_p): Update accordingly.
 968         Fix misindented code.
 969         * aarch64-asm.c (aarch64_ins_limm): Update call to
 970         aarch64_logical_immediate_p.
 971
 972 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 973
 974         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 975
 976 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 977
 978         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 979
 980 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 981
 982         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 983
 984 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 985
 986         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 987         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 988         xor3>: Delete mnemonics.
 989         <cp_abort>: Rename mnemonic from ...
 990         <cpabort>: ...to this.
 991         <setb>: Change to a X form instruction.
 992         <sync>: Change to 1 operand form.
 993         <copy>: Delete mnemonic.
 994         <copy_first>: Rename mnemonic from ...
 995         <copy>: ...to this.
 996         <paste, paste.>: Delete mnemonics.
 997         <paste_last>: Rename mnemonic from ...
 998         <paste.>: ...to this.
 999
1000 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
1001
1002         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
1003
1004 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1005
1006         * s390-mkopc.c (main): Support alternate arch strings.
1007
1008 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
1009
1010         * s390-opc.txt: Fix kmctr instruction type.
1011
1012 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
1013
1014         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
1015         * i386-init.h: Regenerated.
1016
1017 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
1018
1019         * opcodes/arc-dis.c (print_insn_arc): Changed.
1020
1021 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
1022
1023         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1024         camellia_fl.
1025
1026 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1027
1028         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
1029         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1030         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1031
1032 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
1033
1034         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1035         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1036         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1037         PREFIX_MOD_3_0FAE_REG_4.
1038         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1039         PREFIX_MOD_3_0FAE_REG_4.
1040         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1041         (cpu_flags): Add CpuPTWRITE.
1042         * i386-opc.h (CpuPTWRITE): New.
1043         (i386_cpu_flags): Add cpuptwrite.
1044         * i386-opc.tbl: Add ptwrite instruction.
1045         * i386-init.h: Regenerated.
1046         * i386-tbl.h: Likewise.
1047
1048 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
1049
1050         * arc-dis.h: Wrap around in extern "C".
1051
1052 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1053
1054         * aarch64-tbl.h (V8_2_INSN): New macro.
1055         (aarch64_opcode_table): Use it.
1056
1057 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1058
1059         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1060         CORE_INSN, __FP_INSN and SIMD_INSN.
1061
1062 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1063
1064         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1065         (aarch64_opcode_table): Update uses accordingly.
1066
1067 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
1068         Kwok Cheung Yeung  <kcy@codesourcery.com>
1069
1070         opcodes/
1071         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1072         'e_cmplwi' to 'e_cmpli' instead.
1073         (OPVUPRT, OPVUPRT_MASK): Define.
1074         (powerpc_opcodes): Add E200Z4 insns.
1075         (vle_opcodes): Add context save/restore insns.
1076
1077 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
1078
1079         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1080         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1081         "j".
1082
1083 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
1084
1085         * arc-nps400-tbl.h: Change block comments to GNU format.
1086         * arc-dis.c: Add new globals addrtypenames,
1087         addrtypenames_max, and addtypeunknown.
1088         (get_addrtype): New function.
1089         (print_insn_arc): Print colons and address types when
1090         required.
1091         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1092         define insert and extract functions for all address types.
1093         (arc_operands): Add operands for colon and all address
1094         types.
1095         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1096         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1097         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1098         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1099         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1100         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1101
1102 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
1103
1104         * configure: Regenerated.
1105
1106 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
1107
1108         * arc-dis.c (skipclass): New structure.
1109         (decodelist): New variable.
1110         (is_compatible_p): New function.
1111         (new_element): Likewise.
1112         (skip_class_p): Likewise.
1113         (find_format_from_table): Use skip_class_p function.
1114         (find_format): Decode first the extension instructions.
1115         (print_insn_arc): Select either ARCEM or ARCHS based on elf
1116         e_flags.
1117         (parse_option): New function.
1118         (parse_disassembler_options): Likewise.
1119         (print_arc_disassembler_options): Likewise.
1120         (print_insn_arc): Use parse_disassembler_options function.  Proper
1121         select ARCv2 cpu variant.
1122         * disassemble.c (disassembler_usage): Add ARC disassembler
1123         options.
1124
1125 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
1126
1127         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1128         annotation from the "nal" entry and reorder it beyond "bltzal".
1129
1130 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
1131
1132         * sparc-opc.c (ldtxa): New macro.
1133         (sparc_opcodes): Use the macro defined above to add entries for
1134         the LDTXA instructions.
1135         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1136         instruction.
1137
1138 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
1139
1140         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1141         and "jmpc".
1142
1143 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1144
1145         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1146         (movzb): Adjust to cover all permitted suffixes.
1147         (movzw): New.
1148         * i386-tbl.h: Re-generate.
1149
1150 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1151
1152         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1153         (lgdt): Remove Tbyte from non-64-bit variant.
1154         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1155         xsaves64, xsavec64): Remove Disp16.
1156         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1157         Remove Disp32S from non-64-bit variants. Remove Disp16 from
1158         64-bit variants.
1159         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1160         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1161         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1162         64-bit variants.
1163         * i386-tbl.h: Re-generate.
1164
1165 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1166
1167         * i386-opc.tbl (xlat): Remove RepPrefixOk.
1168         * i386-tbl.h: Re-generate.
1169
1170 2016-06-30  Yao Qi  <yao.qi@linaro.org>
1171
1172         * arm-dis.c (print_insn): Fix typo in comment.
1173
1174 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
1175
1176         * aarch64-opc.c (operand_general_constraint_met_p): Check the
1177         range of ldst_elemlist operands.
1178         (print_register_list): Use PRIi64 to print the index.
1179         (aarch64_print_operand): Likewise.
1180
1181 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1182
1183         * mcore-opc.h: Remove sentinal.
1184         * mcore-dis.c (print_insn_mcore): Adjust.
1185
1186 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
1187
1188         * arc-opc.c: Correct description of availability of NPS400
1189         features.
1190
1191 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
1192
1193         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1194         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1195         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1196         xor3>: New mnemonics.
1197         <setb>: Change to a VX form instruction.
1198         (insert_sh6): Add support for rldixor.
1199         (extract_sh6): Likewise.
1200
1201 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1202
1203         * arc-ext.h: Wrap in extern C.
1204
1205 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
1206
1207         * arc-dis.c (arc_insn_length): Add comment on instruction length.
1208         Use same method for determining instruction length on ARC700 and
1209         NPS-400.
1210         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1211         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1212         with the NPS400 subclass.
1213         * arc-opc.c: Likewise.
1214
1215 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1216
1217         * sparc-opc.c (rdasr): New macro.
1218         (wrasr): Likewise.
1219         (rdpr): Likewise.
1220         (wrpr): Likewise.
1221         (rdhpr): Likewise.
1222         (wrhpr): Likewise.
1223         (sparc_opcodes): Use the macros above to fix and expand the
1224         definition of read/write instructions from/to
1225         asr/privileged/hyperprivileged instructions.
1226         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1227         %hva_mask_nz.  Prefer softint_set and softint_clear over
1228         set_softint and clear_softint.
1229         (print_insn_sparc): Support %ver in Rd.
1230
1231 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1232
1233         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1234         architecture according to the hardware capabilities they require.
1235
1236 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1237
1238         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1239         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1240         bfd_mach_sparc_v9{c,d,e,v,m}.
1241         * sparc-opc.c (MASK_V9C): Define.
1242         (MASK_V9D): Likewise.
1243         (MASK_V9E): Likewise.
1244         (MASK_V9V): Likewise.
1245         (MASK_V9M): Likewise.
1246         (v6): Add MASK_V9{C,D,E,V,M}.
1247         (v6notlet): Likewise.
1248         (v7): Likewise.
1249         (v8): Likewise.
1250         (v9): Likewise.
1251         (v9andleon): Likewise.
1252         (v9a): Likewise.
1253         (v9b): Likewise.
1254         (v9c): Define.
1255         (v9d): Likewise.
1256         (v9e): Likewise.
1257         (v9v): Likewise.
1258         (v9m): Likewise.
1259         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1260
1261 2016-06-15  Nick Clifton  <nickc@redhat.com>
1262
1263         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1264         constants to match expected behaviour.
1265         (nds32_parse_opcode): Likewise.  Also for whitespace.
1266
1267 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
1268
1269         * arc-opc.c (extract_rhv1): Extract value from insn.
1270
1271 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1272
1273         * arc-nps400-tbl.h: Add ldbit instruction.
1274         * arc-opc.c: Add flag classes required for ldbit.
1275
1276 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1277
1278         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1279         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1280         support the above instructions.
1281
1282 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1283
1284         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1285         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1286         csma, cbba, zncv, and hofs.
1287         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1288         support the above instructions.
1289
1290 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1291
1292         * arc-nps400-tbl.h: Add andab and orab instructions.
1293
1294 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1295
1296         * arc-nps400-tbl.h: Add addl-like instructions.
1297
1298 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1299
1300         * arc-nps400-tbl.h: Add mxb and imxb instructions.
1301
1302 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1303
1304         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1305         instructions.
1306
1307 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1308
1309         * s390-dis.c (option_use_insn_len_bits_p): New file scope
1310         variable.
1311         (init_disasm): Handle new command line option "insnlength".
1312         (print_s390_disassembler_options): Mention new option in help
1313         output.
1314         (print_insn_s390): Use the encoded insn length when dumping
1315         unknown instructions.
1316
1317 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1318
1319         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1320          to the address and set as symbol address for LDS/ STS immediate operands.
1321
1322 2016-06-07  Alan Modra  <amodra@gmail.com>
1323
1324         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1325         cpu for "vle" to e500.
1326         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1327         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1328         (PPCNONE): Delete, substitute throughout.
1329         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1330         except for major opcode 4 and 31.
1331         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1332
1333 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1334
1335         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1336         ARM_EXT_RAS in relevant entries.
1337
1338 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1339
1340         PR binutils/20196
1341         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1342         opcodes for E6500.
1343
1344 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1345
1346         PR binutis/18386
1347         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1348         (indir_v_mode): New.
1349         Add comments for '&'.
1350         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1351         (putop): Handle '&'.
1352         (intel_operand_size): Handle indir_v_mode.
1353         (OP_E_register): Likewise.
1354         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1355         64-bit indirect call/jmp for AMD64.
1356         * i386-tbl.h: Regenerated
1357
1358 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1359
1360         * arc-dis.c (struct arc_operand_iterator): New structure.
1361         (find_format_from_table): All the old content from find_format,
1362         with some minor adjustments, and parameter renaming.
1363         (find_format_long_instructions): New function.
1364         (find_format): Rewritten.
1365         (arc_insn_length): Add LSB parameter.
1366         (extract_operand_value): New function.
1367         (operand_iterator_next): New function.
1368         (print_insn_arc): Use new functions to find opcode, and iterator
1369         over operands.
1370         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1371         (extract_nps_3bit_dst_short): New function.
1372         (insert_nps_3bit_src2_short): New function.
1373         (extract_nps_3bit_src2_short): New function.
1374         (insert_nps_bitop1_size): New function.
1375         (extract_nps_bitop1_size): New function.
1376         (insert_nps_bitop2_size): New function.
1377         (extract_nps_bitop2_size): New function.
1378         (insert_nps_bitop_mod4_msb): New function.
1379         (extract_nps_bitop_mod4_msb): New function.
1380         (insert_nps_bitop_mod4_lsb): New function.
1381         (extract_nps_bitop_mod4_lsb): New function.
1382         (insert_nps_bitop_dst_pos3_pos4): New function.
1383         (extract_nps_bitop_dst_pos3_pos4): New function.
1384         (insert_nps_bitop_ins_ext): New function.
1385         (extract_nps_bitop_ins_ext): New function.
1386         (arc_operands): Add new operands.
1387         (arc_long_opcodes): New global array.
1388         (arc_num_long_opcodes): New global.
1389         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1390
1391 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1392
1393         * nds32-asm.h: Add extern "C".
1394         * sh-opc.h: Likewise.
1395
1396 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1397
1398         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1399         0,b,limm to the rflt instruction.
1400
1401 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1402
1403         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1404         constant.
1405
1406 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1407
1408         PR gas/20145
1409         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1410         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1411         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1412         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1413         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1414         * i386-init.h: Regenerated.
1415
1416 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1417
1418         PR gas/20145
1419         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1420         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1421         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1422         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1423         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1424         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1425         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1426         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1427         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1428         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1429         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1430         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1431         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1432         CpuRegMask for AVX512.
1433         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1434         and CpuRegMask.
1435         (set_bitfield_from_cpu_flag_init): New function.
1436         (set_bitfield): Remove const on f.  Call
1437         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1438         * i386-opc.h (CpuRegMMX): New.
1439         (CpuRegXMM): Likewise.
1440         (CpuRegYMM): Likewise.
1441         (CpuRegZMM): Likewise.
1442         (CpuRegMask): Likewise.
1443         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1444         and cpuregmask.
1445         * i386-init.h: Regenerated.
1446         * i386-tbl.h: Likewise.
1447
1448 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1449
1450         PR gas/20154
1451         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1452         (opcode_modifiers): Add AMD64 and Intel64.
1453         (main): Properly verify CpuMax.
1454         * i386-opc.h (CpuAMD64): Removed.
1455         (CpuIntel64): Likewise.
1456         (CpuMax): Set to CpuNo64.
1457         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1458         (AMD64): New.
1459         (Intel64): Likewise.
1460         (i386_opcode_modifier): Add amd64 and intel64.
1461         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1462         on call and jmp.
1463         * i386-init.h: Regenerated.
1464         * i386-tbl.h: Likewise.
1465
1466 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1467
1468         PR gas/20154
1469         * i386-gen.c (main): Fail if CpuMax is incorrect.
1470         * i386-opc.h (CpuMax): Set to CpuIntel64.
1471         * i386-tbl.h: Regenerated.
1472
1473 2016-05-27  Nick Clifton  <nickc@redhat.com>
1474
1475         PR target/20150
1476         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1477         (msp430dis_opcode_unsigned): New function.
1478         (msp430dis_opcode_signed): New function.
1479         (msp430_singleoperand): Use the new opcode reading functions.
1480         Only disassenmble bytes if they were successfully read.
1481         (msp430_doubleoperand): Likewise.
1482         (msp430_branchinstr): Likewise.
1483         (msp430x_callx_instr): Likewise.
1484         (print_insn_msp430): Check that it is safe to read bytes before
1485         attempting disassembly.  Use the new opcode reading functions.
1486
1487 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1488
1489         * ppc-opc.c (CY): New define.  Document it.
1490         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1491
1492 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1493
1494         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1495         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1496         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1497         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1498         CPU_ANY_AVX_FLAGS.
1499         * i386-init.h: Regenerated.
1500
1501 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1502
1503         PR gas/20141
1504         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1505         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1506         * i386-init.h: Regenerated.
1507
1508 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1509
1510         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1511         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1512         * i386-init.h: Regenerated.
1513
1514 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1515
1516         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1517         information.
1518         (print_insn_arc): Set insn_type information.
1519         * arc-opc.c (C_CC): Add F_CLASS_COND.
1520         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1521         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1522         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1523         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1524         (brne, brne_s, jeq_s, jne_s): Likewise.
1525
1526 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1527
1528         * arc-tbl.h (neg): New instruction variant.
1529
1530 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1531
1532         * arc-dis.c (find_format, find_format, get_auxreg)
1533         (print_insn_arc): Changed.
1534         * arc-ext.h (INSERT_XOP): Likewise.
1535
1536 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1537
1538         * tic54x-dis.c (sprint_mmr): Adjust.
1539         * tic54x-opc.c: Likewise.
1540
1541 2016-05-19  Alan Modra  <amodra@gmail.com>
1542
1543         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1544
1545 2016-05-19  Alan Modra  <amodra@gmail.com>
1546
1547         * ppc-opc.c: Formatting.
1548         (NSISIGNOPT): Define.
1549         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1550
1551 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1552
1553         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1554         replacing references to `micromips_ase' throughout.
1555         (_print_insn_mips): Don't use file-level microMIPS annotation to
1556         determine the disassembly mode with the symbol table.
1557
1558 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1559
1560         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1561
1562 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1563
1564         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1565         mips64r6.
1566         * mips-opc.c (D34): New macro.
1567         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1568
1569 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1570
1571         * i386-dis.c (prefix_table): Add RDPID instruction.
1572         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1573         (cpu_flags): Add RDPID bitfield.
1574         * i386-opc.h (enum): Add RDPID element.
1575         (i386_cpu_flags): Add RDPID field.
1576         * i386-opc.tbl: Add RDPID instruction.
1577         * i386-init.h: Regenerate.
1578         * i386-tbl.h: Regenerate.
1579
1580 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1581
1582         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1583         branch type of a symbol.
1584         (print_insn): Likewise.
1585
1586 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1587
1588         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1589         Mainline Security Extensions instructions.
1590         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1591         Extensions instructions.
1592         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1593         instructions.
1594         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1595         special registers.
1596
1597 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1598
1599         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1600
1601 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1602
1603         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1604         (arcExtMap_genOpcode): Likewise.
1605         * arc-opc.c (arg_32bit_rc): Define new variable.
1606         (arg_32bit_u6): Likewise.
1607         (arg_32bit_limm): Likewise.
1608
1609 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1610
1611         * aarch64-gen.c (VERIFIER): Define.
1612         * aarch64-opc.c (VERIFIER): Define.
1613         (verify_ldpsw): Use static linkage.
1614         * aarch64-opc.h (verify_ldpsw): Remove.
1615         * aarch64-tbl.h: Use VERIFIER for verifiers.
1616
1617 2016-04-28  Nick Clifton  <nickc@redhat.com>
1618
1619         PR target/19722
1620         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1621         * aarch64-opc.c (verify_ldpsw): New function.
1622         * aarch64-opc.h (verify_ldpsw): New prototype.
1623         * aarch64-tbl.h: Add initialiser for verifier field.
1624         (LDPSW): Set verifier to verify_ldpsw.
1625
1626 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1627
1628         PR binutils/19983
1629         PR binutils/19984
1630         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1631         smaller than address size.
1632
1633 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1634
1635         * alpha-dis.c: Regenerate.
1636         * crx-dis.c: Likewise.
1637         * disassemble.c: Likewise.
1638         * epiphany-opc.c: Likewise.
1639         * fr30-opc.c: Likewise.
1640         * frv-opc.c: Likewise.
1641         * ip2k-opc.c: Likewise.
1642         * iq2000-opc.c: Likewise.
1643         * lm32-opc.c: Likewise.
1644         * lm32-opinst.c: Likewise.
1645         * m32c-opc.c: Likewise.
1646         * m32r-opc.c: Likewise.
1647         * m32r-opinst.c: Likewise.
1648         * mep-opc.c: Likewise.
1649         * mt-opc.c: Likewise.
1650         * or1k-opc.c: Likewise.
1651         * or1k-opinst.c: Likewise.
1652         * tic80-opc.c: Likewise.
1653         * xc16x-opc.c: Likewise.
1654         * xstormy16-opc.c: Likewise.
1655
1656 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1657
1658         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1659         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1660         calcsd, and calcxd instructions.
1661         * arc-opc.c (insert_nps_bitop_size): Delete.
1662         (extract_nps_bitop_size): Delete.
1663         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1664         (extract_nps_qcmp_m3): Define.
1665         (extract_nps_qcmp_m2): Define.
1666         (extract_nps_qcmp_m1): Define.
1667         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1668         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1669         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1670         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1671         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1672         NPS_QCMP_M3.
1673
1674 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1675
1676         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1677
1678 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1679
1680         * Makefile.in: Regenerated with automake 1.11.6.
1681         * aclocal.m4: Likewise.
1682
1683 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1684
1685         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1686         instructions.
1687         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1688         (extract_nps_cmem_uimm16): New function.
1689         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1690
1691 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1692
1693         * arc-dis.c (arc_insn_length): New function.
1694         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1695         (find_format): Change insnLen parameter to unsigned.
1696
1697 2016-04-13  Nick Clifton  <nickc@redhat.com>
1698
1699         PR target/19937
1700         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1701         the LD.B and LD.BU instructions.
1702
1703 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1704
1705         * arc-dis.c (find_format): Check for extension flags.
1706         (print_flags): New function.
1707         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1708         .extAuxRegister.
1709         * arc-ext.c (arcExtMap_coreRegName): Use
1710         LAST_EXTENSION_CORE_REGISTER.
1711         (arcExtMap_coreReadWrite): Likewise.
1712         (dump_ARC_extmap): Update printing.
1713         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1714         (arc_aux_regs): Add cpu field.
1715         * arc-regs.h: Add cpu field, lower case name aux registers.
1716
1717 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1718
1719         * arc-tbl.h: Add rtsc, sleep with no arguments.
1720
1721 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1722
1723         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1724         Initialize.
1725         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1726         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1727         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1728         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1729         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1730         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1731         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1732         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1733         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1734         (arc_opcode arc_opcodes): Null terminate the array.
1735         (arc_num_opcodes): Remove.
1736         * arc-ext.h (INSERT_XOP): Define.
1737         (extInstruction_t): Likewise.
1738         (arcExtMap_instName): Delete.
1739         (arcExtMap_insn): New function.
1740         (arcExtMap_genOpcode): Likewise.
1741         * arc-ext.c (ExtInstruction): Remove.
1742         (create_map): Zero initialize instruction fields.
1743         (arcExtMap_instName): Remove.
1744         (arcExtMap_insn): New function.
1745         (dump_ARC_extmap): More info while debuging.
1746         (arcExtMap_genOpcode): New function.
1747         * arc-dis.c (find_format): New function.
1748         (print_insn_arc): Use find_format.
1749         (arc_get_disassembler): Enable dump_ARC_extmap only when
1750         debugging.
1751
1752 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1753
1754         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1755         instruction bits out.
1756
1757 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1758
1759         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1760         * arc-opc.c (arc_flag_operands): Add new flags.
1761         (arc_flag_classes): Add new classes.
1762
1763 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1764
1765         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1766
1767 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1768
1769         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1770         encode1, rflt, crc16, and crc32 instructions.
1771         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1772         (arc_flag_classes): Add C_NPS_R.
1773         (insert_nps_bitop_size_2b): New function.
1774         (extract_nps_bitop_size_2b): Likewise.
1775         (insert_nps_bitop_uimm8): Likewise.
1776         (extract_nps_bitop_uimm8): Likewise.
1777         (arc_operands): Add new operand entries.
1778
1779 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1780
1781         * arc-regs.h: Add a new subclass field.  Add double assist
1782         accumulator register values.
1783         * arc-tbl.h: Use DPA subclass to mark the double assist
1784         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1785         * arc-opc.c (RSP): Define instead of SP.
1786         (arc_aux_regs): Add the subclass field.
1787
1788 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1789
1790         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1791
1792 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1793
1794         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1795         NPS_R_SRC1.
1796
1797 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1798
1799         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1800         issues.  No functional changes.
1801
1802 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1803
1804         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1805         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1806         (RTT): Remove duplicate.
1807         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1808         (PCT_CONFIG*): Remove.
1809         (D1L, D1H, D2H, D2L): Define.
1810
1811 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1812
1813         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1814
1815 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1816
1817         * arc-tbl.h (invld07): Remove.
1818         * arc-ext-tbl.h: New file.
1819         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1820         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1821
1822 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1823
1824         Fix -Wstack-usage warnings.
1825         * aarch64-dis.c (print_operands): Substitute size.
1826         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1827
1828 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1829
1830         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1831         to get a proper diagnostic when an invalid ASR register is used.
1832
1833 2016-03-22  Nick Clifton  <nickc@redhat.com>
1834
1835         * configure: Regenerate.
1836
1837 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1838
1839         * arc-nps400-tbl.h: New file.
1840         * arc-opc.c: Add top level comment.
1841         (insert_nps_3bit_dst): New function.
1842         (extract_nps_3bit_dst): New function.
1843         (insert_nps_3bit_src2): New function.
1844         (extract_nps_3bit_src2): New function.
1845         (insert_nps_bitop_size): New function.
1846         (extract_nps_bitop_size): New function.
1847         (arc_flag_operands): Add nps400 entries.
1848         (arc_flag_classes): Add nps400 entries.
1849         (arc_operands): Add nps400 entries.
1850         (arc_opcodes): Add nps400 include.
1851
1852 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1853
1854         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1855         the new class enum values.
1856
1857 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1858
1859         * arc-dis.c (print_insn_arc): Handle nps400.
1860
1861 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1862
1863         * arc-opc.c (BASE): Delete.
1864
1865 2016-03-18  Nick Clifton  <nickc@redhat.com>
1866
1867         PR target/19721
1868         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1869         of MOV insn that aliases an ORR insn.
1870
1871 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1872
1873         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1874
1875 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1876
1877         * mcore-opc.h: Add const qualifiers.
1878         * microblaze-opc.h (struct op_code_struct): Likewise.
1879         * sh-opc.h: Likewise.
1880         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1881         (tic4x_print_op): Likewise.
1882
1883 2016-03-02  Alan Modra  <amodra@gmail.com>
1884
1885         * or1k-desc.h: Regenerate.
1886         * fr30-ibld.c: Regenerate.
1887         * rl78-decode.c: Regenerate.
1888
1889 2016-03-01  Nick Clifton  <nickc@redhat.com>
1890
1891         PR target/19747
1892         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1893
1894 2016-02-24  Renlin Li  <renlin.li@arm.com>
1895
1896         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1897         (print_insn_coprocessor): Support fp16 instructions.
1898
1899 2016-02-24  Renlin Li  <renlin.li@arm.com>
1900
1901         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1902         vminnm, vrint(mpna).
1903
1904 2016-02-24  Renlin Li  <renlin.li@arm.com>
1905
1906         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1907         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1908
1909 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1910
1911         * i386-dis.c (print_insn): Parenthesize expression to prevent
1912         truncated addresses.
1913         (OP_J): Likewise.
1914
1915 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1916             Janek van Oirschot  <jvanoirs@synopsys.com>
1917
1918         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1919         variable.
1920
1921 2016-02-04  Nick Clifton  <nickc@redhat.com>
1922
1923         PR target/19561
1924         * msp430-dis.c (print_insn_msp430): Add a special case for
1925         decoding an RRC instruction with the ZC bit set in the extension
1926         word.
1927
1928 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1929
1930         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1931         * epiphany-ibld.c: Regenerate.
1932         * fr30-ibld.c: Regenerate.
1933         * frv-ibld.c: Regenerate.
1934         * ip2k-ibld.c: Regenerate.
1935         * iq2000-ibld.c: Regenerate.
1936         * lm32-ibld.c: Regenerate.
1937         * m32c-ibld.c: Regenerate.
1938         * m32r-ibld.c: Regenerate.
1939         * mep-ibld.c: Regenerate.
1940         * mt-ibld.c: Regenerate.
1941         * or1k-ibld.c: Regenerate.
1942         * xc16x-ibld.c: Regenerate.
1943         * xstormy16-ibld.c: Regenerate.
1944
1945 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1946
1947         * epiphany-dis.c: Regenerated from latest cpu files.
1948
1949 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1950
1951         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1952         test bit.
1953
1954 2016-01-25  Renlin Li  <renlin.li@arm.com>
1955
1956         * arm-dis.c (mapping_symbol_for_insn): New function.
1957         (find_ifthen_state): Call mapping_symbol_for_insn().
1958
1959 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1960
1961         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1962         of MSR UAO immediate operand.
1963
1964 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1965
1966         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1967         instruction support.
1968
1969 2016-01-17  Alan Modra  <amodra@gmail.com>
1970
1971         * configure: Regenerate.
1972
1973 2016-01-14  Nick Clifton  <nickc@redhat.com>
1974
1975         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1976         instructions that can support stack pointer operations.
1977         * rl78-decode.c: Regenerate.
1978         * rl78-dis.c: Fix display of stack pointer in MOVW based
1979         instructions.
1980
1981 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1982
1983         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1984         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1985         erxtatus_el1 and erxaddr_el1.
1986
1987 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1988
1989         * arm-dis.c (arm_opcodes): Add "esb".
1990         (thumb_opcodes): Likewise.
1991
1992 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1993
1994         * ppc-opc.c <xscmpnedp>: Delete.
1995         <xvcmpnedp>: Likewise.
1996         <xvcmpnedp.>: Likewise.
1997         <xvcmpnesp>: Likewise.
1998         <xvcmpnesp.>: Likewise.
1999
2000 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
2001
2002         PR gas/13050
2003         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
2004         addition to ISA_A.
2005
2006 2016-01-01  Alan Modra  <amodra@gmail.com>
2007
2008         Update year range in copyright notice of all files.
2009
2010 For older changes see ChangeLog-2015
2011 \f
2012 Copyright (C) 2016 Free Software Foundation, Inc.
2013
2014 Copying and distribution of this file, with or without modification,
2015 are permitted in any medium without royalty provided the copyright
2016 notice and this notice are preserved.
2017
2018 Local Variables:
2019 mode: change-log
2020 left-margin: 8
2021 fill-column: 74
2022 version-control: never
2023 End: