1 2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
4 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
5 (FGRPd9_4): Replace 1 with 2.
6 (FGRPd9_5): Replace 2 with 3.
7 (FGRPd9_6): Replace 3 with 4.
8 (FGRPd9_7): Replace 4 with 5.
9 (FGRPda_5): Replace 5 with 6.
10 (FGRPdb_4): Replace 6 with 7.
11 (FGRPde_3): Replace 7 with 8.
12 (FGRPdf_4): Replace 8 with 9.
13 (fgrps): Add an entry for Bad_Opcode.
15 2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
17 * arc-opc.c (arc_flag_operands): Add F_DI14.
18 (arc_flag_classes): Add C_DI14.
19 * arc-nps400-tbl.h: Add new exc instructions.
21 2016-11-03 Graham Markall <graham.markall@embecosm.com>
23 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
25 * arc-nps-400-tbl.h: Add dcmac instruction.
26 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
27 (insert_nps_rbdouble_64): Added.
28 (extract_nps_rbdouble_64): Added.
29 (insert_nps_proto_size): Added.
30 (extract_nps_proto_size): Added.
32 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
34 * arc-dis.c (struct arc_operand_iterator): Remove all fields
35 relating to long instruction processing, add new limm field.
36 (OPCODE): Rename to...
37 (OPCODE_32BIT_INSN): ...this.
39 (skip_this_opcode): Handle different instruction lengths, update
41 (special_flag_p): Update parameter type.
42 (find_format_from_table): Update for more instruction lengths.
43 (find_format_long_instructions): Delete.
44 (find_format): Update for more instruction lengths.
45 (arc_insn_length): Likewise.
46 (extract_operand_value): Update for more instruction lengths.
47 (operand_iterator_next): Remove code relating to long
49 (arc_opcode_to_insn_type): New function.
50 (print_insn_arc):Update for more instructions lengths.
51 * arc-ext.c (extInstruction_t): Change argument type.
52 * arc-ext.h (extInstruction_t): Change argument type.
53 * arc-fxi.h: Change type unsigned to unsigned long long
54 extensively throughout.
55 * arc-nps400-tbl.h: Add long instructions taken from
56 arc_long_opcodes table in arc-opc.c.
57 * arc-opc.c: Update parameter types on insert/extract handlers.
58 (arc_long_opcodes): Delete.
59 (arc_num_long_opcodes): Delete.
60 (arc_opcode_len): Update for more instruction lengths.
62 2016-11-03 Graham Markall <graham.markall@embecosm.com>
64 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
66 2016-11-03 Graham Markall <graham.markall@embecosm.com>
68 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
70 (find_format_long_instructions): Likewise.
71 * arc-opc.c (arc_opcode_len): New function.
73 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
75 * arc-nps400-tbl.h: Fix some instruction masks.
77 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
79 * i386-dis.c (REG_82): Removed.
80 (X86_64_82_REG_0): Likewise.
81 (X86_64_82_REG_1): Likewise.
82 (X86_64_82_REG_2): Likewise.
83 (X86_64_82_REG_3): Likewise.
84 (X86_64_82_REG_4): Likewise.
85 (X86_64_82_REG_5): Likewise.
86 (X86_64_82_REG_6): Likewise.
87 (X86_64_82_REG_7): Likewise.
89 (dis386): Use X86_64_82 instead of REG_82.
90 (reg_table): Remove REG_82.
91 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
92 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
93 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
96 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
99 * i386-dis.c (REG_82): New.
100 (X86_64_82_REG_0): Likewise.
101 (X86_64_82_REG_1): Likewise.
102 (X86_64_82_REG_2): Likewise.
103 (X86_64_82_REG_3): Likewise.
104 (X86_64_82_REG_4): Likewise.
105 (X86_64_82_REG_5): Likewise.
106 (X86_64_82_REG_6): Likewise.
107 (X86_64_82_REG_7): Likewise.
108 (dis386): Use REG_82.
109 (reg_table): Add REG_82.
110 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
111 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
112 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
114 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
116 * i386-dis.c (REG_82): Renamed to ...
119 (reg_table): Likewise.
121 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
123 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
124 * i386-dis-evex.h (evex_table): Updated.
125 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
126 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
127 (cpu_flags): Add CpuAVX512_4VNNIW.
128 * i386-opc.h (enum): (AVX512_4VNNIW): New.
129 (i386_cpu_flags): Add cpuavx512_4vnniw.
130 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
131 * i386-init.h: Regenerate.
134 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
136 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
137 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
138 * i386-dis-evex.h (evex_table): Updated.
139 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
140 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
141 (cpu_flags): Add CpuAVX512_4FMAPS.
142 (opcode_modifiers): Add ImplicitQuadGroup modifier.
143 * i386-opc.h (AVX512_4FMAP): New.
144 (i386_cpu_flags): Add cpuavx512_4fmaps.
145 (ImplicitQuadGroup): New.
146 (i386_opcode_modifier): Add implicitquadgroup.
147 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
148 * i386-init.h: Regenerate.
151 2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
152 Andrew Waterman <andrew@sifive.com>
154 Add support for RISC-V architecture.
155 * configure.ac: Add entry for bfd_riscv_arch.
156 * configure: Regenerate.
157 * disassemble.c (disassembler): Add support for riscv.
158 (disassembler_usage): Likewise.
159 * riscv-dis.c: New file.
160 * riscv-opc.c: New file.
162 2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
164 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
165 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
166 (rm_table): Update the RM_0FAE_REG_7 entry.
167 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
168 (cpu_flags): Remove CpuPCOMMIT.
169 * i386-opc.h (CpuPCOMMIT): Removed.
170 (i386_cpu_flags): Remove cpupcommit.
171 * i386-opc.tbl: Remove pcommit.
172 * i386-init.h: Regenerated.
173 * i386-tbl.h: Likewise.
175 2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
178 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
179 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
180 32-bit mode. Don't check vex.register_specifier in 32-bit
182 (OP_VEX): Check for invalid mask registers.
184 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
187 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
190 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
193 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
195 2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
197 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
198 local variable to `index_regno'.
200 2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
202 * arc-tbl.h: Removed any "inv.+" instructions from the table.
204 2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
206 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
209 2016-10-11 Jiong Wang <jiong.wang@arm.com>
212 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
214 2016-10-07 Jiong Wang <jiong.wang@arm.com>
217 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
220 2016-10-07 Alan Modra <amodra@gmail.com>
222 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
224 2016-10-06 Alan Modra <amodra@gmail.com>
226 * aarch64-opc.c: Spell fall through comments consistently.
227 * i386-dis.c: Likewise.
228 * aarch64-dis.c: Add missing fall through comments.
229 * aarch64-opc.c: Likewise.
230 * arc-dis.c: Likewise.
231 * arm-dis.c: Likewise.
232 * i386-dis.c: Likewise.
233 * m68k-dis.c: Likewise.
234 * mep-asm.c: Likewise.
235 * ns32k-dis.c: Likewise.
236 * sh-dis.c: Likewise.
237 * tic4x-dis.c: Likewise.
238 * tic6x-dis.c: Likewise.
239 * vax-dis.c: Likewise.
241 2016-10-06 Alan Modra <amodra@gmail.com>
243 * arc-ext.c (create_map): Add missing break.
244 * msp430-decode.opc (encode_as): Likewise.
245 * msp430-decode.c: Regenerate.
247 2016-10-06 Alan Modra <amodra@gmail.com>
249 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
250 * crx-dis.c (print_insn_crx): Likewise.
252 2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
255 * i386-dis.c (putop): Don't assign alt twice.
257 2016-09-29 Jiong Wang <jiong.wang@arm.com>
260 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
262 2016-09-29 Alan Modra <amodra@gmail.com>
264 * ppc-opc.c (L): Make compulsory.
265 (LOPT): New, optional form of L.
266 (HTM_R): Define as LOPT.
268 (L32OPT): New, optional for 32-bit L.
269 (L2OPT): New, 2-bit L for dcbf.
272 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
273 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
275 <tlbiel, tlbie>: Use LOPT.
276 <wclr, wclrall>: Use L2.
278 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
280 * Makefile.in: Regenerate.
281 * configure: Likewise.
283 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
285 * arc-ext-tbl.h (EXTINSN2OPF): Define.
286 (EXTINSN2OP): Use EXTINSN2OPF.
287 (bspeekm, bspop, modapp): New extension instructions.
288 * arc-opc.c (F_DNZ_ND): Define.
293 * arc-tbl.h (dbnz): New instruction.
294 (prealloc): Allow it for ARC EM.
297 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
299 * aarch64-opc.c (print_immediate_offset_address): Print spaces
300 after commas in addresses.
301 (aarch64_print_operand): Likewise.
303 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
305 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
306 rather than "should be" or "expected to be" in error messages.
308 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
310 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
311 (print_mnemonic_name): ...here.
312 (print_comment): New function.
313 (print_aarch64_insn): Call it.
314 * aarch64-opc.c (aarch64_conds): Add SVE names.
315 (aarch64_print_operand): Print alternative condition names in
318 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
320 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
321 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
322 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
323 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
324 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
325 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
326 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
327 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
328 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
329 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
330 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
331 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
332 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
333 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
334 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
335 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
336 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
337 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
338 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
339 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
340 (OP_SVE_XWU, OP_SVE_XXU): New macros.
341 (aarch64_feature_sve): New variable.
343 (_SVE_INSN): Likewise.
344 (aarch64_opcode_table): Add SVE instructions.
345 * aarch64-opc.h (extract_fields): Declare.
346 * aarch64-opc-2.c: Regenerate.
347 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
348 * aarch64-asm-2.c: Regenerate.
349 * aarch64-dis.c (extract_fields): Make global.
350 (do_misc_decoding): Handle the new SVE aarch64_ops.
351 * aarch64-dis-2.c: Regenerate.
353 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
355 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
356 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
358 * aarch64-opc.c (fields): Add corresponding entries.
359 * aarch64-asm.c (aarch64_get_variant): New function.
360 (aarch64_encode_variant_using_iclass): Likewise.
361 (aarch64_opcode_encode): Call it.
362 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
363 (aarch64_opcode_decode): Call it.
365 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
367 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
368 and FP register operands.
369 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
370 (FLD_SVE_Vn): New aarch64_field_kinds.
371 * aarch64-opc.c (fields): Add corresponding entries.
372 (aarch64_print_operand): Handle the new SVE core and FP register
374 * aarch64-opc-2.c: Regenerate.
375 * aarch64-asm-2.c: Likewise.
376 * aarch64-dis-2.c: Likewise.
378 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
380 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
382 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
383 * aarch64-opc.c (fields): Add corresponding entry.
384 (operand_general_constraint_met_p): Handle the new SVE FP immediate
386 (aarch64_print_operand): Likewise.
387 * aarch64-opc-2.c: Regenerate.
388 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
389 (ins_sve_float_zero_one): New inserters.
390 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
391 (aarch64_ins_sve_float_half_two): Likewise.
392 (aarch64_ins_sve_float_zero_one): Likewise.
393 * aarch64-asm-2.c: Regenerate.
394 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
395 (ext_sve_float_zero_one): New extractors.
396 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
397 (aarch64_ext_sve_float_half_two): Likewise.
398 (aarch64_ext_sve_float_zero_one): Likewise.
399 * aarch64-dis-2.c: Regenerate.
401 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
403 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
404 integer immediate operands.
405 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
406 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
407 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
408 * aarch64-opc.c (fields): Add corresponding entries.
409 (operand_general_constraint_met_p): Handle the new SVE integer
411 (aarch64_print_operand): Likewise.
412 (aarch64_sve_dupm_mov_immediate_p): New function.
413 * aarch64-opc-2.c: Regenerate.
414 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
415 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
416 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
417 (aarch64_ins_limm): ...here.
418 (aarch64_ins_inv_limm): New function.
419 (aarch64_ins_sve_aimm): Likewise.
420 (aarch64_ins_sve_asimm): Likewise.
421 (aarch64_ins_sve_limm_mov): Likewise.
422 (aarch64_ins_sve_shlimm): Likewise.
423 (aarch64_ins_sve_shrimm): Likewise.
424 * aarch64-asm-2.c: Regenerate.
425 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
426 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
427 * aarch64-dis.c (decode_limm): New function, split out from...
428 (aarch64_ext_limm): ...here.
429 (aarch64_ext_inv_limm): New function.
430 (decode_sve_aimm): Likewise.
431 (aarch64_ext_sve_aimm): Likewise.
432 (aarch64_ext_sve_asimm): Likewise.
433 (aarch64_ext_sve_limm_mov): Likewise.
434 (aarch64_top_bit): Likewise.
435 (aarch64_ext_sve_shlimm): Likewise.
436 (aarch64_ext_sve_shrimm): Likewise.
437 * aarch64-dis-2.c: Regenerate.
439 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
441 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
443 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
444 the AARCH64_MOD_MUL_VL entry.
445 (value_aligned_p): Cope with non-power-of-two alignments.
446 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
447 (print_immediate_offset_address): Likewise.
448 (aarch64_print_operand): Likewise.
449 * aarch64-opc-2.c: Regenerate.
450 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
451 (ins_sve_addr_ri_s9xvl): New inserters.
452 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
453 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
454 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
455 * aarch64-asm-2.c: Regenerate.
456 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
457 (ext_sve_addr_ri_s9xvl): New extractors.
458 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
459 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
460 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
461 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
462 * aarch64-dis-2.c: Regenerate.
464 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
466 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
468 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
469 (FLD_SVE_xs_22): New aarch64_field_kinds.
470 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
471 (get_operand_specific_data): New function.
472 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
473 FLD_SVE_xs_14 and FLD_SVE_xs_22.
474 (operand_general_constraint_met_p): Handle the new SVE address
476 (sve_reg): New array.
477 (get_addr_sve_reg_name): New function.
478 (aarch64_print_operand): Handle the new SVE address operands.
479 * aarch64-opc-2.c: Regenerate.
480 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
481 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
482 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
483 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
484 (aarch64_ins_sve_addr_rr_lsl): Likewise.
485 (aarch64_ins_sve_addr_rz_xtw): Likewise.
486 (aarch64_ins_sve_addr_zi_u5): Likewise.
487 (aarch64_ins_sve_addr_zz): Likewise.
488 (aarch64_ins_sve_addr_zz_lsl): Likewise.
489 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
490 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
491 * aarch64-asm-2.c: Regenerate.
492 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
493 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
494 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
495 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
496 (aarch64_ext_sve_addr_ri_u6): Likewise.
497 (aarch64_ext_sve_addr_rr_lsl): Likewise.
498 (aarch64_ext_sve_addr_rz_xtw): Likewise.
499 (aarch64_ext_sve_addr_zi_u5): Likewise.
500 (aarch64_ext_sve_addr_zz): Likewise.
501 (aarch64_ext_sve_addr_zz_lsl): Likewise.
502 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
503 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
504 * aarch64-dis-2.c: Regenerate.
506 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
508 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
509 AARCH64_OPND_SVE_PATTERN_SCALED.
510 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
511 * aarch64-opc.c (fields): Add a corresponding entry.
512 (set_multiplier_out_of_range_error): New function.
513 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
514 (operand_general_constraint_met_p): Handle
515 AARCH64_OPND_SVE_PATTERN_SCALED.
516 (print_register_offset_address): Use PRIi64 to print the
518 (aarch64_print_operand): Likewise. Handle
519 AARCH64_OPND_SVE_PATTERN_SCALED.
520 * aarch64-opc-2.c: Regenerate.
521 * aarch64-asm.h (ins_sve_scale): New inserter.
522 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
523 * aarch64-asm-2.c: Regenerate.
524 * aarch64-dis.h (ext_sve_scale): New inserter.
525 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
526 * aarch64-dis-2.c: Regenerate.
528 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
530 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
531 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
532 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
533 (FLD_SVE_prfop): Likewise.
534 * aarch64-opc.c: Include libiberty.h.
535 (aarch64_sve_pattern_array): New variable.
536 (aarch64_sve_prfop_array): Likewise.
537 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
538 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
539 AARCH64_OPND_SVE_PRFOP.
540 * aarch64-asm-2.c: Regenerate.
541 * aarch64-dis-2.c: Likewise.
542 * aarch64-opc-2.c: Likewise.
544 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
546 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
547 AARCH64_OPND_QLF_P_[ZM].
548 (aarch64_print_operand): Print /z and /m where appropriate.
550 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
552 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
553 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
554 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
555 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
556 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
557 * aarch64-opc.c (fields): Add corresponding entries here.
558 (operand_general_constraint_met_p): Check that SVE register lists
559 have the correct length. Check the ranges of SVE index registers.
560 Check for cases where p8-p15 are used in 3-bit predicate fields.
561 (aarch64_print_operand): Handle the new SVE operands.
562 * aarch64-opc-2.c: Regenerate.
563 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
564 * aarch64-asm.c (aarch64_ins_sve_index): New function.
565 (aarch64_ins_sve_reglist): Likewise.
566 * aarch64-asm-2.c: Regenerate.
567 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
568 * aarch64-dis.c (aarch64_ext_sve_index): New function.
569 (aarch64_ext_sve_reglist): Likewise.
570 * aarch64-dis-2.c: Regenerate.
572 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
574 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
575 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
576 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
577 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
580 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
582 * aarch64-opc.c (get_offset_int_reg_name): New function.
583 (print_immediate_offset_address): Likewise.
584 (print_register_offset_address): Take the base and offset
585 registers as parameters.
586 (aarch64_print_operand): Update caller accordingly. Use
587 print_immediate_offset_address.
589 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
591 * aarch64-opc.c (BANK): New macro.
592 (R32, R64): Take a register number as argument
595 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
597 * aarch64-opc.c (print_register_list): Add a prefix parameter.
598 (aarch64_print_operand): Update accordingly.
600 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
602 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
604 * aarch64-asm.h (ins_fpimm): New inserter.
605 * aarch64-asm.c (aarch64_ins_fpimm): New function.
606 * aarch64-asm-2.c: Regenerate.
607 * aarch64-dis.h (ext_fpimm): New extractor.
608 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
609 (aarch64_ext_fpimm): New function.
610 * aarch64-dis-2.c: Regenerate.
612 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
614 * aarch64-asm.c: Include libiberty.h.
615 (insert_fields): New function.
616 (aarch64_ins_imm): Use it.
617 * aarch64-dis.c (extract_fields): New function.
618 (aarch64_ext_imm): Use it.
620 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
622 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
623 with an esize parameter.
624 (operand_general_constraint_met_p): Update accordingly.
625 Fix misindented code.
626 * aarch64-asm.c (aarch64_ins_limm): Update call to
627 aarch64_logical_immediate_p.
629 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
631 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
633 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
635 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
637 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
639 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
641 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
643 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
644 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
645 xor3>: Delete mnemonics.
646 <cp_abort>: Rename mnemonic from ...
647 <cpabort>: ...to this.
648 <setb>: Change to a X form instruction.
649 <sync>: Change to 1 operand form.
650 <copy>: Delete mnemonic.
651 <copy_first>: Rename mnemonic from ...
653 <paste, paste.>: Delete mnemonics.
654 <paste_last>: Rename mnemonic from ...
655 <paste.>: ...to this.
657 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
659 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
661 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
663 * s390-mkopc.c (main): Support alternate arch strings.
665 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
667 * s390-opc.txt: Fix kmctr instruction type.
669 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
671 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
672 * i386-init.h: Regenerated.
674 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
676 * opcodes/arc-dis.c (print_insn_arc): Changed.
678 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
680 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
683 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
685 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
686 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
687 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
689 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
691 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
692 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
693 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
694 PREFIX_MOD_3_0FAE_REG_4.
695 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
696 PREFIX_MOD_3_0FAE_REG_4.
697 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
698 (cpu_flags): Add CpuPTWRITE.
699 * i386-opc.h (CpuPTWRITE): New.
700 (i386_cpu_flags): Add cpuptwrite.
701 * i386-opc.tbl: Add ptwrite instruction.
702 * i386-init.h: Regenerated.
703 * i386-tbl.h: Likewise.
705 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
707 * arc-dis.h: Wrap around in extern "C".
709 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
711 * aarch64-tbl.h (V8_2_INSN): New macro.
712 (aarch64_opcode_table): Use it.
714 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
716 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
717 CORE_INSN, __FP_INSN and SIMD_INSN.
719 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
721 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
722 (aarch64_opcode_table): Update uses accordingly.
724 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
725 Kwok Cheung Yeung <kcy@codesourcery.com>
728 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
729 'e_cmplwi' to 'e_cmpli' instead.
730 (OPVUPRT, OPVUPRT_MASK): Define.
731 (powerpc_opcodes): Add E200Z4 insns.
732 (vle_opcodes): Add context save/restore insns.
734 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
736 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
737 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
740 2016-07-27 Graham Markall <graham.markall@embecosm.com>
742 * arc-nps400-tbl.h: Change block comments to GNU format.
743 * arc-dis.c: Add new globals addrtypenames,
744 addrtypenames_max, and addtypeunknown.
745 (get_addrtype): New function.
746 (print_insn_arc): Print colons and address types when
748 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
749 define insert and extract functions for all address types.
750 (arc_operands): Add operands for colon and all address
752 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
753 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
754 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
755 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
756 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
757 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
759 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
761 * configure: Regenerated.
763 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
765 * arc-dis.c (skipclass): New structure.
766 (decodelist): New variable.
767 (is_compatible_p): New function.
768 (new_element): Likewise.
769 (skip_class_p): Likewise.
770 (find_format_from_table): Use skip_class_p function.
771 (find_format): Decode first the extension instructions.
772 (print_insn_arc): Select either ARCEM or ARCHS based on elf
774 (parse_option): New function.
775 (parse_disassembler_options): Likewise.
776 (print_arc_disassembler_options): Likewise.
777 (print_insn_arc): Use parse_disassembler_options function. Proper
778 select ARCv2 cpu variant.
779 * disassemble.c (disassembler_usage): Add ARC disassembler
782 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
784 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
785 annotation from the "nal" entry and reorder it beyond "bltzal".
787 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
789 * sparc-opc.c (ldtxa): New macro.
790 (sparc_opcodes): Use the macro defined above to add entries for
791 the LDTXA instructions.
792 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
795 2016-07-07 James Bowman <james.bowman@ftdichip.com>
797 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
800 2016-07-01 Jan Beulich <jbeulich@suse.com>
802 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
803 (movzb): Adjust to cover all permitted suffixes.
805 * i386-tbl.h: Re-generate.
807 2016-07-01 Jan Beulich <jbeulich@suse.com>
809 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
810 (lgdt): Remove Tbyte from non-64-bit variant.
811 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
812 xsaves64, xsavec64): Remove Disp16.
813 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
814 Remove Disp32S from non-64-bit variants. Remove Disp16 from
816 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
817 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
818 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
820 * i386-tbl.h: Re-generate.
822 2016-07-01 Jan Beulich <jbeulich@suse.com>
824 * i386-opc.tbl (xlat): Remove RepPrefixOk.
825 * i386-tbl.h: Re-generate.
827 2016-06-30 Yao Qi <yao.qi@linaro.org>
829 * arm-dis.c (print_insn): Fix typo in comment.
831 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
833 * aarch64-opc.c (operand_general_constraint_met_p): Check the
834 range of ldst_elemlist operands.
835 (print_register_list): Use PRIi64 to print the index.
836 (aarch64_print_operand): Likewise.
838 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
840 * mcore-opc.h: Remove sentinal.
841 * mcore-dis.c (print_insn_mcore): Adjust.
843 2016-06-23 Graham Markall <graham.markall@embecosm.com>
845 * arc-opc.c: Correct description of availability of NPS400
848 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
850 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
851 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
852 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
853 xor3>: New mnemonics.
854 <setb>: Change to a VX form instruction.
855 (insert_sh6): Add support for rldixor.
856 (extract_sh6): Likewise.
858 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
860 * arc-ext.h: Wrap in extern C.
862 2016-06-21 Graham Markall <graham.markall@embecosm.com>
864 * arc-dis.c (arc_insn_length): Add comment on instruction length.
865 Use same method for determining instruction length on ARC700 and
867 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
868 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
869 with the NPS400 subclass.
870 * arc-opc.c: Likewise.
872 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
874 * sparc-opc.c (rdasr): New macro.
880 (sparc_opcodes): Use the macros above to fix and expand the
881 definition of read/write instructions from/to
882 asr/privileged/hyperprivileged instructions.
883 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
884 %hva_mask_nz. Prefer softint_set and softint_clear over
885 set_softint and clear_softint.
886 (print_insn_sparc): Support %ver in Rd.
888 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
890 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
891 architecture according to the hardware capabilities they require.
893 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
895 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
896 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
897 bfd_mach_sparc_v9{c,d,e,v,m}.
898 * sparc-opc.c (MASK_V9C): Define.
899 (MASK_V9D): Likewise.
900 (MASK_V9E): Likewise.
901 (MASK_V9V): Likewise.
902 (MASK_V9M): Likewise.
903 (v6): Add MASK_V9{C,D,E,V,M}.
904 (v6notlet): Likewise.
908 (v9andleon): Likewise.
916 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
918 2016-06-15 Nick Clifton <nickc@redhat.com>
920 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
921 constants to match expected behaviour.
922 (nds32_parse_opcode): Likewise. Also for whitespace.
924 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
926 * arc-opc.c (extract_rhv1): Extract value from insn.
928 2016-06-14 Graham Markall <graham.markall@embecosm.com>
930 * arc-nps400-tbl.h: Add ldbit instruction.
931 * arc-opc.c: Add flag classes required for ldbit.
933 2016-06-14 Graham Markall <graham.markall@embecosm.com>
935 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
936 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
937 support the above instructions.
939 2016-06-14 Graham Markall <graham.markall@embecosm.com>
941 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
942 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
943 csma, cbba, zncv, and hofs.
944 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
945 support the above instructions.
947 2016-06-06 Graham Markall <graham.markall@embecosm.com>
949 * arc-nps400-tbl.h: Add andab and orab instructions.
951 2016-06-06 Graham Markall <graham.markall@embecosm.com>
953 * arc-nps400-tbl.h: Add addl-like instructions.
955 2016-06-06 Graham Markall <graham.markall@embecosm.com>
957 * arc-nps400-tbl.h: Add mxb and imxb instructions.
959 2016-06-06 Graham Markall <graham.markall@embecosm.com>
961 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
964 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
966 * s390-dis.c (option_use_insn_len_bits_p): New file scope
968 (init_disasm): Handle new command line option "insnlength".
969 (print_s390_disassembler_options): Mention new option in help
971 (print_insn_s390): Use the encoded insn length when dumping
972 unknown instructions.
974 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
976 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
977 to the address and set as symbol address for LDS/ STS immediate operands.
979 2016-06-07 Alan Modra <amodra@gmail.com>
981 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
982 cpu for "vle" to e500.
983 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
984 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
985 (PPCNONE): Delete, substitute throughout.
986 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
987 except for major opcode 4 and 31.
988 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
990 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
992 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
993 ARM_EXT_RAS in relevant entries.
995 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
998 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1001 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1004 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1005 (indir_v_mode): New.
1006 Add comments for '&'.
1007 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1008 (putop): Handle '&'.
1009 (intel_operand_size): Handle indir_v_mode.
1010 (OP_E_register): Likewise.
1011 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1012 64-bit indirect call/jmp for AMD64.
1013 * i386-tbl.h: Regenerated
1015 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1017 * arc-dis.c (struct arc_operand_iterator): New structure.
1018 (find_format_from_table): All the old content from find_format,
1019 with some minor adjustments, and parameter renaming.
1020 (find_format_long_instructions): New function.
1021 (find_format): Rewritten.
1022 (arc_insn_length): Add LSB parameter.
1023 (extract_operand_value): New function.
1024 (operand_iterator_next): New function.
1025 (print_insn_arc): Use new functions to find opcode, and iterator
1027 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1028 (extract_nps_3bit_dst_short): New function.
1029 (insert_nps_3bit_src2_short): New function.
1030 (extract_nps_3bit_src2_short): New function.
1031 (insert_nps_bitop1_size): New function.
1032 (extract_nps_bitop1_size): New function.
1033 (insert_nps_bitop2_size): New function.
1034 (extract_nps_bitop2_size): New function.
1035 (insert_nps_bitop_mod4_msb): New function.
1036 (extract_nps_bitop_mod4_msb): New function.
1037 (insert_nps_bitop_mod4_lsb): New function.
1038 (extract_nps_bitop_mod4_lsb): New function.
1039 (insert_nps_bitop_dst_pos3_pos4): New function.
1040 (extract_nps_bitop_dst_pos3_pos4): New function.
1041 (insert_nps_bitop_ins_ext): New function.
1042 (extract_nps_bitop_ins_ext): New function.
1043 (arc_operands): Add new operands.
1044 (arc_long_opcodes): New global array.
1045 (arc_num_long_opcodes): New global.
1046 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1048 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1050 * nds32-asm.h: Add extern "C".
1051 * sh-opc.h: Likewise.
1053 2016-06-01 Graham Markall <graham.markall@embecosm.com>
1055 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1056 0,b,limm to the rflt instruction.
1058 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1060 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1063 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1066 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1067 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1068 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1069 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1070 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1071 * i386-init.h: Regenerated.
1073 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1076 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1077 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1078 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1079 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1080 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1081 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1082 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1083 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1084 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1085 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1086 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1087 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1088 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1089 CpuRegMask for AVX512.
1090 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1092 (set_bitfield_from_cpu_flag_init): New function.
1093 (set_bitfield): Remove const on f. Call
1094 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1095 * i386-opc.h (CpuRegMMX): New.
1096 (CpuRegXMM): Likewise.
1097 (CpuRegYMM): Likewise.
1098 (CpuRegZMM): Likewise.
1099 (CpuRegMask): Likewise.
1100 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1102 * i386-init.h: Regenerated.
1103 * i386-tbl.h: Likewise.
1105 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1108 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1109 (opcode_modifiers): Add AMD64 and Intel64.
1110 (main): Properly verify CpuMax.
1111 * i386-opc.h (CpuAMD64): Removed.
1112 (CpuIntel64): Likewise.
1113 (CpuMax): Set to CpuNo64.
1114 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1116 (Intel64): Likewise.
1117 (i386_opcode_modifier): Add amd64 and intel64.
1118 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1120 * i386-init.h: Regenerated.
1121 * i386-tbl.h: Likewise.
1123 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1126 * i386-gen.c (main): Fail if CpuMax is incorrect.
1127 * i386-opc.h (CpuMax): Set to CpuIntel64.
1128 * i386-tbl.h: Regenerated.
1130 2016-05-27 Nick Clifton <nickc@redhat.com>
1133 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1134 (msp430dis_opcode_unsigned): New function.
1135 (msp430dis_opcode_signed): New function.
1136 (msp430_singleoperand): Use the new opcode reading functions.
1137 Only disassenmble bytes if they were successfully read.
1138 (msp430_doubleoperand): Likewise.
1139 (msp430_branchinstr): Likewise.
1140 (msp430x_callx_instr): Likewise.
1141 (print_insn_msp430): Check that it is safe to read bytes before
1142 attempting disassembly. Use the new opcode reading functions.
1144 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1146 * ppc-opc.c (CY): New define. Document it.
1147 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1149 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1151 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1152 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1153 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1154 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1156 * i386-init.h: Regenerated.
1158 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1161 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1162 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1163 * i386-init.h: Regenerated.
1165 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1167 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1168 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1169 * i386-init.h: Regenerated.
1171 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1173 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1175 (print_insn_arc): Set insn_type information.
1176 * arc-opc.c (C_CC): Add F_CLASS_COND.
1177 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1178 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1179 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1180 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1181 (brne, brne_s, jeq_s, jne_s): Likewise.
1183 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1185 * arc-tbl.h (neg): New instruction variant.
1187 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1189 * arc-dis.c (find_format, find_format, get_auxreg)
1190 (print_insn_arc): Changed.
1191 * arc-ext.h (INSERT_XOP): Likewise.
1193 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1195 * tic54x-dis.c (sprint_mmr): Adjust.
1196 * tic54x-opc.c: Likewise.
1198 2016-05-19 Alan Modra <amodra@gmail.com>
1200 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1202 2016-05-19 Alan Modra <amodra@gmail.com>
1204 * ppc-opc.c: Formatting.
1205 (NSISIGNOPT): Define.
1206 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1208 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1210 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1211 replacing references to `micromips_ase' throughout.
1212 (_print_insn_mips): Don't use file-level microMIPS annotation to
1213 determine the disassembly mode with the symbol table.
1215 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1217 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1219 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1221 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1223 * mips-opc.c (D34): New macro.
1224 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1226 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1228 * i386-dis.c (prefix_table): Add RDPID instruction.
1229 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1230 (cpu_flags): Add RDPID bitfield.
1231 * i386-opc.h (enum): Add RDPID element.
1232 (i386_cpu_flags): Add RDPID field.
1233 * i386-opc.tbl: Add RDPID instruction.
1234 * i386-init.h: Regenerate.
1235 * i386-tbl.h: Regenerate.
1237 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1239 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1240 branch type of a symbol.
1241 (print_insn): Likewise.
1243 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1245 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1246 Mainline Security Extensions instructions.
1247 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1248 Extensions instructions.
1249 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1251 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1254 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1256 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1258 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1260 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1261 (arcExtMap_genOpcode): Likewise.
1262 * arc-opc.c (arg_32bit_rc): Define new variable.
1263 (arg_32bit_u6): Likewise.
1264 (arg_32bit_limm): Likewise.
1266 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1268 * aarch64-gen.c (VERIFIER): Define.
1269 * aarch64-opc.c (VERIFIER): Define.
1270 (verify_ldpsw): Use static linkage.
1271 * aarch64-opc.h (verify_ldpsw): Remove.
1272 * aarch64-tbl.h: Use VERIFIER for verifiers.
1274 2016-04-28 Nick Clifton <nickc@redhat.com>
1277 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1278 * aarch64-opc.c (verify_ldpsw): New function.
1279 * aarch64-opc.h (verify_ldpsw): New prototype.
1280 * aarch64-tbl.h: Add initialiser for verifier field.
1281 (LDPSW): Set verifier to verify_ldpsw.
1283 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1287 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1288 smaller than address size.
1290 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1292 * alpha-dis.c: Regenerate.
1293 * crx-dis.c: Likewise.
1294 * disassemble.c: Likewise.
1295 * epiphany-opc.c: Likewise.
1296 * fr30-opc.c: Likewise.
1297 * frv-opc.c: Likewise.
1298 * ip2k-opc.c: Likewise.
1299 * iq2000-opc.c: Likewise.
1300 * lm32-opc.c: Likewise.
1301 * lm32-opinst.c: Likewise.
1302 * m32c-opc.c: Likewise.
1303 * m32r-opc.c: Likewise.
1304 * m32r-opinst.c: Likewise.
1305 * mep-opc.c: Likewise.
1306 * mt-opc.c: Likewise.
1307 * or1k-opc.c: Likewise.
1308 * or1k-opinst.c: Likewise.
1309 * tic80-opc.c: Likewise.
1310 * xc16x-opc.c: Likewise.
1311 * xstormy16-opc.c: Likewise.
1313 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1315 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1316 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1317 calcsd, and calcxd instructions.
1318 * arc-opc.c (insert_nps_bitop_size): Delete.
1319 (extract_nps_bitop_size): Delete.
1320 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1321 (extract_nps_qcmp_m3): Define.
1322 (extract_nps_qcmp_m2): Define.
1323 (extract_nps_qcmp_m1): Define.
1324 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1325 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1326 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1327 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1328 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1331 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1333 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1335 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1337 * Makefile.in: Regenerated with automake 1.11.6.
1338 * aclocal.m4: Likewise.
1340 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1342 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1344 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1345 (extract_nps_cmem_uimm16): New function.
1346 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1348 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1350 * arc-dis.c (arc_insn_length): New function.
1351 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1352 (find_format): Change insnLen parameter to unsigned.
1354 2016-04-13 Nick Clifton <nickc@redhat.com>
1357 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1358 the LD.B and LD.BU instructions.
1360 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1362 * arc-dis.c (find_format): Check for extension flags.
1363 (print_flags): New function.
1364 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1366 * arc-ext.c (arcExtMap_coreRegName): Use
1367 LAST_EXTENSION_CORE_REGISTER.
1368 (arcExtMap_coreReadWrite): Likewise.
1369 (dump_ARC_extmap): Update printing.
1370 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1371 (arc_aux_regs): Add cpu field.
1372 * arc-regs.h: Add cpu field, lower case name aux registers.
1374 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1376 * arc-tbl.h: Add rtsc, sleep with no arguments.
1378 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1380 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1382 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1383 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1384 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1385 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1386 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1387 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1388 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1389 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1390 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1391 (arc_opcode arc_opcodes): Null terminate the array.
1392 (arc_num_opcodes): Remove.
1393 * arc-ext.h (INSERT_XOP): Define.
1394 (extInstruction_t): Likewise.
1395 (arcExtMap_instName): Delete.
1396 (arcExtMap_insn): New function.
1397 (arcExtMap_genOpcode): Likewise.
1398 * arc-ext.c (ExtInstruction): Remove.
1399 (create_map): Zero initialize instruction fields.
1400 (arcExtMap_instName): Remove.
1401 (arcExtMap_insn): New function.
1402 (dump_ARC_extmap): More info while debuging.
1403 (arcExtMap_genOpcode): New function.
1404 * arc-dis.c (find_format): New function.
1405 (print_insn_arc): Use find_format.
1406 (arc_get_disassembler): Enable dump_ARC_extmap only when
1409 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1411 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1412 instruction bits out.
1414 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1416 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1417 * arc-opc.c (arc_flag_operands): Add new flags.
1418 (arc_flag_classes): Add new classes.
1420 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1422 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1424 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1426 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1427 encode1, rflt, crc16, and crc32 instructions.
1428 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1429 (arc_flag_classes): Add C_NPS_R.
1430 (insert_nps_bitop_size_2b): New function.
1431 (extract_nps_bitop_size_2b): Likewise.
1432 (insert_nps_bitop_uimm8): Likewise.
1433 (extract_nps_bitop_uimm8): Likewise.
1434 (arc_operands): Add new operand entries.
1436 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1438 * arc-regs.h: Add a new subclass field. Add double assist
1439 accumulator register values.
1440 * arc-tbl.h: Use DPA subclass to mark the double assist
1441 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1442 * arc-opc.c (RSP): Define instead of SP.
1443 (arc_aux_regs): Add the subclass field.
1445 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1447 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1449 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1451 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1454 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1456 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1457 issues. No functional changes.
1459 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1461 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1462 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1463 (RTT): Remove duplicate.
1464 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1465 (PCT_CONFIG*): Remove.
1466 (D1L, D1H, D2H, D2L): Define.
1468 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1470 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1472 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1474 * arc-tbl.h (invld07): Remove.
1475 * arc-ext-tbl.h: New file.
1476 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1477 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1479 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1481 Fix -Wstack-usage warnings.
1482 * aarch64-dis.c (print_operands): Substitute size.
1483 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1485 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1487 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1488 to get a proper diagnostic when an invalid ASR register is used.
1490 2016-03-22 Nick Clifton <nickc@redhat.com>
1492 * configure: Regenerate.
1494 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1496 * arc-nps400-tbl.h: New file.
1497 * arc-opc.c: Add top level comment.
1498 (insert_nps_3bit_dst): New function.
1499 (extract_nps_3bit_dst): New function.
1500 (insert_nps_3bit_src2): New function.
1501 (extract_nps_3bit_src2): New function.
1502 (insert_nps_bitop_size): New function.
1503 (extract_nps_bitop_size): New function.
1504 (arc_flag_operands): Add nps400 entries.
1505 (arc_flag_classes): Add nps400 entries.
1506 (arc_operands): Add nps400 entries.
1507 (arc_opcodes): Add nps400 include.
1509 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1511 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1512 the new class enum values.
1514 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1516 * arc-dis.c (print_insn_arc): Handle nps400.
1518 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1520 * arc-opc.c (BASE): Delete.
1522 2016-03-18 Nick Clifton <nickc@redhat.com>
1525 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1526 of MOV insn that aliases an ORR insn.
1528 2016-03-16 Jiong Wang <jiong.wang@arm.com>
1530 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1532 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1534 * mcore-opc.h: Add const qualifiers.
1535 * microblaze-opc.h (struct op_code_struct): Likewise.
1536 * sh-opc.h: Likewise.
1537 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1538 (tic4x_print_op): Likewise.
1540 2016-03-02 Alan Modra <amodra@gmail.com>
1542 * or1k-desc.h: Regenerate.
1543 * fr30-ibld.c: Regenerate.
1544 * rl78-decode.c: Regenerate.
1546 2016-03-01 Nick Clifton <nickc@redhat.com>
1549 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1551 2016-02-24 Renlin Li <renlin.li@arm.com>
1553 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1554 (print_insn_coprocessor): Support fp16 instructions.
1556 2016-02-24 Renlin Li <renlin.li@arm.com>
1558 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1559 vminnm, vrint(mpna).
1561 2016-02-24 Renlin Li <renlin.li@arm.com>
1563 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1564 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1566 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1568 * i386-dis.c (print_insn): Parenthesize expression to prevent
1569 truncated addresses.
1572 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1573 Janek van Oirschot <jvanoirs@synopsys.com>
1575 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1578 2016-02-04 Nick Clifton <nickc@redhat.com>
1581 * msp430-dis.c (print_insn_msp430): Add a special case for
1582 decoding an RRC instruction with the ZC bit set in the extension
1585 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1587 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1588 * epiphany-ibld.c: Regenerate.
1589 * fr30-ibld.c: Regenerate.
1590 * frv-ibld.c: Regenerate.
1591 * ip2k-ibld.c: Regenerate.
1592 * iq2000-ibld.c: Regenerate.
1593 * lm32-ibld.c: Regenerate.
1594 * m32c-ibld.c: Regenerate.
1595 * m32r-ibld.c: Regenerate.
1596 * mep-ibld.c: Regenerate.
1597 * mt-ibld.c: Regenerate.
1598 * or1k-ibld.c: Regenerate.
1599 * xc16x-ibld.c: Regenerate.
1600 * xstormy16-ibld.c: Regenerate.
1602 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1604 * epiphany-dis.c: Regenerated from latest cpu files.
1606 2016-02-01 Michael McConville <mmcco@mykolab.com>
1608 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1611 2016-01-25 Renlin Li <renlin.li@arm.com>
1613 * arm-dis.c (mapping_symbol_for_insn): New function.
1614 (find_ifthen_state): Call mapping_symbol_for_insn().
1616 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1618 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1619 of MSR UAO immediate operand.
1621 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1623 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1624 instruction support.
1626 2016-01-17 Alan Modra <amodra@gmail.com>
1628 * configure: Regenerate.
1630 2016-01-14 Nick Clifton <nickc@redhat.com>
1632 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1633 instructions that can support stack pointer operations.
1634 * rl78-decode.c: Regenerate.
1635 * rl78-dis.c: Fix display of stack pointer in MOVW based
1638 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1640 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1641 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1642 erxtatus_el1 and erxaddr_el1.
1644 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1646 * arm-dis.c (arm_opcodes): Add "esb".
1647 (thumb_opcodes): Likewise.
1649 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1651 * ppc-opc.c <xscmpnedp>: Delete.
1652 <xvcmpnedp>: Likewise.
1653 <xvcmpnedp.>: Likewise.
1654 <xvcmpnesp>: Likewise.
1655 <xvcmpnesp.>: Likewise.
1657 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1660 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1663 2016-01-01 Alan Modra <amodra@gmail.com>
1665 Update year range in copyright notice of all files.
1667 For older changes see ChangeLog-2015
1669 Copyright (C) 2016 Free Software Foundation, Inc.
1671 Copying and distribution of this file, with or without modification,
1672 are permitted in any medium without royalty provided the copyright
1673 notice and this notice are preserved.
1679 version-control: never