opcodes/ChangeLog

   1 2020-06-29  Alan Modra  <amodra@gmail.com>
   2
   3         * arm-dis.c: Use C style comments.
   4         * cr16-opc.c: Likewise.
   5         * ft32-dis.c: Likewise.
   6         * moxie-opc.c: Likewise.
   7         * tic54x-dis.c: Likewise.
   8         * s12z-opc.c: Remove useless comment.
   9         * xgate-dis.c: Likewise.
  10
  11 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
  12
  13         * i386-opc.tbl: Add a blank line.
  14
  15 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
  16
  17         * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
  18         (VecSIB128): Renamed to ...
  19         (VECSIB128): This.
  20         (VecSIB256): Renamed to ...
  21         (VECSIB256): This.
  22         (VecSIB512): Renamed to ...
  23         (VECSIB512): This.
  24         (VecSIB): Renamed to ...
  25         (SIB): This.
  26         (i386_opcode_modifier): Replace vecsib with sib.
  27         * i386-opc.tbl (VecSIB128): New.
  28         (VecSIB256): Likewise.
  29         (VecSIB512): Likewise.
  30         Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
  31         and VecSIB512, respectively.
  32
  33 2020-06-26  Jan Beulich  <jbeulich@suse.com>
  34
  35         * i386-dis.c: Adjust description of I macro.
  36         (x86_64_table): Drop use of I.
  37         (float_mem): Replace use of I.
  38         (putop): Remove handling of I. Adjust setting/clearing of "alt".
  39
  40 2020-06-26  Jan Beulich  <jbeulich@suse.com>
  41
  42         * i386-dis.c: (print_insn): Avoid straight assignment to
  43         priv.orig_sizeflag when processing -M sub-options.
  44
  45 2020-06-25  Jan Beulich  <jbeulich@suse.com>
  46
  47         * i386-dis.c: Adjust description of J macro.
  48         (dis386, x86_64_table, mod_table): Replace J.
  49         (putop): Remove handling of J.
  50
  51 2020-06-25  Jan Beulich  <jbeulich@suse.com>
  52
  53         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
  54
  55 2020-06-25  Jan Beulich  <jbeulich@suse.com>
  56
  57         * i386-dis.c: Adjust description of "LQ" macro.
  58         (dis386_twobyte): Use LQ for sysret.
  59         (putop): Adjust handling of LQ.
  60
  61 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
  62
  63         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
  64         * riscv-dis.c: Include elfxx-riscv.h.
  65
  66 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
  67
  68         * i386-dis.c (prefix_table): Revert the last vmgexit change.
  69
  70 2020-06-17  Lili Cui  <lili.cui@intel.com>
  71
  72         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
  73
  74 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
  75
  76         PR gas/26115
  77         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
  78         * i386-opc.tbl: Likewise.
  79         * i386-tbl.h: Regenerated.
  80
  81 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
  82
  83         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
  84
  85 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
  86
  87         * aarch64-opc.c (SYSREG): New macro for describing system registers.
  88         (SR_CORE): Likewise.
  89         (SR_FEAT): Likewise.
  90         (SR_RNG): Likewise.
  91         (SR_V8_1): Likewise.
  92         (SR_V8_2): Likewise.
  93         (SR_V8_3): Likewise.
  94         (SR_V8_4): Likewise.
  95         (SR_PAN): Likewise.
  96         (SR_RAS): Likewise.
  97         (SR_SSBS): Likewise.
  98         (SR_SVE): Likewise.
  99         (SR_ID_PFR2): Likewise.
 100         (SR_PROFILE): Likewise.
 101         (SR_MEMTAG): Likewise.
 102         (SR_SCXTNUM): Likewise.
 103         (aarch64_sys_regs): Refactor to store feature information in the table.
 104         (aarch64_sys_reg_supported_p): Collapse logic for system registers
 105         that now describe their own features.
 106         (aarch64_pstatefield_supported_p): Likewise.
 107
 108 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
 109
 110         * i386-dis.c (prefix_table): Fix a typo in comments.
 111
 112 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 113
 114         * i386-dis.c (rex_ignored): Delete.
 115         (ckprefix): Drop rex_ignored initialization.
 116         (get_valid_dis386): Drop setting of rex_ignored.
 117         (print_insn): Drop checking of rex_ignored. Don't record data
 118         size prefix as used with VEX-and-alike encodings.
 119
 120 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 121
 122         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
 123         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
 124         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
 125         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
 126         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
 127         VEX_0F12, and VEX_0F16.
 128         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
 129         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
 130         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
 131         from movlps and movhlps. New MOD_0F12_PREFIX_2,
 132         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
 133         MOD_VEX_0F16_PREFIX_2 entries.
 134
 135 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 136
 137         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
 138         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
 139         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 140         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
 141         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 142         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
 143         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
 144         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
 145         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
 146         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
 147         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
 148         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
 149         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
 150         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
 151         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
 152         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
 153         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
 154         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
 155         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
 156         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
 157         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
 158         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
 159         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
 160         EVEX_W_0FC6_P_2): Delete.
 161         (print_insn): Add EVEX.W vs embedded prefix consistency check
 162         to prefix validation.
 163         * i386-dis-evex.h (evex_table): Don't further descend for
 164         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
 165         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
 166         and 0F2B.
 167         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
 168         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
 169         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
 170         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
 171         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
 172         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 173         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
 174         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
 175         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
 176         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
 177         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
 178         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 179         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
 180         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
 181         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 182         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
 183         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 184         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
 185         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
 186         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 187         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
 188         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
 189         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
 190         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
 191         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
 192         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
 193         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
 194
 195 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 196
 197         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
 198         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
 199         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
 200         vmovmskpX.
 201         (print_insn): Drop pointless check against bad_opcode. Split
 202         prefix validation into legacy and VEX-and-alike parts.
 203         (putop): Re-work 'X' macro handling.
 204
 205 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 206
 207         * i386-dis.c (MOD_0F51): Rename to ...
 208         (MOD_0F50): ... this.
 209
 210 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
 211
 212         * arm-dis.c (arm_opcodes): Add dfb.
 213         (thumb32_opcodes): Add dfb.
 214
 215 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 216
 217         * i386-opc.h (reg_entry): Const-qualify reg_name field.
 218
 219 2020-06-06  Alan Modra  <amodra@gmail.com>
 220
 221         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
 222
 223 2020-06-05  Alan Modra  <amodra@gmail.com>
 224
 225         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
 226         size is large enough.
 227
 228 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
 229
 230         * disassemble.c (disassemble_init_for_target): Set endian_code for
 231         bpf targets.
 232         * bpf-desc.c: Regenerate.
 233         * bpf-opc.c: Likewise.
 234         * bpf-dis.c: Likewise.
 235
 236 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
 237
 238         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
 239         (cgen_put_insn_value): Likewise.
 240         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
 241         * cgen-dis.in (print_insn): Likewise.
 242         * cgen-ibld.in (insert_1): Likewise.
 243         (insert_1): Likewise.
 244         (insert_insn_normal): Likewise.
 245         (extract_1): Likewise.
 246         * bpf-dis.c: Regenerate.
 247         * bpf-ibld.c: Likewise.
 248         * bpf-ibld.c: Likewise.
 249         * cgen-dis.in: Likewise.
 250         * cgen-ibld.in: Likewise.
 251         * cgen-opc.c: Likewise.
 252         * epiphany-dis.c: Likewise.
 253         * epiphany-ibld.c: Likewise.
 254         * fr30-dis.c: Likewise.
 255         * fr30-ibld.c: Likewise.
 256         * frv-dis.c: Likewise.
 257         * frv-ibld.c: Likewise.
 258         * ip2k-dis.c: Likewise.
 259         * ip2k-ibld.c: Likewise.
 260         * iq2000-dis.c: Likewise.
 261         * iq2000-ibld.c: Likewise.
 262         * lm32-dis.c: Likewise.
 263         * lm32-ibld.c: Likewise.
 264         * m32c-dis.c: Likewise.
 265         * m32c-ibld.c: Likewise.
 266         * m32r-dis.c: Likewise.
 267         * m32r-ibld.c: Likewise.
 268         * mep-dis.c: Likewise.
 269         * mep-ibld.c: Likewise.
 270         * mt-dis.c: Likewise.
 271         * mt-ibld.c: Likewise.
 272         * or1k-dis.c: Likewise.
 273         * or1k-ibld.c: Likewise.
 274         * xc16x-dis.c: Likewise.
 275         * xc16x-ibld.c: Likewise.
 276         * xstormy16-dis.c: Likewise.
 277         * xstormy16-ibld.c: Likewise.
 278
 279 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
 280
 281         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
 282         (print_insn_): Handle instruction endian.
 283         * bpf-dis.c: Regenerate.
 284         * bpf-desc.c: Regenerate.
 285         * epiphany-dis.c: Likewise.
 286         * epiphany-desc.c: Likewise.
 287         * fr30-dis.c: Likewise.
 288         * fr30-desc.c: Likewise.
 289         * frv-dis.c: Likewise.
 290         * frv-desc.c: Likewise.
 291         * ip2k-dis.c: Likewise.
 292         * ip2k-desc.c: Likewise.
 293         * iq2000-dis.c: Likewise.
 294         * iq2000-desc.c: Likewise.
 295         * lm32-dis.c: Likewise.
 296         * lm32-desc.c: Likewise.
 297         * m32c-dis.c: Likewise.
 298         * m32c-desc.c: Likewise.
 299         * m32r-dis.c: Likewise.
 300         * m32r-desc.c: Likewise.
 301         * mep-dis.c: Likewise.
 302         * mep-desc.c: Likewise.
 303         * mt-dis.c: Likewise.
 304         * mt-desc.c: Likewise.
 305         * or1k-dis.c: Likewise.
 306         * or1k-desc.c: Likewise.
 307         * xc16x-dis.c: Likewise.
 308         * xc16x-desc.c: Likewise.
 309         * xstormy16-dis.c: Likewise.
 310         * xstormy16-desc.c: Likewise.
 311
 312 2020-06-03  Nick Clifton  <nickc@redhat.com>
 313
 314         * po/sr.po: Updated Serbian translation.
 315
 316 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 317
 318         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 319         (riscv_get_priv_spec_class): Likewise.
 320
 321 2020-06-01  Alan Modra  <amodra@gmail.com>
 322
 323         * bpf-desc.c: Regenerate.
 324
 325 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 326             David Faust <david.faust@oracle.com>
 327
 328         * bpf-desc.c: Regenerate.
 329         * bpf-opc.h: Likewise.
 330         * bpf-opc.c: Likewise.
 331         * bpf-dis.c: Likewise.
 332
 333 2020-05-28  Alan Modra  <amodra@gmail.com>
 334
 335         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 336         values.
 337
 338 2020-05-28  Alan Modra  <amodra@gmail.com>
 339
 340         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 341         immediates.
 342         (print_insn_ns32k): Revert last change.
 343
 344 2020-05-28  Nick Clifton  <nickc@redhat.com>
 345
 346         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 347         static.
 348
 349 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 350
 351         Fix extraction of signed constants in nios2 disassembler (again).
 352
 353         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 354         extractions of signed fields.
 355
 356 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 357
 358         * s390-opc.txt: Relocate vector load/store instructions with
 359         additional alignment parameter and change architecture level
 360         constraint from z14 to z13.
 361
 362 2020-05-21  Alan Modra  <amodra@gmail.com>
 363
 364         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 365         * sparc-dis.c: Likewise.
 366         * tic4x-dis.c: Likewise.
 367         * xtensa-dis.c: Likewise.
 368         * bpf-desc.c: Regenerate.
 369         * epiphany-desc.c: Regenerate.
 370         * fr30-desc.c: Regenerate.
 371         * frv-desc.c: Regenerate.
 372         * ip2k-desc.c: Regenerate.
 373         * iq2000-desc.c: Regenerate.
 374         * lm32-desc.c: Regenerate.
 375         * m32c-desc.c: Regenerate.
 376         * m32r-desc.c: Regenerate.
 377         * mep-asm.c: Regenerate.
 378         * mep-desc.c: Regenerate.
 379         * mt-desc.c: Regenerate.
 380         * or1k-desc.c: Regenerate.
 381         * xc16x-desc.c: Regenerate.
 382         * xstormy16-desc.c: Regenerate.
 383
 384 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 385
 386         * riscv-opc.c (riscv_ext_version_table): The table used to store
 387         all information about the supported spec and the corresponding ISA
 388         versions.  Currently, only Zicsr is supported to verify the
 389         correctness of Z sub extension settings.  Others will be supported
 390         in the future patches.
 391         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 392         classes and the corresponding strings.
 393         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 394         spec class by giving a ISA spec string.
 395         * riscv-opc.c (struct priv_spec_t): New structure.
 396         (struct priv_spec_t priv_specs): List for all supported privilege spec
 397         classes and the corresponding strings.
 398         (riscv_get_priv_spec_class): New function.  Get the corresponding
 399         privilege spec class by giving a spec string.
 400         (riscv_get_priv_spec_name): New function.  Get the corresponding
 401         privilege spec string by giving a CSR version class.
 402         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 403         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 404         according to the chosen version.  Build a hash table riscv_csr_hash to
 405         store the valid CSR for the chosen pirv verison.  Dump the direct
 406         CSR address rather than it's name if it is invalid.
 407         (parse_riscv_dis_option_without_args): New function.  Parse the options
 408         without arguments.
 409         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 410         parse the options without arguments first, and then handle the options
 411         with arguments.  Add the new option -Mpriv-spec, which has argument.
 412         * riscv-dis.c (print_riscv_disassembler_options): Add description
 413         about the new OBJDUMP option.
 414
 415 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 416
 417         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 418         WC values on POWER10 sync, dcbf  and wait instructions.
 419         (insert_pl, extract_pl): New functions.
 420         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 421         (LS3): New , 3-bit L for sync.
 422         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 423         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 424         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 425         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 426         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 427         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 428         <wait>: Enable PL operand on POWER10.
 429         <dcbf>: Enable L3OPT operand on POWER10.
 430         <sync>: Enable SC2 operand on POWER10.
 431
 432 2020-05-19  Stafford Horne  <shorne@gmail.com>
 433
 434         PR 25184
 435         * or1k-asm.c: Regenerate.
 436         * or1k-desc.c: Regenerate.
 437         * or1k-desc.h: Regenerate.
 438         * or1k-dis.c: Regenerate.
 439         * or1k-ibld.c: Regenerate.
 440         * or1k-opc.c: Regenerate.
 441         * or1k-opc.h: Regenerate.
 442         * or1k-opinst.c: Regenerate.
 443
 444 2020-05-11  Alan Modra  <amodra@gmail.com>
 445
 446         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 447         xsmaxcqp, xsmincqp.
 448
 449 2020-05-11  Alan Modra  <amodra@gmail.com>
 450
 451         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 452         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 453
 454 2020-05-11  Alan Modra  <amodra@gmail.com>
 455
 456         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 457
 458 2020-05-11  Alan Modra  <amodra@gmail.com>
 459
 460         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 461         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 462
 463 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 464
 465         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 466         mnemonics.
 467
 468 2020-05-11  Alan Modra  <amodra@gmail.com>
 469
 470         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 471         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 472         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 473         (prefix_opcodes): Add xxeval.
 474
 475 2020-05-11  Alan Modra  <amodra@gmail.com>
 476
 477         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 478         xxgenpcvwm, xxgenpcvdm.
 479
 480 2020-05-11  Alan Modra  <amodra@gmail.com>
 481
 482         * ppc-opc.c (MP, VXVAM_MASK): Define.
 483         (VXVAPS_MASK): Use VXVA_MASK.
 484         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 485         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 486         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 487         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 488
 489 2020-05-11  Alan Modra  <amodra@gmail.com>
 490             Peter Bergner  <bergner@linux.ibm.com>
 491
 492         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 493         New functions.
 494         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 495         YMSK2, XA6a, XA6ap, XB6a entries.
 496         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 497         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 498         (PPCVSX4): Define.
 499         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 500         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 501         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 502         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 503         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 504         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 505         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 506         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 507         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 508         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 509         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 510         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 511         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 512         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 513
 514 2020-05-11  Alan Modra  <amodra@gmail.com>
 515
 516         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 517         (insert_xts, extract_xts): New functions.
 518         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 519         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 520         (VXRC_MASK, VXSH_MASK): Define.
 521         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 522         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 523         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 524         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 525         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 526         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 527         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 528
 529 2020-05-11  Alan Modra  <amodra@gmail.com>
 530
 531         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 532         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 533         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 534         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 535         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 536
 537 2020-05-11  Alan Modra  <amodra@gmail.com>
 538
 539         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 540         (XTP, DQXP, DQXP_MASK): Define.
 541         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 542         (prefix_opcodes): Add plxvp and pstxvp.
 543
 544 2020-05-11  Alan Modra  <amodra@gmail.com>
 545
 546         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 547         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 548         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 549
 550 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 551
 552         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 553
 554 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 555
 556         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 557         (L1OPT): Define.
 558         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 559
 560 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 561
 562         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 563
 564 2020-05-11  Alan Modra  <amodra@gmail.com>
 565
 566         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 567
 568 2020-05-11  Alan Modra  <amodra@gmail.com>
 569
 570         * ppc-dis.c (ppc_opts): Add "power10" entry.
 571         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 572         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 573
 574 2020-05-11  Nick Clifton  <nickc@redhat.com>
 575
 576         * po/fr.po: Updated French translation.
 577
 578 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 579
 580         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 581         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 582         (operand_general_constraint_met_p): validate
 583         AARCH64_OPND_UNDEFINED.
 584         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 585         for FLD_imm16_2.
 586         * aarch64-asm-2.c: Regenerated.
 587         * aarch64-dis-2.c: Regenerated.
 588         * aarch64-opc-2.c: Regenerated.
 589
 590 2020-04-29  Nick Clifton  <nickc@redhat.com>
 591
 592         PR 22699
 593         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 594         and SETRC insns.
 595
 596 2020-04-29  Nick Clifton  <nickc@redhat.com>
 597
 598         * po/sv.po: Updated Swedish translation.
 599
 600 2020-04-29  Nick Clifton  <nickc@redhat.com>
 601
 602         PR 22699
 603         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 604         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 605         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 606         IMM0_8U case.
 607
 608 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 609
 610         PR 25848
 611         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 612         cmpi only on m68020up and cpu32.
 613
 614 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 615
 616         * aarch64-asm.c (aarch64_ins_none): New.
 617         * aarch64-asm.h (ins_none): New declaration.
 618         * aarch64-dis.c (aarch64_ext_none): New.
 619         * aarch64-dis.h (ext_none): New declaration.
 620         * aarch64-opc.c (aarch64_print_operand): Update case for
 621         AARCH64_OPND_BARRIER_PSB.
 622         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 623         (AARCH64_OPERANDS): Update inserter/extracter for
 624         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 625         * aarch64-asm-2.c: Regenerated.
 626         * aarch64-dis-2.c: Regenerated.
 627         * aarch64-opc-2.c: Regenerated.
 628
 629 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 630
 631         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 632         (aarch64_feature_ras, RAS): Likewise.
 633         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 634         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 635         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 636         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 637         * aarch64-asm-2.c: Regenerated.
 638         * aarch64-dis-2.c: Regenerated.
 639         * aarch64-opc-2.c: Regenerated.
 640
 641 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 642
 643         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 644         (print_insn_neon): Support disassembly of conditional
 645         instructions.
 646
 647 2020-02-16  David Faust  <david.faust@oracle.com>
 648
 649         * bpf-desc.c: Regenerate.
 650         * bpf-desc.h: Likewise.
 651         * bpf-opc.c: Regenerate.
 652         * bpf-opc.h: Likewise.
 653
 654 2020-04-07  Lili Cui  <lili.cui@intel.com>
 655
 656         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 657         (prefix_table): New instructions (see prefixes above).
 658         (rm_table): Likewise
 659         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 660         CPU_ANY_TSXLDTRK_FLAGS.
 661         (cpu_flags): Add CpuTSXLDTRK.
 662         * i386-opc.h (enum): Add CpuTSXLDTRK.
 663         (i386_cpu_flags): Add cputsxldtrk.
 664         * i386-opc.tbl: Add XSUSPLDTRK insns.
 665         * i386-init.h: Regenerate.
 666         * i386-tbl.h: Likewise.
 667
 668 2020-04-02  Lili Cui  <lili.cui@intel.com>
 669
 670         * i386-dis.c (prefix_table): New instructions serialize.
 671         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 672         CPU_ANY_SERIALIZE_FLAGS.
 673         (cpu_flags): Add CpuSERIALIZE.
 674         * i386-opc.h (enum): Add CpuSERIALIZE.
 675         (i386_cpu_flags): Add cpuserialize.
 676         * i386-opc.tbl: Add SERIALIZE insns.
 677         * i386-init.h: Regenerate.
 678         * i386-tbl.h: Likewise.
 679
 680 2020-03-26  Alan Modra  <amodra@gmail.com>
 681
 682         * disassemble.h (opcodes_assert): Declare.
 683         (OPCODES_ASSERT): Define.
 684         * disassemble.c: Don't include assert.h.  Include opintl.h.
 685         (opcodes_assert): New function.
 686         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 687         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 688         calculate maxlen.  Omit insn decoding when insn length exceeds
 689         maxlen.  Exit from nibble loop when looking for E, before
 690         accessing next data byte.  Move processing of E outside loop.
 691         Replace tests of maxlen in loop with assertions.
 692
 693 2020-03-26  Alan Modra  <amodra@gmail.com>
 694
 695         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 696
 697 2020-03-25  Alan Modra  <amodra@gmail.com>
 698
 699         * z80-dis.c (suffix): Init mybuf.
 700
 701 2020-03-22  Alan Modra  <amodra@gmail.com>
 702
 703         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 704         successflly read from section.
 705
 706 2020-03-22  Alan Modra  <amodra@gmail.com>
 707
 708         * arc-dis.c (find_format): Use ISO C string concatenation rather
 709         than line continuation within a string.  Don't access needs_limm
 710         before testing opcode != NULL.
 711
 712 2020-03-22  Alan Modra  <amodra@gmail.com>
 713
 714         * ns32k-dis.c (print_insn_arg): Update comment.
 715         (print_insn_ns32k): Reduce size of index_offset array, and
 716         initialize, passing -1 to print_insn_arg for args that are not
 717         an index.  Don't exit arg loop early.  Abort on bad arg number.
 718
 719 2020-03-22  Alan Modra  <amodra@gmail.com>
 720
 721         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 722         * s12z-opc.c: Formatting.
 723         (operands_f): Return an int.
 724         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 725         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 726         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 727         (exg_sex_discrim): Likewise.
 728         (create_immediate_operand, create_bitfield_operand),
 729         (create_register_operand_with_size, create_register_all_operand),
 730         (create_register_all16_operand, create_simple_memory_operand),
 731         (create_memory_operand, create_memory_auto_operand): Don't
 732         segfault on malloc failure.
 733         (z_ext24_decode): Return an int status, negative on fail, zero
 734         on success.
 735         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 736         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 737         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 738         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 739         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 740         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 741         (loop_primitive_decode, shift_decode, psh_pul_decode),
 742         (bit_field_decode): Similarly.
 743         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 744         to return value, update callers.
 745         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 746         Don't segfault on NULL operand.
 747         (decode_operation): Return OP_INVALID on first fail.
 748         (decode_s12z): Check all reads, returning -1 on fail.
 749
 750 2020-03-20  Alan Modra  <amodra@gmail.com>
 751
 752         * metag-dis.c (print_insn_metag): Don't ignore status from
 753         read_memory_func.
 754
 755 2020-03-20  Alan Modra  <amodra@gmail.com>
 756
 757         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 758         Initialize parts of buffer not written when handling a possible
 759         2-byte insn at end of section.  Don't attempt decoding of such
 760         an insn by the 4-byte machinery.
 761
 762 2020-03-20  Alan Modra  <amodra@gmail.com>
 763
 764         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 765         partially filled buffer.  Prevent lookup of 4-byte insns when
 766         only VLE 2-byte insns are possible due to section size.  Print
 767         ".word" rather than ".long" for 2-byte leftovers.
 768
 769 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 770
 771         PR 25641
 772         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 773
 774 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 775
 776         * i386-dis.c (X86_64_0D): Rename to ...
 777         (X86_64_0E): ... this.
 778
 779 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 780
 781         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 782         * Makefile.in: Regenerated.
 783
 784 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 785
 786         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 787         3-operand pseudos.
 788         * i386-tbl.h: Re-generate.
 789
 790 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 791
 792         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 793         vprot*, vpsha*, and vpshl*.
 794         * i386-tbl.h: Re-generate.
 795
 796 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 797
 798         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 799         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 800         * i386-tbl.h: Re-generate.
 801
 802 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 803
 804         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 805         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 806         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 807         * i386-tbl.h: Re-generate.
 808
 809 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 810
 811         * i386-gen.c (struct template_arg, struct template_instance,
 812         struct template_param, struct template, templates,
 813         parse_template, expand_templates): New.
 814         (process_i386_opcodes): Various local variables moved to
 815         expand_templates. Call parse_template and expand_templates.
 816         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 817         * i386-tbl.h: Re-generate.
 818
 819 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 820
 821         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 822         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 823         register and memory source templates. Replace VexW= by VexW*
 824         where applicable.
 825         * i386-tbl.h: Re-generate.
 826
 827 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 828
 829         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 830         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 831         * i386-tbl.h: Re-generate.
 832
 833 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 834
 835         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 836         * i386-tbl.h: Re-generate.
 837
 838 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 839
 840         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 841         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 842         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 843         VexW0 on SSE2AVX variants.
 844         (vmovq): Drop NoRex64 from XMM/XMM variants.
 845         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 846         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 847         applicable use VexW0.
 848         * i386-tbl.h: Re-generate.
 849
 850 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 851
 852         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 853         * i386-opc.h (Rex64): Delete.
 854         (struct i386_opcode_modifier): Remove rex64 field.
 855         * i386-opc.tbl (crc32): Drop Rex64.
 856         Replace Rex64 with Size64 everywhere else.
 857         * i386-tbl.h: Re-generate.
 858
 859 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 860
 861         * i386-dis.c (OP_E_memory): Exclude recording of used address
 862         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 863         addressed memory operands for MPX insns.
 864
 865 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 866
 867         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 868         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 869         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 870         (ptwrite): Split into non-64-bit and 64-bit forms.
 871         * i386-tbl.h: Re-generate.
 872
 873 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 874
 875         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 876         template.
 877         * i386-tbl.h: Re-generate.
 878
 879 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 880
 881         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 882         (prefix_table): Move vmmcall here. Add vmgexit.
 883         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 884         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 885         (cpu_flags): Add CpuSEV_ES entry.
 886         * i386-opc.h (CpuSEV_ES): New.
 887         (union i386_cpu_flags): Add cpusev_es field.
 888         * i386-opc.tbl (vmgexit): New.
 889         * i386-init.h, i386-tbl.h: Re-generate.
 890
 891 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 892
 893         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 894         with MnemonicSize.
 895         * i386-opc.h (IGNORESIZE): New.
 896         (DEFAULTSIZE): Likewise.
 897         (IgnoreSize): Removed.
 898         (DefaultSize): Likewise.
 899         (MnemonicSize): New.
 900         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 901         mnemonicsize.
 902         * i386-opc.tbl (IgnoreSize): New.
 903         (DefaultSize): Likewise.
 904         * i386-tbl.h: Regenerated.
 905
 906 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 907
 908         PR 25627
 909         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 910         instructions.
 911
 912 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 913
 914         PR gas/25622
 915         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 916         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 917         * i386-tbl.h: Regenerated.
 918
 919 2020-02-26  Alan Modra  <amodra@gmail.com>
 920
 921         * aarch64-asm.c: Indent labels correctly.
 922         * aarch64-dis.c: Likewise.
 923         * aarch64-gen.c: Likewise.
 924         * aarch64-opc.c: Likewise.
 925         * alpha-dis.c: Likewise.
 926         * i386-dis.c: Likewise.
 927         * nds32-asm.c: Likewise.
 928         * nfp-dis.c: Likewise.
 929         * visium-dis.c: Likewise.
 930
 931 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 932
 933         * arc-regs.h (int_vector_base): Make it available for all ARC
 934         CPUs.
 935
 936 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 937
 938         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 939         changed.
 940
 941 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 942
 943         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 944         c.mv/c.li if rs1 is zero.
 945
 946 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 947
 948         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 949         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 950         CPU_POPCNT_FLAGS.
 951         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 952         * i386-opc.h (CpuABM): Removed.
 953         (CpuPOPCNT): New.
 954         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 955         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 956         popcnt.  Remove CpuABM from lzcnt.
 957         * i386-init.h: Regenerated.
 958         * i386-tbl.h: Likewise.
 959
 960 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 961
 962         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 963         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 964         VexW1 instead of open-coding them.
 965         * i386-tbl.h: Re-generate.
 966
 967 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 968
 969         * i386-opc.tbl (AddrPrefixOpReg): Define.
 970         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 971         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 972         templates. Drop NoRex64.
 973         * i386-tbl.h: Re-generate.
 974
 975 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 976
 977         PR gas/6518
 978         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 979         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 980         into Intel syntax instance (with Unpsecified) and AT&T one
 981         (without).
 982         (vcvtneps2bf16): Likewise, along with folding the two so far
 983         separate ones.
 984         * i386-tbl.h: Re-generate.
 985
 986 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 987
 988         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 989         CPU_ANY_SSE4A_FLAGS.
 990
 991 2020-02-17  Alan Modra  <amodra@gmail.com>
 992
 993         * i386-gen.c (cpu_flag_init): Correct last change.
 994
 995 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 996
 997         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 998         CPU_ANY_SSE4_FLAGS.
 999
1000 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
1001
1002         * i386-opc.tbl (movsx): Remove Intel syntax comments.
1003         (movzx): Likewise.
1004
1005 2020-02-14  Jan Beulich  <jbeulich@suse.com>
1006
1007         PR gas/25438
1008         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1009         destination for Cpu64-only variant.
1010         (movzx): Fold patterns.
1011         * i386-tbl.h: Re-generate.
1012
1013 2020-02-13  Jan Beulich  <jbeulich@suse.com>
1014
1015         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1016         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1017         CPU_ANY_SSE4_FLAGS entry.
1018         * i386-init.h: Re-generate.
1019
1020 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1021
1022         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1023         with Unspecified, making the present one AT&T syntax only.
1024         * i386-tbl.h: Re-generate.
1025
1026 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1027
1028         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1029         * i386-tbl.h: Re-generate.
1030
1031 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1032
1033         PR gas/24546
1034         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1035         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1036         Amd64 and Intel64 templates.
1037         (call, jmp): Likewise for far indirect variants. Dro
1038         Unspecified.
1039         * i386-tbl.h: Re-generate.
1040
1041 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1042
1043         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1044         * i386-opc.h (ShortForm): Delete.
1045         (struct i386_opcode_modifier): Remove shortform field.
1046         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1047         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1048         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1049         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1050         Drop ShortForm.
1051         * i386-tbl.h: Re-generate.
1052
1053 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1054
1055         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1056         fucompi): Drop ShortForm from operand-less templates.
1057         * i386-tbl.h: Re-generate.
1058
1059 2020-02-11  Alan Modra  <amodra@gmail.com>
1060
1061         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1062         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1063         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1064         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1065         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1066
1067 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
1068
1069         * arm-dis.c (print_insn_cde): Define 'V' parse character.
1070         (cde_opcodes): Add VCX* instructions.
1071
1072 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
1073             Matthew Malcomson  <matthew.malcomson@arm.com>
1074
1075         * arm-dis.c (struct cdeopcode32): New.
1076         (CDE_OPCODE): New macro.
1077         (cde_opcodes): New disassembly table.
1078         (regnames): New option to table.
1079         (cde_coprocs): New global variable.
1080         (print_insn_cde): New
1081         (print_insn_thumb32): Use print_insn_cde.
1082         (parse_arm_disassembler_options): Parse coprocN args.
1083
1084 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
1085
1086         PR gas/25516
1087         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1088         with ISA64.
1089         * i386-opc.h (AMD64): Removed.
1090         (Intel64): Likewose.
1091         (AMD64): New.
1092         (INTEL64): Likewise.
1093         (INTEL64ONLY): Likewise.
1094         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1095         * i386-opc.tbl (Amd64): New.
1096         (Intel64): Likewise.
1097         (Intel64Only): Likewise.
1098         Replace AMD64 with Amd64.  Update sysenter/sysenter with
1099         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
1100         * i386-tbl.h: Regenerated.
1101
1102 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
1103
1104         PR 25469
1105         * z80-dis.c: Add support for GBZ80 opcodes.
1106
1107 2020-02-04  Alan Modra  <amodra@gmail.com>
1108
1109         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1110
1111 2020-02-03  Alan Modra  <amodra@gmail.com>
1112
1113         * m32c-ibld.c: Regenerate.
1114
1115 2020-02-01  Alan Modra  <amodra@gmail.com>
1116
1117         * frv-ibld.c: Regenerate.
1118
1119 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1120
1121         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1122         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1123         (OP_E_memory): Replace xmm_mdq_mode case label by
1124         vex_scalar_w_dq_mode one.
1125         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1126
1127 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1128
1129         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1130         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1131         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1132         (intel_operand_size): Drop vex_w_dq_mode case label.
1133
1134 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
1135
1136         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1137         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1138
1139 2020-01-30  Alan Modra  <amodra@gmail.com>
1140
1141         * m32c-ibld.c: Regenerate.
1142
1143 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
1144
1145         * bpf-opc.c: Regenerate.
1146
1147 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1148
1149         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1150         (dis386): Use them to replace C2/C3 table entries.
1151         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1152         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1153         ones. Use Size64 instead of DefaultSize on Intel64 ones.
1154         * i386-tbl.h: Re-generate.
1155
1156 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1157
1158         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1159         forms.
1160         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1161         DefaultSize.
1162         * i386-tbl.h: Re-generate.
1163
1164 2020-01-30  Alan Modra  <amodra@gmail.com>
1165
1166         * tic4x-dis.c (tic4x_dp): Make unsigned.
1167
1168 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
1169             Jan Beulich  <jbeulich@suse.com>
1170
1171         PR binutils/25445
1172         * i386-dis.c (MOVSXD_Fixup): New function.
1173         (movsxd_mode): New enum.
1174         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1175         (intel_operand_size): Handle movsxd_mode.
1176         (OP_E_register): Likewise.
1177         (OP_G): Likewise.
1178         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1179         register on movsxd.  Add movsxd with 16-bit destination register
1180         for AMD64 and Intel64 ISAs.
1181         * i386-tbl.h: Regenerated.
1182
1183 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
1184
1185         PR 25403
1186         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1187         * aarch64-asm-2.c: Regenerate
1188         * aarch64-dis-2.c: Likewise.
1189         * aarch64-opc-2.c: Likewise.
1190
1191 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1192
1193         * i386-opc.tbl (sysret): Drop DefaultSize.
1194         * i386-tbl.h: Re-generate.
1195
1196 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1197
1198         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1199         Dword.
1200         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1201         * i386-tbl.h: Re-generate.
1202
1203 2020-01-20  Nick Clifton  <nickc@redhat.com>
1204
1205         * po/de.po: Updated German translation.
1206         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1207         * po/uk.po: Updated Ukranian translation.
1208
1209 2020-01-20  Alan Modra  <amodra@gmail.com>
1210
1211         * hppa-dis.c (fput_const): Remove useless cast.
1212
1213 2020-01-20  Alan Modra  <amodra@gmail.com>
1214
1215         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1216
1217 2020-01-18  Nick Clifton  <nickc@redhat.com>
1218
1219         * configure: Regenerate.
1220         * po/opcodes.pot: Regenerate.
1221
1222 2020-01-18  Nick Clifton  <nickc@redhat.com>
1223
1224         Binutils 2.34 branch created.
1225
1226 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1227
1228         * opintl.h: Fix spelling error (seperate).
1229
1230 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1231
1232         * i386-opc.tbl: Add {vex} pseudo prefix.
1233         * i386-tbl.h: Regenerated.
1234
1235 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1236
1237         PR 25376
1238         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1239         (neon_opcodes): Likewise.
1240         (select_arm_features): Make sure we enable MVE bits when selecting
1241         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1242         any architecture.
1243
1244 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1245
1246         * i386-opc.tbl: Drop stale comment from XOP section.
1247
1248 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1249
1250         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1251         (extractps): Add VexWIG to SSE2AVX forms.
1252         * i386-tbl.h: Re-generate.
1253
1254 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1255
1256         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1257         Size64 from and use VexW1 on SSE2AVX forms.
1258         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1259         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1260         * i386-tbl.h: Re-generate.
1261
1262 2020-01-15  Alan Modra  <amodra@gmail.com>
1263
1264         * tic4x-dis.c (tic4x_version): Make unsigned long.
1265         (optab, optab_special, registernames): New file scope vars.
1266         (tic4x_print_register): Set up registernames rather than
1267         malloc'd registertable.
1268         (tic4x_disassemble): Delete optable and optable_special.  Use
1269         optab and optab_special instead.  Throw away old optab,
1270         optab_special and registernames when info->mach changes.
1271
1272 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1273
1274         PR 25377
1275         * z80-dis.c (suffix): Use .db instruction to generate double
1276         prefix.
1277
1278 2020-01-14  Alan Modra  <amodra@gmail.com>
1279
1280         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1281         values to unsigned before shifting.
1282
1283 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1284
1285         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1286         flow instructions.
1287         (print_insn_thumb16, print_insn_thumb32): Likewise.
1288         (print_insn): Initialize the insn info.
1289         * i386-dis.c (print_insn): Initialize the insn info fields, and
1290         detect jumps.
1291
1292 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1293
1294         * arc-opc.c (C_NE): Make it required.
1295
1296 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1297
1298         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1299         reserved register name.
1300
1301 2020-01-13  Alan Modra  <amodra@gmail.com>
1302
1303         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1304         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1305
1306 2020-01-13  Alan Modra  <amodra@gmail.com>
1307
1308         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1309         result of wasm_read_leb128 in a uint64_t and check that bits
1310         are not lost when copying to other locals.  Use uint32_t for
1311         most locals.  Use PRId64 when printing int64_t.
1312
1313 2020-01-13  Alan Modra  <amodra@gmail.com>
1314
1315         * score-dis.c: Formatting.
1316         * score7-dis.c: Formatting.
1317
1318 2020-01-13  Alan Modra  <amodra@gmail.com>
1319
1320         * score-dis.c (print_insn_score48): Use unsigned variables for
1321         unsigned values.  Don't left shift negative values.
1322         (print_insn_score32): Likewise.
1323         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1324
1325 2020-01-13  Alan Modra  <amodra@gmail.com>
1326
1327         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1328
1329 2020-01-13  Alan Modra  <amodra@gmail.com>
1330
1331         * fr30-ibld.c: Regenerate.
1332
1333 2020-01-13  Alan Modra  <amodra@gmail.com>
1334
1335         * xgate-dis.c (print_insn): Don't left shift signed value.
1336         (ripBits): Formatting, use 1u.
1337
1338 2020-01-10  Alan Modra  <amodra@gmail.com>
1339
1340         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1341         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1342
1343 2020-01-10  Alan Modra  <amodra@gmail.com>
1344
1345         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1346         and XRREG value earlier to avoid a shift with negative exponent.
1347         * m10200-dis.c (disassemble): Similarly.
1348
1349 2020-01-09  Nick Clifton  <nickc@redhat.com>
1350
1351         PR 25224
1352         * z80-dis.c (ld_ii_ii): Use correct cast.
1353
1354 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1355
1356         PR 25224
1357         * z80-dis.c (ld_ii_ii): Use character constant when checking
1358         opcode byte value.
1359
1360 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1361
1362         * i386-dis.c (SEP_Fixup): New.
1363         (SEP): Define.
1364         (dis386_twobyte): Use it for sysenter/sysexit.
1365         (enum x86_64_isa): Change amd64 enumerator to value 1.
1366         (OP_J): Compare isa64 against intel64 instead of amd64.
1367         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1368         forms.
1369         * i386-tbl.h: Re-generate.
1370
1371 2020-01-08  Alan Modra  <amodra@gmail.com>
1372
1373         * z8k-dis.c: Include libiberty.h
1374         (instr_data_s): Make max_fetched unsigned.
1375         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1376         Don't exceed byte_info bounds.
1377         (output_instr): Make num_bytes unsigned.
1378         (unpack_instr): Likewise for nibl_count and loop.
1379         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1380         idx unsigned.
1381         * z8k-opc.h: Regenerate.
1382
1383 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1384
1385         * arc-tbl.h (llock): Use 'LLOCK' as class.
1386         (llockd): Likewise.
1387         (scond): Use 'SCOND' as class.
1388         (scondd): Likewise.
1389         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1390         (scondd): Likewise.
1391
1392 2020-01-06  Alan Modra  <amodra@gmail.com>
1393
1394         * m32c-ibld.c: Regenerate.
1395
1396 2020-01-06  Alan Modra  <amodra@gmail.com>
1397
1398         PR 25344
1399         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1400         Peek at next byte to prevent recursion on repeated prefix bytes.
1401         Ensure uninitialised "mybuf" is not accessed.
1402         (print_insn_z80): Don't zero n_fetch and n_used here,..
1403         (print_insn_z80_buf): ..do it here instead.
1404
1405 2020-01-04  Alan Modra  <amodra@gmail.com>
1406
1407         * m32r-ibld.c: Regenerate.
1408
1409 2020-01-04  Alan Modra  <amodra@gmail.com>
1410
1411         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1412
1413 2020-01-04  Alan Modra  <amodra@gmail.com>
1414
1415         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1416
1417 2020-01-04  Alan Modra  <amodra@gmail.com>
1418
1419         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1420
1421 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1422
1423         * aarch64-tbl.h (aarch64_opcode_table): Use
1424         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1425
1426 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1427
1428         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1429         forms of SUDOT and USDOT.
1430
1431 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1432
1433         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1434         uzip{1,2}.
1435         * opcodes/aarch64-dis-2.c: Re-generate.
1436
1437 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1438
1439         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1440         FMMLA encoding.
1441         * opcodes/aarch64-dis-2.c: Re-generate.
1442
1443 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1444
1445         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1446
1447 2020-01-01  Alan Modra  <amodra@gmail.com>
1448
1449         Update year range in copyright notice of all files.
1450
1451 For older changes see ChangeLog-2019
1452 \f
1453 Copyright (C) 2020 Free Software Foundation, Inc.
1454
1455 Copying and distribution of this file, with or without modification,
1456 are permitted in any medium without royalty provided the copyright
1457 notice and this notice are preserved.
1458
1459 Local Variables:
1460 mode: change-log
1461 left-margin: 8
1462 fill-column: 74
1463 version-control: never
1464 End: