opcodes/ChangeLog

   1 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
   2
   3         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
   4         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
   5         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
   6         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
   7         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
   8         * aarch64-opc.c (fields): Add corresponding entries here.
   9         (operand_general_constraint_met_p): Check that SVE register lists
  10         have the correct length.  Check the ranges of SVE index registers.
  11         Check for cases where p8-p15 are used in 3-bit predicate fields.
  12         (aarch64_print_operand): Handle the new SVE operands.
  13         * aarch64-opc-2.c: Regenerate.
  14         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
  15         * aarch64-asm.c (aarch64_ins_sve_index): New function.
  16         (aarch64_ins_sve_reglist): Likewise.
  17         * aarch64-asm-2.c: Regenerate.
  18         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
  19         * aarch64-dis.c (aarch64_ext_sve_index): New function.
  20         (aarch64_ext_sve_reglist): Likewise.
  21         * aarch64-dis-2.c: Regenerate.
  22
  23 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  24
  25         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
  26         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
  27         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
  28         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
  29         tied operands.
  30
  31 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  32
  33         * aarch64-opc.c (get_offset_int_reg_name): New function.
  34         (print_immediate_offset_address): Likewise.
  35         (print_register_offset_address): Take the base and offset
  36         registers as parameters.
  37         (aarch64_print_operand): Update caller accordingly.  Use
  38         print_immediate_offset_address.
  39
  40 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  41
  42         * aarch64-opc.c (BANK): New macro.
  43         (R32, R64): Take a register number as argument
  44         (int_reg): Use BANK.
  45
  46 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  47
  48         * aarch64-opc.c (print_register_list): Add a prefix parameter.
  49         (aarch64_print_operand): Update accordingly.
  50
  51 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  52
  53         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
  54         for FPIMM.
  55         * aarch64-asm.h (ins_fpimm): New inserter.
  56         * aarch64-asm.c (aarch64_ins_fpimm): New function.
  57         * aarch64-asm-2.c: Regenerate.
  58         * aarch64-dis.h (ext_fpimm): New extractor.
  59         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
  60         (aarch64_ext_fpimm): New function.
  61         * aarch64-dis-2.c: Regenerate.
  62
  63 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  64
  65         * aarch64-asm.c: Include libiberty.h.
  66         (insert_fields): New function.
  67         (aarch64_ins_imm): Use it.
  68         * aarch64-dis.c (extract_fields): New function.
  69         (aarch64_ext_imm): Use it.
  70
  71 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  72
  73         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
  74         with an esize parameter.
  75         (operand_general_constraint_met_p): Update accordingly.
  76         Fix misindented code.
  77         * aarch64-asm.c (aarch64_ins_limm): Update call to
  78         aarch64_logical_immediate_p.
  79
  80 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  81
  82         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
  83
  84 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  85
  86         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
  87
  88 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
  89
  90         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
  91
  92 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
  93
  94         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
  95         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
  96         xor3>: Delete mnemonics.
  97         <cp_abort>: Rename mnemonic from ...
  98         <cpabort>: ...to this.
  99         <setb>: Change to a X form instruction.
 100         <sync>: Change to 1 operand form.
 101         <copy>: Delete mnemonic.
 102         <copy_first>: Rename mnemonic from ...
 103         <copy>: ...to this.
 104         <paste, paste.>: Delete mnemonics.
 105         <paste_last>: Rename mnemonic from ...
 106         <paste.>: ...to this.
 107
 108 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 109
 110         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 111
 112 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 113
 114         * s390-mkopc.c (main): Support alternate arch strings.
 115
 116 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 117
 118         * s390-opc.txt: Fix kmctr instruction type.
 119
 120 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 121
 122         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 123         * i386-init.h: Regenerated.
 124
 125 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 126
 127         * opcodes/arc-dis.c (print_insn_arc): Changed.
 128
 129 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 130
 131         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 132         camellia_fl.
 133
 134 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 135
 136         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 137         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 138         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 139
 140 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 141
 142         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 143         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 144         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 145         PREFIX_MOD_3_0FAE_REG_4.
 146         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 147         PREFIX_MOD_3_0FAE_REG_4.
 148         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 149         (cpu_flags): Add CpuPTWRITE.
 150         * i386-opc.h (CpuPTWRITE): New.
 151         (i386_cpu_flags): Add cpuptwrite.
 152         * i386-opc.tbl: Add ptwrite instruction.
 153         * i386-init.h: Regenerated.
 154         * i386-tbl.h: Likewise.
 155
 156 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 157
 158         * arc-dis.h: Wrap around in extern "C".
 159
 160 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 161
 162         * aarch64-tbl.h (V8_2_INSN): New macro.
 163         (aarch64_opcode_table): Use it.
 164
 165 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 166
 167         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 168         CORE_INSN, __FP_INSN and SIMD_INSN.
 169
 170 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 171
 172         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 173         (aarch64_opcode_table): Update uses accordingly.
 174
 175 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 176         Kwok Cheung Yeung  <kcy@codesourcery.com>
 177
 178         opcodes/
 179         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 180         'e_cmplwi' to 'e_cmpli' instead.
 181         (OPVUPRT, OPVUPRT_MASK): Define.
 182         (powerpc_opcodes): Add E200Z4 insns.
 183         (vle_opcodes): Add context save/restore insns.
 184
 185 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 186
 187         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 188         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 189         "j".
 190
 191 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 192
 193         * arc-nps400-tbl.h: Change block comments to GNU format.
 194         * arc-dis.c: Add new globals addrtypenames,
 195         addrtypenames_max, and addtypeunknown.
 196         (get_addrtype): New function.
 197         (print_insn_arc): Print colons and address types when
 198         required.
 199         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 200         define insert and extract functions for all address types.
 201         (arc_operands): Add operands for colon and all address
 202         types.
 203         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 204         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 205         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 206         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 207         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 208         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 209
 210 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 211
 212         * configure: Regenerated.
 213
 214 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 215
 216         * arc-dis.c (skipclass): New structure.
 217         (decodelist): New variable.
 218         (is_compatible_p): New function.
 219         (new_element): Likewise.
 220         (skip_class_p): Likewise.
 221         (find_format_from_table): Use skip_class_p function.
 222         (find_format): Decode first the extension instructions.
 223         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 224         e_flags.
 225         (parse_option): New function.
 226         (parse_disassembler_options): Likewise.
 227         (print_arc_disassembler_options): Likewise.
 228         (print_insn_arc): Use parse_disassembler_options function.  Proper
 229         select ARCv2 cpu variant.
 230         * disassemble.c (disassembler_usage): Add ARC disassembler
 231         options.
 232
 233 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 234
 235         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 236         annotation from the "nal" entry and reorder it beyond "bltzal".
 237
 238 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 239
 240         * sparc-opc.c (ldtxa): New macro.
 241         (sparc_opcodes): Use the macro defined above to add entries for
 242         the LDTXA instructions.
 243         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 244         instruction.
 245
 246 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 247
 248         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 249         and "jmpc".
 250
 251 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 252
 253         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 254         (movzb): Adjust to cover all permitted suffixes.
 255         (movzw): New.
 256         * i386-tbl.h: Re-generate.
 257
 258 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 259
 260         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 261         (lgdt): Remove Tbyte from non-64-bit variant.
 262         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 263         xsaves64, xsavec64): Remove Disp16.
 264         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 265         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 266         64-bit variants.
 267         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 268         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 269         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 270         64-bit variants.
 271         * i386-tbl.h: Re-generate.
 272
 273 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 274
 275         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 276         * i386-tbl.h: Re-generate.
 277
 278 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 279
 280         * arm-dis.c (print_insn): Fix typo in comment.
 281
 282 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 283
 284         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 285         range of ldst_elemlist operands.
 286         (print_register_list): Use PRIi64 to print the index.
 287         (aarch64_print_operand): Likewise.
 288
 289 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 290
 291         * mcore-opc.h: Remove sentinal.
 292         * mcore-dis.c (print_insn_mcore): Adjust.
 293
 294 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 295
 296         * arc-opc.c: Correct description of availability of NPS400
 297         features.
 298
 299 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 300
 301         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 302         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 303         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 304         xor3>: New mnemonics.
 305         <setb>: Change to a VX form instruction.
 306         (insert_sh6): Add support for rldixor.
 307         (extract_sh6): Likewise.
 308
 309 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 310
 311         * arc-ext.h: Wrap in extern C.
 312
 313 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 314
 315         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 316         Use same method for determining instruction length on ARC700 and
 317         NPS-400.
 318         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 319         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 320         with the NPS400 subclass.
 321         * arc-opc.c: Likewise.
 322
 323 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 324
 325         * sparc-opc.c (rdasr): New macro.
 326         (wrasr): Likewise.
 327         (rdpr): Likewise.
 328         (wrpr): Likewise.
 329         (rdhpr): Likewise.
 330         (wrhpr): Likewise.
 331         (sparc_opcodes): Use the macros above to fix and expand the
 332         definition of read/write instructions from/to
 333         asr/privileged/hyperprivileged instructions.
 334         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 335         %hva_mask_nz.  Prefer softint_set and softint_clear over
 336         set_softint and clear_softint.
 337         (print_insn_sparc): Support %ver in Rd.
 338
 339 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 340
 341         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 342         architecture according to the hardware capabilities they require.
 343
 344 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 345
 346         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 347         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 348         bfd_mach_sparc_v9{c,d,e,v,m}.
 349         * sparc-opc.c (MASK_V9C): Define.
 350         (MASK_V9D): Likewise.
 351         (MASK_V9E): Likewise.
 352         (MASK_V9V): Likewise.
 353         (MASK_V9M): Likewise.
 354         (v6): Add MASK_V9{C,D,E,V,M}.
 355         (v6notlet): Likewise.
 356         (v7): Likewise.
 357         (v8): Likewise.
 358         (v9): Likewise.
 359         (v9andleon): Likewise.
 360         (v9a): Likewise.
 361         (v9b): Likewise.
 362         (v9c): Define.
 363         (v9d): Likewise.
 364         (v9e): Likewise.
 365         (v9v): Likewise.
 366         (v9m): Likewise.
 367         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 368
 369 2016-06-15  Nick Clifton  <nickc@redhat.com>
 370
 371         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 372         constants to match expected behaviour.
 373         (nds32_parse_opcode): Likewise.  Also for whitespace.
 374
 375 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 376
 377         * arc-opc.c (extract_rhv1): Extract value from insn.
 378
 379 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 380
 381         * arc-nps400-tbl.h: Add ldbit instruction.
 382         * arc-opc.c: Add flag classes required for ldbit.
 383
 384 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 385
 386         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 387         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 388         support the above instructions.
 389
 390 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 391
 392         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 393         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 394         csma, cbba, zncv, and hofs.
 395         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 396         support the above instructions.
 397
 398 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 399
 400         * arc-nps400-tbl.h: Add andab and orab instructions.
 401
 402 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 403
 404         * arc-nps400-tbl.h: Add addl-like instructions.
 405
 406 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 407
 408         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 409
 410 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 411
 412         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 413         instructions.
 414
 415 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 416
 417         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 418         variable.
 419         (init_disasm): Handle new command line option "insnlength".
 420         (print_s390_disassembler_options): Mention new option in help
 421         output.
 422         (print_insn_s390): Use the encoded insn length when dumping
 423         unknown instructions.
 424
 425 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 426
 427         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 428          to the address and set as symbol address for LDS/ STS immediate operands.
 429
 430 2016-06-07  Alan Modra  <amodra@gmail.com>
 431
 432         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 433         cpu for "vle" to e500.
 434         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 435         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 436         (PPCNONE): Delete, substitute throughout.
 437         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 438         except for major opcode 4 and 31.
 439         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 440
 441 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 442
 443         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 444         ARM_EXT_RAS in relevant entries.
 445
 446 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 447
 448         PR binutils/20196
 449         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 450         opcodes for E6500.
 451
 452 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 453
 454         PR binutis/18386
 455         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 456         (indir_v_mode): New.
 457         Add comments for '&'.
 458         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 459         (putop): Handle '&'.
 460         (intel_operand_size): Handle indir_v_mode.
 461         (OP_E_register): Likewise.
 462         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 463         64-bit indirect call/jmp for AMD64.
 464         * i386-tbl.h: Regenerated
 465
 466 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 467
 468         * arc-dis.c (struct arc_operand_iterator): New structure.
 469         (find_format_from_table): All the old content from find_format,
 470         with some minor adjustments, and parameter renaming.
 471         (find_format_long_instructions): New function.
 472         (find_format): Rewritten.
 473         (arc_insn_length): Add LSB parameter.
 474         (extract_operand_value): New function.
 475         (operand_iterator_next): New function.
 476         (print_insn_arc): Use new functions to find opcode, and iterator
 477         over operands.
 478         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 479         (extract_nps_3bit_dst_short): New function.
 480         (insert_nps_3bit_src2_short): New function.
 481         (extract_nps_3bit_src2_short): New function.
 482         (insert_nps_bitop1_size): New function.
 483         (extract_nps_bitop1_size): New function.
 484         (insert_nps_bitop2_size): New function.
 485         (extract_nps_bitop2_size): New function.
 486         (insert_nps_bitop_mod4_msb): New function.
 487         (extract_nps_bitop_mod4_msb): New function.
 488         (insert_nps_bitop_mod4_lsb): New function.
 489         (extract_nps_bitop_mod4_lsb): New function.
 490         (insert_nps_bitop_dst_pos3_pos4): New function.
 491         (extract_nps_bitop_dst_pos3_pos4): New function.
 492         (insert_nps_bitop_ins_ext): New function.
 493         (extract_nps_bitop_ins_ext): New function.
 494         (arc_operands): Add new operands.
 495         (arc_long_opcodes): New global array.
 496         (arc_num_long_opcodes): New global.
 497         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 498
 499 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 500
 501         * nds32-asm.h: Add extern "C".
 502         * sh-opc.h: Likewise.
 503
 504 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 505
 506         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 507         0,b,limm to the rflt instruction.
 508
 509 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 510
 511         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 512         constant.
 513
 514 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 515
 516         PR gas/20145
 517         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 518         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 519         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 520         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 521         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 522         * i386-init.h: Regenerated.
 523
 524 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 525
 526         PR gas/20145
 527         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 528         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 529         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 530         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 531         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 532         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 533         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 534         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 535         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 536         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 537         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 538         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 539         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 540         CpuRegMask for AVX512.
 541         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 542         and CpuRegMask.
 543         (set_bitfield_from_cpu_flag_init): New function.
 544         (set_bitfield): Remove const on f.  Call
 545         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 546         * i386-opc.h (CpuRegMMX): New.
 547         (CpuRegXMM): Likewise.
 548         (CpuRegYMM): Likewise.
 549         (CpuRegZMM): Likewise.
 550         (CpuRegMask): Likewise.
 551         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 552         and cpuregmask.
 553         * i386-init.h: Regenerated.
 554         * i386-tbl.h: Likewise.
 555
 556 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 557
 558         PR gas/20154
 559         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 560         (opcode_modifiers): Add AMD64 and Intel64.
 561         (main): Properly verify CpuMax.
 562         * i386-opc.h (CpuAMD64): Removed.
 563         (CpuIntel64): Likewise.
 564         (CpuMax): Set to CpuNo64.
 565         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 566         (AMD64): New.
 567         (Intel64): Likewise.
 568         (i386_opcode_modifier): Add amd64 and intel64.
 569         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 570         on call and jmp.
 571         * i386-init.h: Regenerated.
 572         * i386-tbl.h: Likewise.
 573
 574 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 575
 576         PR gas/20154
 577         * i386-gen.c (main): Fail if CpuMax is incorrect.
 578         * i386-opc.h (CpuMax): Set to CpuIntel64.
 579         * i386-tbl.h: Regenerated.
 580
 581 2016-05-27  Nick Clifton  <nickc@redhat.com>
 582
 583         PR target/20150
 584         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 585         (msp430dis_opcode_unsigned): New function.
 586         (msp430dis_opcode_signed): New function.
 587         (msp430_singleoperand): Use the new opcode reading functions.
 588         Only disassenmble bytes if they were successfully read.
 589         (msp430_doubleoperand): Likewise.
 590         (msp430_branchinstr): Likewise.
 591         (msp430x_callx_instr): Likewise.
 592         (print_insn_msp430): Check that it is safe to read bytes before
 593         attempting disassembly.  Use the new opcode reading functions.
 594
 595 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 596
 597         * ppc-opc.c (CY): New define.  Document it.
 598         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 599
 600 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 601
 602         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 603         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 604         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 605         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 606         CPU_ANY_AVX_FLAGS.
 607         * i386-init.h: Regenerated.
 608
 609 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 610
 611         PR gas/20141
 612         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 613         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 614         * i386-init.h: Regenerated.
 615
 616 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 617
 618         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 619         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 620         * i386-init.h: Regenerated.
 621
 622 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 623
 624         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 625         information.
 626         (print_insn_arc): Set insn_type information.
 627         * arc-opc.c (C_CC): Add F_CLASS_COND.
 628         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 629         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 630         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 631         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 632         (brne, brne_s, jeq_s, jne_s): Likewise.
 633
 634 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 635
 636         * arc-tbl.h (neg): New instruction variant.
 637
 638 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 639
 640         * arc-dis.c (find_format, find_format, get_auxreg)
 641         (print_insn_arc): Changed.
 642         * arc-ext.h (INSERT_XOP): Likewise.
 643
 644 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 645
 646         * tic54x-dis.c (sprint_mmr): Adjust.
 647         * tic54x-opc.c: Likewise.
 648
 649 2016-05-19  Alan Modra  <amodra@gmail.com>
 650
 651         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 652
 653 2016-05-19  Alan Modra  <amodra@gmail.com>
 654
 655         * ppc-opc.c: Formatting.
 656         (NSISIGNOPT): Define.
 657         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 658
 659 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 660
 661         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 662         replacing references to `micromips_ase' throughout.
 663         (_print_insn_mips): Don't use file-level microMIPS annotation to
 664         determine the disassembly mode with the symbol table.
 665
 666 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 667
 668         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 669
 670 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 671
 672         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 673         mips64r6.
 674         * mips-opc.c (D34): New macro.
 675         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 676
 677 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 678
 679         * i386-dis.c (prefix_table): Add RDPID instruction.
 680         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 681         (cpu_flags): Add RDPID bitfield.
 682         * i386-opc.h (enum): Add RDPID element.
 683         (i386_cpu_flags): Add RDPID field.
 684         * i386-opc.tbl: Add RDPID instruction.
 685         * i386-init.h: Regenerate.
 686         * i386-tbl.h: Regenerate.
 687
 688 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 689
 690         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 691         branch type of a symbol.
 692         (print_insn): Likewise.
 693
 694 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 695
 696         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 697         Mainline Security Extensions instructions.
 698         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 699         Extensions instructions.
 700         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 701         instructions.
 702         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 703         special registers.
 704
 705 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 706
 707         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 708
 709 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 710
 711         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 712         (arcExtMap_genOpcode): Likewise.
 713         * arc-opc.c (arg_32bit_rc): Define new variable.
 714         (arg_32bit_u6): Likewise.
 715         (arg_32bit_limm): Likewise.
 716
 717 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 718
 719         * aarch64-gen.c (VERIFIER): Define.
 720         * aarch64-opc.c (VERIFIER): Define.
 721         (verify_ldpsw): Use static linkage.
 722         * aarch64-opc.h (verify_ldpsw): Remove.
 723         * aarch64-tbl.h: Use VERIFIER for verifiers.
 724
 725 2016-04-28  Nick Clifton  <nickc@redhat.com>
 726
 727         PR target/19722
 728         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 729         * aarch64-opc.c (verify_ldpsw): New function.
 730         * aarch64-opc.h (verify_ldpsw): New prototype.
 731         * aarch64-tbl.h: Add initialiser for verifier field.
 732         (LDPSW): Set verifier to verify_ldpsw.
 733
 734 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 735
 736         PR binutils/19983
 737         PR binutils/19984
 738         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 739         smaller than address size.
 740
 741 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 742
 743         * alpha-dis.c: Regenerate.
 744         * crx-dis.c: Likewise.
 745         * disassemble.c: Likewise.
 746         * epiphany-opc.c: Likewise.
 747         * fr30-opc.c: Likewise.
 748         * frv-opc.c: Likewise.
 749         * ip2k-opc.c: Likewise.
 750         * iq2000-opc.c: Likewise.
 751         * lm32-opc.c: Likewise.
 752         * lm32-opinst.c: Likewise.
 753         * m32c-opc.c: Likewise.
 754         * m32r-opc.c: Likewise.
 755         * m32r-opinst.c: Likewise.
 756         * mep-opc.c: Likewise.
 757         * mt-opc.c: Likewise.
 758         * or1k-opc.c: Likewise.
 759         * or1k-opinst.c: Likewise.
 760         * tic80-opc.c: Likewise.
 761         * xc16x-opc.c: Likewise.
 762         * xstormy16-opc.c: Likewise.
 763
 764 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 765
 766         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 767         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 768         calcsd, and calcxd instructions.
 769         * arc-opc.c (insert_nps_bitop_size): Delete.
 770         (extract_nps_bitop_size): Delete.
 771         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 772         (extract_nps_qcmp_m3): Define.
 773         (extract_nps_qcmp_m2): Define.
 774         (extract_nps_qcmp_m1): Define.
 775         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 776         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 777         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 778         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 779         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 780         NPS_QCMP_M3.
 781
 782 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 783
 784         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 785
 786 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 787
 788         * Makefile.in: Regenerated with automake 1.11.6.
 789         * aclocal.m4: Likewise.
 790
 791 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 792
 793         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 794         instructions.
 795         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 796         (extract_nps_cmem_uimm16): New function.
 797         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 798
 799 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 800
 801         * arc-dis.c (arc_insn_length): New function.
 802         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 803         (find_format): Change insnLen parameter to unsigned.
 804
 805 2016-04-13  Nick Clifton  <nickc@redhat.com>
 806
 807         PR target/19937
 808         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 809         the LD.B and LD.BU instructions.
 810
 811 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 812
 813         * arc-dis.c (find_format): Check for extension flags.
 814         (print_flags): New function.
 815         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 816         .extAuxRegister.
 817         * arc-ext.c (arcExtMap_coreRegName): Use
 818         LAST_EXTENSION_CORE_REGISTER.
 819         (arcExtMap_coreReadWrite): Likewise.
 820         (dump_ARC_extmap): Update printing.
 821         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 822         (arc_aux_regs): Add cpu field.
 823         * arc-regs.h: Add cpu field, lower case name aux registers.
 824
 825 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 826
 827         * arc-tbl.h: Add rtsc, sleep with no arguments.
 828
 829 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 830
 831         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 832         Initialize.
 833         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 834         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 835         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 836         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 837         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 838         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 839         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 840         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 841         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 842         (arc_opcode arc_opcodes): Null terminate the array.
 843         (arc_num_opcodes): Remove.
 844         * arc-ext.h (INSERT_XOP): Define.
 845         (extInstruction_t): Likewise.
 846         (arcExtMap_instName): Delete.
 847         (arcExtMap_insn): New function.
 848         (arcExtMap_genOpcode): Likewise.
 849         * arc-ext.c (ExtInstruction): Remove.
 850         (create_map): Zero initialize instruction fields.
 851         (arcExtMap_instName): Remove.
 852         (arcExtMap_insn): New function.
 853         (dump_ARC_extmap): More info while debuging.
 854         (arcExtMap_genOpcode): New function.
 855         * arc-dis.c (find_format): New function.
 856         (print_insn_arc): Use find_format.
 857         (arc_get_disassembler): Enable dump_ARC_extmap only when
 858         debugging.
 859
 860 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 861
 862         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 863         instruction bits out.
 864
 865 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 866
 867         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 868         * arc-opc.c (arc_flag_operands): Add new flags.
 869         (arc_flag_classes): Add new classes.
 870
 871 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 872
 873         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 874
 875 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 876
 877         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 878         encode1, rflt, crc16, and crc32 instructions.
 879         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 880         (arc_flag_classes): Add C_NPS_R.
 881         (insert_nps_bitop_size_2b): New function.
 882         (extract_nps_bitop_size_2b): Likewise.
 883         (insert_nps_bitop_uimm8): Likewise.
 884         (extract_nps_bitop_uimm8): Likewise.
 885         (arc_operands): Add new operand entries.
 886
 887 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 888
 889         * arc-regs.h: Add a new subclass field.  Add double assist
 890         accumulator register values.
 891         * arc-tbl.h: Use DPA subclass to mark the double assist
 892         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 893         * arc-opc.c (RSP): Define instead of SP.
 894         (arc_aux_regs): Add the subclass field.
 895
 896 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 897
 898         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 899
 900 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 901
 902         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 903         NPS_R_SRC1.
 904
 905 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 906
 907         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 908         issues.  No functional changes.
 909
 910 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 911
 912         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 913         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
 914         (RTT): Remove duplicate.
 915         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
 916         (PCT_CONFIG*): Remove.
 917         (D1L, D1H, D2H, D2L): Define.
 918
 919 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 920
 921         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 922
 923 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 924
 925         * arc-tbl.h (invld07): Remove.
 926         * arc-ext-tbl.h: New file.
 927         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
 928         * arc-opc.c (arc_opcodes): Add ext-tbl include.
 929
 930 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 931
 932         Fix -Wstack-usage warnings.
 933         * aarch64-dis.c (print_operands): Substitute size.
 934         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
 935
 936 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 937
 938         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
 939         to get a proper diagnostic when an invalid ASR register is used.
 940
 941 2016-03-22  Nick Clifton  <nickc@redhat.com>
 942
 943         * configure: Regenerate.
 944
 945 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 946
 947         * arc-nps400-tbl.h: New file.
 948         * arc-opc.c: Add top level comment.
 949         (insert_nps_3bit_dst): New function.
 950         (extract_nps_3bit_dst): New function.
 951         (insert_nps_3bit_src2): New function.
 952         (extract_nps_3bit_src2): New function.
 953         (insert_nps_bitop_size): New function.
 954         (extract_nps_bitop_size): New function.
 955         (arc_flag_operands): Add nps400 entries.
 956         (arc_flag_classes): Add nps400 entries.
 957         (arc_operands): Add nps400 entries.
 958         (arc_opcodes): Add nps400 include.
 959
 960 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 961
 962         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
 963         the new class enum values.
 964
 965 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 966
 967         * arc-dis.c (print_insn_arc): Handle nps400.
 968
 969 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 970
 971         * arc-opc.c (BASE): Delete.
 972
 973 2016-03-18  Nick Clifton  <nickc@redhat.com>
 974
 975         PR target/19721
 976         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
 977         of MOV insn that aliases an ORR insn.
 978
 979 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
 980
 981         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
 982
 983 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 984
 985         * mcore-opc.h: Add const qualifiers.
 986         * microblaze-opc.h (struct op_code_struct): Likewise.
 987         * sh-opc.h: Likewise.
 988         * tic4x-dis.c (tic4x_print_indirect): Likewise.
 989         (tic4x_print_op): Likewise.
 990
 991 2016-03-02  Alan Modra  <amodra@gmail.com>
 992
 993         * or1k-desc.h: Regenerate.
 994         * fr30-ibld.c: Regenerate.
 995         * rl78-decode.c: Regenerate.
 996
 997 2016-03-01  Nick Clifton  <nickc@redhat.com>
 998
 999         PR target/19747
1000         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1001
1002 2016-02-24  Renlin Li  <renlin.li@arm.com>
1003
1004         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1005         (print_insn_coprocessor): Support fp16 instructions.
1006
1007 2016-02-24  Renlin Li  <renlin.li@arm.com>
1008
1009         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1010         vminnm, vrint(mpna).
1011
1012 2016-02-24  Renlin Li  <renlin.li@arm.com>
1013
1014         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1015         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1016
1017 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1018
1019         * i386-dis.c (print_insn): Parenthesize expression to prevent
1020         truncated addresses.
1021         (OP_J): Likewise.
1022
1023 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1024             Janek van Oirschot  <jvanoirs@synopsys.com>
1025
1026         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1027         variable.
1028
1029 2016-02-04  Nick Clifton  <nickc@redhat.com>
1030
1031         PR target/19561
1032         * msp430-dis.c (print_insn_msp430): Add a special case for
1033         decoding an RRC instruction with the ZC bit set in the extension
1034         word.
1035
1036 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1037
1038         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1039         * epiphany-ibld.c: Regenerate.
1040         * fr30-ibld.c: Regenerate.
1041         * frv-ibld.c: Regenerate.
1042         * ip2k-ibld.c: Regenerate.
1043         * iq2000-ibld.c: Regenerate.
1044         * lm32-ibld.c: Regenerate.
1045         * m32c-ibld.c: Regenerate.
1046         * m32r-ibld.c: Regenerate.
1047         * mep-ibld.c: Regenerate.
1048         * mt-ibld.c: Regenerate.
1049         * or1k-ibld.c: Regenerate.
1050         * xc16x-ibld.c: Regenerate.
1051         * xstormy16-ibld.c: Regenerate.
1052
1053 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1054
1055         * epiphany-dis.c: Regenerated from latest cpu files.
1056
1057 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1058
1059         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1060         test bit.
1061
1062 2016-01-25  Renlin Li  <renlin.li@arm.com>
1063
1064         * arm-dis.c (mapping_symbol_for_insn): New function.
1065         (find_ifthen_state): Call mapping_symbol_for_insn().
1066
1067 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1068
1069         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1070         of MSR UAO immediate operand.
1071
1072 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1073
1074         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1075         instruction support.
1076
1077 2016-01-17  Alan Modra  <amodra@gmail.com>
1078
1079         * configure: Regenerate.
1080
1081 2016-01-14  Nick Clifton  <nickc@redhat.com>
1082
1083         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1084         instructions that can support stack pointer operations.
1085         * rl78-decode.c: Regenerate.
1086         * rl78-dis.c: Fix display of stack pointer in MOVW based
1087         instructions.
1088
1089 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1090
1091         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1092         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1093         erxtatus_el1 and erxaddr_el1.
1094
1095 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1096
1097         * arm-dis.c (arm_opcodes): Add "esb".
1098         (thumb_opcodes): Likewise.
1099
1100 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1101
1102         * ppc-opc.c <xscmpnedp>: Delete.
1103         <xvcmpnedp>: Likewise.
1104         <xvcmpnedp.>: Likewise.
1105         <xvcmpnesp>: Likewise.
1106         <xvcmpnesp.>: Likewise.
1107
1108 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1109
1110         PR gas/13050
1111         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1112         addition to ISA_A.
1113
1114 2016-01-01  Alan Modra  <amodra@gmail.com>
1115
1116         Update year range in copyright notice of all files.
1117
1118 For older changes see ChangeLog-2015
1119 \f
1120 Copyright (C) 2016 Free Software Foundation, Inc.
1121
1122 Copying and distribution of this file, with or without modification,
1123 are permitted in any medium without royalty provided the copyright
1124 notice and this notice are preserved.
1125
1126 Local Variables:
1127 mode: change-log
1128 left-margin: 8
1129 fill-column: 74
1130 version-control: never
1131 End: