Regenerate cgen files
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
1 2005-02-22 Alan Modra <amodra@bigpond.net.au>
2
3 * fr30-desc.c: Regenerate.
4 * fr30-desc.h: Regenerate.
5 * fr30-opc.c: Regenerate.
6 * fr30-opc.h: Regenerate.
7 * frv-desc.c: Regenerate.
8 * frv-desc.h: Regenerate.
9 * frv-opc.c: Regenerate.
10 * frv-opc.h: Regenerate.
11 * ip2k-desc.c: Regenerate.
12 * ip2k-desc.h: Regenerate.
13 * ip2k-opc.c: Regenerate.
14 * ip2k-opc.h: Regenerate.
15 * iq2000-desc.c: Regenerate.
16 * iq2000-desc.h: Regenerate.
17 * iq2000-opc.c: Regenerate.
18 * iq2000-opc.h: Regenerate.
19 * m32r-desc.c: Regenerate.
20 * m32r-desc.h: Regenerate.
21 * m32r-opc.c: Regenerate.
22 * m32r-opc.h: Regenerate.
23 * m32r-opinst.c: Regenerate.
24 * openrisc-desc.c: Regenerate.
25 * openrisc-desc.h: Regenerate.
26 * openrisc-opc.c: Regenerate.
27 * openrisc-opc.h: Regenerate.
28 * xstormy16-desc.c: Regenerate.
29 * xstormy16-desc.h: Regenerate.
30 * xstormy16-opc.c: Regenerate.
31 * xstormy16-opc.h: Regenerate.
32
33 2005-02-21 Alan Modra <amodra@bigpond.net.au>
34
35 * Makefile.am: Run "make dep-am"
36 * Makefile.in: Regenerate.
37
38 2005-02-15 Nick Clifton <nickc@redhat.com>
39
40 * cgen-dis.in (print_address): Add an ATTRIBUTE_UNUSED to prevent
41 compile time warnings.
42 (print_keyword): Likewise.
43 (default_print_insn): Likewise.
44
45 * fr30-desc.c: Regenerated.
46 * fr30-desc.h: Regenerated.
47 * fr30-dis.c: Regenerated.
48 * fr30-opc.c: Regenerated.
49 * fr30-opc.h: Regenerated.
50 * frv-desc.c: Regenerated.
51 * frv-dis.c: Regenerated.
52 * frv-opc.c: Regenerated.
53 * ip2k-asm.c: Regenerated.
54 * ip2k-desc.c: Regenerated.
55 * ip2k-desc.h: Regenerated.
56 * ip2k-dis.c: Regenerated.
57 * ip2k-opc.c: Regenerated.
58 * ip2k-opc.h: Regenerated.
59 * iq2000-desc.c: Regenerated.
60 * iq2000-dis.c: Regenerated.
61 * iq2000-opc.c: Regenerated.
62 * m32r-asm.c: Regenerated.
63 * m32r-desc.c: Regenerated.
64 * m32r-desc.h: Regenerated.
65 * m32r-dis.c: Regenerated.
66 * m32r-opc.c: Regenerated.
67 * m32r-opc.h: Regenerated.
68 * m32r-opinst.c: Regenerated.
69 * openrisc-desc.c: Regenerated.
70 * openrisc-desc.h: Regenerated.
71 * openrisc-dis.c: Regenerated.
72 * openrisc-opc.c: Regenerated.
73 * openrisc-opc.h: Regenerated.
74 * xstormy16-desc.c: Regenerated.
75 * xstormy16-desc.h: Regenerated.
76 * xstormy16-dis.c: Regenerated.
77 * xstormy16-opc.c: Regenerated.
78 * xstormy16-opc.h: Regenerated.
79
80 2005-02-14 H.J. Lu <hongjiu.lu@intel.com>
81
82 * dis-buf.c (perror_memory): Use sprintf_vma to print out
83 address.
84
85 2005-02-11 Nick Clifton <nickc@redhat.com>
86
87 * iq2000-asm.c: Regenerate.
88
89 * frv-dis.c: Regenerate.
90
91 2005-02-07 Jim Blandy <jimb@redhat.com>
92
93 * Makefile.am (CGEN): Load guile.scm before calling the main
94 application script.
95 * Makefile.in: Regenerated.
96 * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
97 Simply pass the cgen-opc.scm path to ${cgen} as its first
98 argument; ${cgen} itself now contains the '-s', or whatever is
99 appropriate for the Scheme being used.
100
101 2005-01-31 Andrew Cagney <cagney@gnu.org>
102
103 * configure: Regenerate to track ../gettext.m4.
104
105 2005-01-31 Jan Beulich <jbeulich@novell.com>
106
107 * ia64-gen.c (NELEMS): Define.
108 (shrink): Generate alias with missing second predicate register when
109 opcode has two outputs and these are both predicates.
110 * ia64-opc-i.c (FULL17): Define.
111 (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
112 here to generate output template.
113 (TBITCM, TNATCM): Undefine after use.
114 * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
115 first input. Add ld16 aliases without ar.csd as second output. Add
116 st16 aliases without ar.csd as second input. Add cmpxchg aliases
117 without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
118 ar.ccv as third/fourth inputs. Consolidate through...
119 (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
120 CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
121 * ia64-asmtab.c: Regenerate.
122
123 2005-01-27 Andrew Cagney <cagney@gnu.org>
124
125 * configure: Regenerate to track ../gettext.m4 change.
126
127 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
128
129 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
130 * frv-asm.c: Rebuilt.
131 * frv-desc.c: Rebuilt.
132 * frv-desc.h: Rebuilt.
133 * frv-dis.c: Rebuilt.
134 * frv-ibld.c: Rebuilt.
135 * frv-opc.c: Rebuilt.
136 * frv-opc.h: Rebuilt.
137
138 2005-01-24 Andrew Cagney <cagney@gnu.org>
139
140 * configure: Regenerate, ../gettext.m4 was updated.
141
142 2005-01-21 Fred Fish <fnf@specifixinc.com>
143
144 * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
145 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
146 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
147 * mips-dis.c: Ditto.
148
149 2005-01-20 Alan Modra <amodra@bigpond.net.au>
150
151 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
152
153 2005-01-19 Fred Fish <fnf@specifixinc.com>
154
155 * mips-dis.c (no_aliases): New disassembly option flag.
156 (set_default_mips_dis_options): Init no_aliases to zero.
157 (parse_mips_dis_option): Handle no-aliases option.
158 (print_insn_mips): Ignore table entries that are aliases
159 if no_aliases is set.
160 (print_insn_mips16): Ditto.
161 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
162 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
163 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
164 * mips16-opc.c (mips16_opcodes): Ditto.
165
166 2005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
167
168 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
169 (inheritance diagram): Add missing edge.
170 (arch_sh1_up): Rename arch_sh_up to match external name to make life
171 easier for the testsuite.
172 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
173 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
174 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
175 arch_sh2a_or_sh4_up child.
176 (sh_table): Do renaming as above.
177 Correct comment for ldc.l for gas testsuite to read.
178 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
179 Correct comments for movy.w and movy.l for gas testsuite to read.
180 Correct comments for fmov.d and fmov.s for gas testsuite to read.
181
182 2005-01-12 H.J. Lu <hongjiu.lu@intel.com>
183
184 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
185
186 2005-01-12 H.J. Lu <hongjiu.lu@intel.com>
187
188 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
189
190 2005-01-10 Andreas Schwab <schwab@suse.de>
191
192 * disassemble.c (disassemble_init_for_target) <case
193 bfd_arch_ia64>: Set skip_zeroes to 16.
194 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
195
196 2004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
197
198 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
199
200 2004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
201
202 * avr-dis.c: Prettyprint. Added printing of symbol names in all
203 memory references. Convert avr_operand() to C90 formatting.
204
205 2004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
206
207 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
208
209 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
210
211 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
212 (no_op_insn): Initialize array with instructions that have no
213 operands.
214 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
215
216 2004-11-29 Richard Earnshaw <rearnsha@arm.com>
217
218 * arm-dis.c: Correct top-level comment.
219
220 2004-11-27 Richard Earnshaw <rearnsha@arm.com>
221
222 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
223 architecuture defining the insn.
224 (arm_opcodes, thumb_opcodes): Delete. Move to ...
225 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
226 field.
227 Also include opcode/arm.h.
228 * Makefile.am (arm-dis.lo): Update dependency list.
229 * Makefile.in: Regenerate.
230
231 2004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
232
233 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
234 reflect the change to the short immediate syntax.
235
236 2004-11-19 Alan Modra <amodra@bigpond.net.au>
237
238 * or32-opc.c (debug): Warning fix.
239 * po/POTFILES.in: Regenerate.
240
241 * maxq-dis.c: Formatting.
242 (print_insn): Warning fix.
243
244 2004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
245
246 * arm-dis.c (WORD_ADDRESS): Define.
247 (print_insn): Use it. Correct big-endian end-of-section handling.
248
249 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
250 Vineet Sharma <vineets@noida.hcltech.com>
251
252 * maxq-dis.c: New file.
253 * disassemble.c (ARCH_maxq): Define.
254 (disassembler): Add 'print_insn_maxq_little' for handling maxq
255 instructions..
256 * configure.in: Add case for bfd_maxq_arch.
257 * configure: Regenerate.
258 * Makefile.am: Add support for maxq-dis.c
259 * Makefile.in: Regenerate.
260 * aclocal.m4: Regenerate.
261
262 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
263
264 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
265 mode.
266 * crx-dis.c: Likewise.
267
268 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
269
270 Generally, handle CRISv32.
271 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
272 (struct cris_disasm_data): New type.
273 (format_reg, format_hex, cris_constraint, print_flags)
274 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
275 callers changed.
276 (format_sup_reg, print_insn_crisv32_with_register_prefix)
277 (print_insn_crisv32_without_register_prefix)
278 (print_insn_crisv10_v32_with_register_prefix)
279 (print_insn_crisv10_v32_without_register_prefix)
280 (cris_parse_disassembler_options): New functions.
281 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
282 parameter. All callers changed.
283 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
284 failure.
285 (cris_constraint) <case 'Y', 'U'>: New cases.
286 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
287 for constraint 'n'.
288 (print_with_operands) <case 'Y'>: New case.
289 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
290 <case 'N', 'Y', 'Q'>: New cases.
291 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
292 (print_insn_cris_with_register_prefix)
293 (print_insn_cris_without_register_prefix): Call
294 cris_parse_disassembler_options.
295 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
296 for CRISv32 and the size of immediate operands. New v32-only
297 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
298 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
299 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
300 Change brp to be v3..v10.
301 (cris_support_regs): New vector.
302 (cris_opcodes): Update head comment. New format characters '[',
303 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
304 Add new opcodes for v32 and adjust existing opcodes to accommodate
305 differences to earlier variants.
306 (cris_cond15s): New vector.
307
308 2004-11-04 Jan Beulich <jbeulich@novell.com>
309
310 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
311 (indirEb): Remove.
312 (Mp): Use f_mode rather than none at all.
313 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
314 replaces what previously was x_mode; x_mode now means 128-bit SSE
315 operands.
316 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
317 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
318 pinsrw's second operand is Edqw.
319 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
320 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
321 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
322 mode when an operand size override is present or always suffixing.
323 More instructions will need to be added to this group.
324 (putop): Handle new macro chars 'C' (short/long suffix selector),
325 'I' (Intel mode override for following macro char), and 'J' (for
326 adding the 'l' prefix to far branches in AT&T mode). When an
327 alternative was specified in the template, honor macro character when
328 specified for Intel mode.
329 (OP_E): Handle new *_mode values. Correct pointer specifications for
330 memory operands. Consolidate output of index register.
331 (OP_G): Handle new *_mode values.
332 (OP_I): Handle const_1_mode.
333 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
334 respective opcode prefix bits have been consumed.
335 (OP_EM, OP_EX): Provide some default handling for generating pointer
336 specifications.
337
338 2004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
339
340 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
341 COP_INST macro.
342
343 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
344
345 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
346 (getregliststring): Support HI/LO and user registers.
347 * crx-opc.c (crx_instruction): Update data structure according to the
348 rearrangement done in CRX opcode header file.
349 (crx_regtab): Likewise.
350 (crx_optab): Likewise.
351 (crx_instruction): Reorder load/stor instructions, remove unsupported
352 formats.
353 support new Co-Processor instruction 'cpi'.
354
355 2004-10-27 Nick Clifton <nickc@redhat.com>
356
357 * opcodes/iq2000-asm.c: Regenerate.
358 * opcodes/iq2000-desc.c: Regenerate.
359 * opcodes/iq2000-desc.h: Regenerate.
360 * opcodes/iq2000-dis.c: Regenerate.
361 * opcodes/iq2000-ibld.c: Regenerate.
362 * opcodes/iq2000-opc.c: Regenerate.
363 * opcodes/iq2000-opc.h: Regenerate.
364
365 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
366
367 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
368 us4, us5 (respectively).
369 Remove unsupported 'popa' instruction.
370 Reverse operands order in store co-processor instructions.
371
372 2004-10-15 Alan Modra <amodra@bigpond.net.au>
373
374 * Makefile.am: Run "make dep-am"
375 * Makefile.in: Regenerate.
376
377 2004-10-12 Bob Wilson <bob.wilson@acm.org>
378
379 * xtensa-dis.c: Use ISO C90 formatting.
380
381 2004-10-09 Alan Modra <amodra@bigpond.net.au>
382
383 * ppc-opc.c: Revert 2004-09-09 change.
384
385 2004-10-07 Bob Wilson <bob.wilson@acm.org>
386
387 * xtensa-dis.c (state_names): Delete.
388 (fetch_data): Use xtensa_isa_maxlength.
389 (print_xtensa_operand): Replace operand parameter with opcode/operand
390 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
391 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
392 instruction bundles. Use xmalloc instead of malloc.
393
394 2004-10-07 David Gibson <david@gibson.dropbear.id.au>
395
396 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
397 initializers.
398
399 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
400
401 * crx-opc.c (crx_instruction): Support Co-processor insns.
402 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
403 (getregliststring): Change function to use the above enum.
404 (print_arg): Handle CO-Processor insns.
405 (crx_cinvs): Add 'b' option to invalidate the branch-target
406 cache.
407
408 2004-10-06 Aldy Hernandez <aldyh@redhat.com>
409
410 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
411 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
412 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
413 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
414 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
415
416 2004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
417
418 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
419 rather than add it.
420
421 2004-09-30 Paul Brook <paul@codesourcery.com>
422
423 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
424 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
425
426 2004-09-17 H.J. Lu <hongjiu.lu@intel.com>
427
428 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
429 (CONFIG_STATUS_DEPENDENCIES): New.
430 (Makefile): Removed.
431 (config.status): Likewise.
432 * Makefile.in: Regenerated.
433
434 2004-09-17 Alan Modra <amodra@bigpond.net.au>
435
436 * Makefile.am: Run "make dep-am".
437 * Makefile.in: Regenerate.
438 * aclocal.m4: Regenerate.
439 * configure: Regenerate.
440 * po/POTFILES.in: Regenerate.
441 * po/opcodes.pot: Regenerate.
442
443 2004-09-11 Andreas Schwab <schwab@suse.de>
444
445 * configure: Rebuild.
446
447 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
448
449 * ppc-opc.c (L): Make this field not optional.
450
451 2004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
452
453 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
454 Fix parameter to 'm[t|f]csr' insns.
455
456 2004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
457
458 * configure.in: Autoupdate to autoconf 2.59.
459 * aclocal.m4: Rebuild with aclocal 1.4p6.
460 * configure: Rebuild with autoconf 2.59.
461 * Makefile.in: Rebuild with automake 1.4p6 (picking up
462 bfd changes for autoconf 2.59 on the way).
463 * config.in: Rebuild with autoheader 2.59.
464
465 2004-08-27 Richard Sandiford <rsandifo@redhat.com>
466
467 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
468
469 2004-07-30 Michal Ludvig <mludvig@suse.cz>
470
471 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
472 (GRPPADLCK2): New define.
473 (twobyte_has_modrm): True for 0xA6.
474 (grps): GRPPADLCK2 for opcode 0xA6.
475
476 2004-07-29 Alexandre Oliva <aoliva@redhat.com>
477
478 Introduce SH2a support.
479 * sh-opc.h (arch_sh2a_base): Renumber.
480 (arch_sh2a_nofpu_base): Remove.
481 (arch_sh_base_mask): Adjust.
482 (arch_opann_mask): New.
483 (arch_sh2a, arch_sh2a_nofpu): Adjust.
484 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
485 (sh_table): Adjust whitespace.
486 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
487 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
488 instruction list throughout.
489 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
490 of arch_sh2a in instruction list throughout.
491 (arch_sh2e_up): Accomodate above changes.
492 (arch_sh2_up): Ditto.
493 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
494 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
495 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
496 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
497 * sh-opc.h (arch_sh2a_nofpu): New.
498 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
499 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
500 instruction.
501 2004-01-20 DJ Delorie <dj@redhat.com>
502 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
503 2003-12-29 DJ Delorie <dj@redhat.com>
504 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
505 sh_opcode_info, sh_table): Add sh2a support.
506 (arch_op32): New, to tag 32-bit opcodes.
507 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
508 2003-12-02 Michael Snyder <msnyder@redhat.com>
509 * sh-opc.h (arch_sh2a): Add.
510 * sh-dis.c (arch_sh2a): Handle.
511 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
512
513 2004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
514
515 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
516
517 2004-07-22 Nick Clifton <nickc@redhat.com>
518
519 PR/280
520 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
521 insns - this is done by objdump itself.
522 * h8500-dis.c (print_insn_h8500): Likewise.
523
524 2004-07-21 Jan Beulich <jbeulich@novell.com>
525
526 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
527 regardless of address size prefix in effect.
528 (ptr_reg): Size or address registers does not depend on rex64, but
529 on the presence of an address size override.
530 (OP_MMX): Use rex.x only for xmm registers.
531 (OP_EM): Use rex.z only for xmm registers.
532
533 2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
534
535 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
536 move/branch operations to the bottom so that VR5400 multimedia
537 instructions take precedence in disassembly.
538
539 2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
540
541 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
542 ISA-specific "break" encoding.
543
544 2004-07-13 Elvis Chiang <elvisfb@gmail.com>
545
546 * arm-opc.h: Fix typo in comment.
547
548 2004-07-11 Andreas Schwab <schwab@suse.de>
549
550 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
551
552 2004-07-09 Andreas Schwab <schwab@suse.de>
553
554 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
555
556 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
557
558 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
559 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
560 (crx-dis.lo): New target.
561 (crx-opc.lo): Likewise.
562 * Makefile.in: Regenerate.
563 * configure.in: Handle bfd_crx_arch.
564 * configure: Regenerate.
565 * crx-dis.c: New file.
566 * crx-opc.c: New file.
567 * disassemble.c (ARCH_crx): Define.
568 (disassembler): Handle ARCH_crx.
569
570 2004-06-29 James E Wilson <wilson@specifixinc.com>
571
572 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
573 * ia64-asmtab.c: Regnerate.
574
575 2004-06-28 Alan Modra <amodra@bigpond.net.au>
576
577 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
578 (extract_fxm): Don't test dialect.
579 (XFXFXM_MASK): Include the power4 bit.
580 (XFXM): Add p4 param.
581 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
582
583 2004-06-27 Alexandre Oliva <aoliva@redhat.com>
584
585 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
586 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
587
588 2004-06-26 Alan Modra <amodra@bigpond.net.au>
589
590 * ppc-opc.c (BH, XLBH_MASK): Define.
591 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
592
593 2004-06-24 Alan Modra <amodra@bigpond.net.au>
594
595 * i386-dis.c (x_mode): Comment.
596 (two_source_ops): File scope.
597 (float_mem): Correct fisttpll and fistpll.
598 (float_mem_mode): New table.
599 (dofloat): Use it.
600 (OP_E): Correct intel mode PTR output.
601 (ptr_reg): Use open_char and close_char.
602 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
603 operands. Set two_source_ops.
604
605 2004-06-15 Alan Modra <amodra@bigpond.net.au>
606
607 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
608 instead of _raw_size.
609
610 2004-06-08 Jakub Jelinek <jakub@redhat.com>
611
612 * ia64-gen.c (in_iclass): Handle more postinc st
613 and ld variants.
614 * ia64-asmtab.c: Rebuilt.
615
616 2004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
617
618 * s390-opc.txt: Correct architecture mask for some opcodes.
619 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
620 in the esa mode as well.
621
622 2004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
623
624 * sh-dis.c (target_arch): Make unsigned.
625 (print_insn_sh): Replace (most of) switch with a call to
626 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
627 * sh-opc.h: Redefine architecture flags values.
628 Add sh3-nommu architecture.
629 Reorganise <arch>_up macros so they make more visual sense.
630 (SH_MERGE_ARCH_SET): Define new macro.
631 (SH_VALID_BASE_ARCH_SET): Likewise.
632 (SH_VALID_MMU_ARCH_SET): Likewise.
633 (SH_VALID_CO_ARCH_SET): Likewise.
634 (SH_VALID_ARCH_SET): Likewise.
635 (SH_MERGE_ARCH_SET_VALID): Likewise.
636 (SH_ARCH_SET_HAS_FPU): Likewise.
637 (SH_ARCH_SET_HAS_DSP): Likewise.
638 (SH_ARCH_UNKNOWN_ARCH): Likewise.
639 (sh_get_arch_from_bfd_mach): Add prototype.
640 (sh_get_arch_up_from_bfd_mach): Likewise.
641 (sh_get_bfd_mach_from_arch_set): Likewise.
642 (sh_merge_bfd_arc): Likewise.
643
644 2004-05-24 Peter Barada <peter@the-baradas.com>
645
646 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
647 into new match_insn_m68k function. Loop over canidate
648 matches and select first that completely matches.
649 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
650 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
651 to verify addressing for MAC/EMAC.
652 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
653 reigster halves since 'fpu' and 'spl' look misleading.
654 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
655 * m68k-opc.c: Rearragne mac/emac cases to use longest for
656 first, tighten up match masks.
657 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
658 'size' from special case code in print_insn_m68k to
659 determine decode size of insns.
660
661 2004-05-19 Alan Modra <amodra@bigpond.net.au>
662
663 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
664 well as when -mpower4.
665
666 2004-05-13 Nick Clifton <nickc@redhat.com>
667
668 * po/fr.po: Updated French translation.
669
670 2004-05-05 Peter Barada <peter@the-baradas.com>
671
672 * m68k-dis.c(print_insn_m68k): Add new chips, use core
673 variants in arch_mask. Only set m68881/68851 for 68k chips.
674 * m68k-op.c: Switch from ColdFire chips to core variants.
675
676 2004-05-05 Alan Modra <amodra@bigpond.net.au>
677
678 PR 147.
679 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
680
681 2004-04-29 Ben Elliston <bje@au.ibm.com>
682
683 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
684 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
685
686 2004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
687
688 * sh-dis.c (print_insn_sh): Print the value in constant pool
689 as a symbol if it looks like a symbol.
690
691 2004-04-22 Peter Barada <peter@the-baradas.com>
692
693 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
694 appropriate ColdFire architectures.
695 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
696 mask addressing.
697 Add EMAC instructions, fix MAC instructions. Remove
698 macmw/macml/msacmw/msacml instructions since mask addressing now
699 supported.
700
701 2004-04-20 Jakub Jelinek <jakub@redhat.com>
702
703 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
704 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
705 suffix. Use fmov*x macros, create all 3 fpsize variants in one
706 macro. Adjust all users.
707
708 2004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
709
710 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
711 separately.
712
713 2004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
714
715 * m32r-asm.c: Regenerate.
716
717 2004-03-29 Stan Shebs <shebs@apple.com>
718
719 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
720 used.
721
722 2004-03-19 Alan Modra <amodra@bigpond.net.au>
723
724 * aclocal.m4: Regenerate.
725 * config.in: Regenerate.
726 * configure: Regenerate.
727 * po/POTFILES.in: Regenerate.
728 * po/opcodes.pot: Regenerate.
729
730 2004-03-16 Alan Modra <amodra@bigpond.net.au>
731
732 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
733 PPC_OPERANDS_GPR_0.
734 * ppc-opc.c (RA0): Define.
735 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
736 (RAOPT): Rename from RAO. Update all uses.
737 (powerpc_opcodes): Use RA0 as appropriate.
738
739 2004-03-15 Aldy Hernandez <aldyh@redhat.com>
740
741 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
742
743 2004-03-15 Alan Modra <amodra@bigpond.net.au>
744
745 * sparc-dis.c (print_insn_sparc): Update getword prototype.
746
747 2004-03-12 Michal Ludvig <mludvig@suse.cz>
748
749 * i386-dis.c (GRPPLOCK): Delete.
750 (grps): Delete GRPPLOCK entry.
751
752 2004-03-12 Alan Modra <amodra@bigpond.net.au>
753
754 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
755 (M, Mp): Use OP_M.
756 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
757 (GRPPADLCK): Define.
758 (dis386): Use NOP_Fixup on "nop".
759 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
760 (twobyte_has_modrm): Set for 0xa7.
761 (padlock_table): Delete. Move to..
762 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
763 and clflush.
764 (print_insn): Revert PADLOCK_SPECIAL code.
765 (OP_E): Delete sfence, lfence, mfence checks.
766
767 2004-03-12 Jakub Jelinek <jakub@redhat.com>
768
769 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
770 (INVLPG_Fixup): New function.
771 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
772
773 2004-03-12 Michal Ludvig <mludvig@suse.cz>
774
775 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
776 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
777 (padlock_table): New struct with PadLock instructions.
778 (print_insn): Handle PADLOCK_SPECIAL.
779
780 2004-03-12 Alan Modra <amodra@bigpond.net.au>
781
782 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
783 (OP_E): Twiddle clflush to sfence here.
784
785 2004-03-08 Nick Clifton <nickc@redhat.com>
786
787 * po/de.po: Updated German translation.
788
789 2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
790
791 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
792 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
793 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
794 accordingly.
795
796 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
797
798 * frv-asm.c: Regenerate.
799 * frv-desc.c: Regenerate.
800 * frv-desc.h: Regenerate.
801 * frv-dis.c: Regenerate.
802 * frv-ibld.c: Regenerate.
803 * frv-opc.c: Regenerate.
804 * frv-opc.h: Regenerate.
805
806 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
807
808 * frv-desc.c, frv-opc.c: Regenerate.
809
810 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
811
812 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
813
814 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
815
816 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
817 Also correct mistake in the comment.
818
819 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
820
821 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
822 ensure that double registers have even numbers.
823 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
824 that reserved instruction 0xfffd does not decode the same
825 as 0xfdfd (ftrv).
826 * sh-opc.h: Add REG_N_D nibble type and use it whereever
827 REG_N refers to a double register.
828 Add REG_N_B01 nibble type and use it instead of REG_NM
829 in ftrv.
830 Adjust the bit patterns in a few comments.
831
832 2004-02-25 Aldy Hernandez <aldyh@redhat.com>
833
834 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
835
836 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
837
838 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
839
840 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
841
842 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
843
844 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
845
846 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
847 mtivor32, mtivor33, mtivor34.
848
849 2004-02-19 Aldy Hernandez <aldyh@redhat.com>
850
851 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
852
853 2004-02-10 Petko Manolov <petkan@nucleusys.com>
854
855 * arm-opc.h Maverick accumulator register opcode fixes.
856
857 2004-02-13 Ben Elliston <bje@wasabisystems.com>
858
859 * m32r-dis.c: Regenerate.
860
861 2004-01-27 Michael Snyder <msnyder@redhat.com>
862
863 * sh-opc.h (sh_table): "fsrra", not "fssra".
864
865 2004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
866
867 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
868 contraints.
869
870 2004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
871
872 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
873
874 2004-01-19 Alan Modra <amodra@bigpond.net.au>
875
876 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
877 1. Don't print scale factor on AT&T mode when index missing.
878
879 2004-01-16 Alexandre Oliva <aoliva@redhat.com>
880
881 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
882 when loaded into XR registers.
883
884 2004-01-14 Richard Sandiford <rsandifo@redhat.com>
885
886 * frv-desc.h: Regenerate.
887 * frv-desc.c: Regenerate.
888 * frv-opc.c: Regenerate.
889
890 2004-01-13 Michael Snyder <msnyder@redhat.com>
891
892 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
893
894 2004-01-09 Paul Brook <paul@codesourcery.com>
895
896 * arm-opc.h (arm_opcodes): Move generic mcrr after known
897 specific opcodes.
898
899 2004-01-07 Daniel Jacobowitz <drow@mvista.com>
900
901 * Makefile.am (libopcodes_la_DEPENDENCIES)
902 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
903 comment about the problem.
904 * Makefile.in: Regenerate.
905
906 2004-01-06 Alexandre Oliva <aoliva@redhat.com>
907
908 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
909 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
910 cut&paste errors in shifting/truncating numerical operands.
911 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
912 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
913 (parse_uslo16): Likewise.
914 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
915 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
916 (parse_s12): Likewise.
917 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
918 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
919 (parse_uslo16): Likewise.
920 (parse_uhi16): Parse gothi and gotfuncdeschi.
921 (parse_d12): Parse got12 and gotfuncdesc12.
922 (parse_s12): Likewise.
923
924 2004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
925
926 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
927 instruction which looks similar to an 'rla' instruction.
928
929 For older changes see ChangeLog-0203
930 \f
931 Local Variables:
932 mode: change-log
933 left-margin: 8
934 fill-column: 74
935 version-control: never
936 End:
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