1 2019-12-11 Alan Modra <amodra@gmail.com>
3 * cr16-dis.c (EXTRACT, SBM): Rewrite.
4 (cr16_match_opcode): Delete duplicate bcond test.
6 2019-12-11 Alan Modra <amodra@gmail.com>
8 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
10 (MASKBITS, SIGNEXTEND): Rewrite.
11 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
12 unsigned arithmetic, instead assign result of SIGNEXTEND back
14 (fmtconst_val): Use 1u in shift expression.
16 2019-12-11 Alan Modra <amodra@gmail.com>
18 * arc-dis.c (find_format_from_table): Use ull constant when
21 2019-12-11 Alan Modra <amodra@gmail.com>
24 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
25 false when field is zero for sve_size_tsz_bhs.
27 2019-12-11 Alan Modra <amodra@gmail.com>
29 * epiphany-ibld.c: Regenerate.
31 2019-12-10 Alan Modra <amodra@gmail.com>
34 * disassemble.c (disassemble_free_target): New function.
36 2019-12-10 Alan Modra <amodra@gmail.com>
38 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
39 * disassemble.c (disassemble_init_for_target): Likewise.
40 * bpf-dis.c: Regenerate.
41 * epiphany-dis.c: Regenerate.
42 * fr30-dis.c: Regenerate.
43 * frv-dis.c: Regenerate.
44 * ip2k-dis.c: Regenerate.
45 * iq2000-dis.c: Regenerate.
46 * lm32-dis.c: Regenerate.
47 * m32c-dis.c: Regenerate.
48 * m32r-dis.c: Regenerate.
49 * mep-dis.c: Regenerate.
50 * mt-dis.c: Regenerate.
51 * or1k-dis.c: Regenerate.
52 * xc16x-dis.c: Regenerate.
53 * xstormy16-dis.c: Regenerate.
55 2019-12-10 Alan Modra <amodra@gmail.com>
57 * ppc-dis.c (private): Delete variable.
58 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
59 (powerpc_init_dialect): Don't use global private.
61 2019-12-10 Alan Modra <amodra@gmail.com>
63 * s12z-opc.c: Formatting.
65 2019-12-08 Alan Modra <amodra@gmail.com>
67 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
70 2019-12-05 Jan Beulich <jbeulich@suse.com>
72 * aarch64-tbl.h (aarch64_feature_crypto,
73 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
74 CRYPTO_V8_2_INSN): Delete.
76 2019-12-05 Alan Modra <amodra@gmail.com>
79 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
80 (struct string_buf): New.
81 (strbuf): New function.
82 (get_field): Use strbuf rather than strdup of local temp.
83 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
84 (get_field_rfsl, get_field_imm15): Likewise.
85 (get_field_rd, get_field_r1, get_field_r2): Update macros.
86 (get_field_special): Likewise. Don't strcpy spr. Formatting.
87 (print_insn_microblaze): Formatting. Init and pass string_buf to
90 2019-12-04 Jan Beulich <jbeulich@suse.com>
92 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
93 * i386-tbl.h: Re-generate.
95 2019-12-04 Jan Beulich <jbeulich@suse.com>
97 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
99 2019-12-04 Jan Beulich <jbeulich@suse.com>
101 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
103 (xbegin): Drop DefaultSize.
104 * i386-tbl.h: Re-generate.
106 2019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
108 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
109 Change the coproc CRC conditions to use the extension
110 feature set, second word, base on ARM_EXT2_CRC.
112 2019-11-14 Jan Beulich <jbeulich@suse.com>
114 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
115 * i386-tbl.h: Re-generate.
117 2019-11-14 Jan Beulich <jbeulich@suse.com>
119 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
120 JumpInterSegment, and JumpAbsolute entries.
121 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
122 JUMP_ABSOLUTE): Define.
123 (struct i386_opcode_modifier): Extend jump field to 3 bits.
124 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
126 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
127 JumpInterSegment): Define.
128 * i386-tbl.h: Re-generate.
130 2019-11-14 Jan Beulich <jbeulich@suse.com>
132 * i386-gen.c (operand_type_init): Remove
133 OPERAND_TYPE_JUMPABSOLUTE entry.
134 (opcode_modifiers): Add JumpAbsolute entry.
135 (operand_types): Remove JumpAbsolute entry.
136 * i386-opc.h (JumpAbsolute): Move between enums.
137 (struct i386_opcode_modifier): Add jumpabsolute field.
138 (union i386_operand_type): Remove jumpabsolute field.
139 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
140 * i386-init.h, i386-tbl.h: Re-generate.
142 2019-11-14 Jan Beulich <jbeulich@suse.com>
144 * i386-gen.c (opcode_modifiers): Add AnySize entry.
145 (operand_types): Remove AnySize entry.
146 * i386-opc.h (AnySize): Move between enums.
147 (struct i386_opcode_modifier): Add anysize field.
148 (OTUnused): Un-comment.
149 (union i386_operand_type): Remove anysize field.
150 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
151 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
152 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
154 * i386-tbl.h: Re-generate.
156 2019-11-12 Nelson Chu <nelson.chu@sifive.com>
158 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
159 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
160 use the floating point register (FPR).
162 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
164 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
166 (is_mve_encoding_conflict): Update cmode conflict checks for
169 2019-11-12 Jan Beulich <jbeulich@suse.com>
171 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
173 (operand_types): Remove EsSeg entry.
174 (main): Replace stale use of OTMax.
175 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
176 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
178 (OTUnused): Comment out.
179 (union i386_operand_type): Remove esseg field.
180 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
181 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
182 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
183 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
184 * i386-init.h, i386-tbl.h: Re-generate.
186 2019-11-12 Jan Beulich <jbeulich@suse.com>
188 * i386-gen.c (operand_instances): Add RegB entry.
189 * i386-opc.h (enum operand_instance): Add RegB.
190 * i386-opc.tbl (RegC, RegD, RegB): Define.
191 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
192 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
193 monitorx, mwaitx): Drop ImmExt and convert encodings
195 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
196 (edx, rdx): Add Instance=RegD.
197 (ebx, rbx): Add Instance=RegB.
198 * i386-tbl.h: Re-generate.
200 2019-11-12 Jan Beulich <jbeulich@suse.com>
202 * i386-gen.c (operand_type_init): Adjust
203 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
204 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
205 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
206 (operand_instances): New.
207 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
208 (output_operand_type): New parameter "instance". Process it.
209 (process_i386_operand_type): New local variable "instance".
210 (main): Adjust static assertions.
211 * i386-opc.h (INSTANCE_WIDTH): Define.
212 (enum operand_instance): New.
213 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
214 (union i386_operand_type): Replace acc, inoutportreg, and
215 shiftcount by instance.
216 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
217 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
219 * i386-init.h, i386-tbl.h: Re-generate.
221 2019-11-11 Jan Beulich <jbeulich@suse.com>
223 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
224 smaxp/sminp entries' "tied_operand" field to 2.
226 2019-11-11 Jan Beulich <jbeulich@suse.com>
228 * aarch64-opc.c (operand_general_constraint_met_p): Replace
229 "index" local variable by that of the already existing "num".
231 2019-11-08 H.J. Lu <hongjiu.lu@intel.com>
234 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
235 * i386-tbl.h: Regenerated.
237 2019-11-08 Jan Beulich <jbeulich@suse.com>
239 * i386-gen.c (operand_type_init): Add Class= to
240 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
241 OPERAND_TYPE_REGBND entry.
242 (operand_classes): Add RegMask and RegBND entries.
243 (operand_types): Drop RegMask and RegBND entry.
244 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
245 (RegMask, RegBND): Delete.
246 (union i386_operand_type): Remove regmask and regbnd fields.
247 * i386-opc.tbl (RegMask, RegBND): Define.
248 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
250 * i386-init.h, i386-tbl.h: Re-generate.
252 2019-11-08 Jan Beulich <jbeulich@suse.com>
254 * i386-gen.c (operand_type_init): Add Class= to
255 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
256 OPERAND_TYPE_REGZMM entries.
257 (operand_classes): Add RegMMX and RegSIMD entries.
258 (operand_types): Drop RegMMX and RegSIMD entries.
259 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
260 (RegMMX, RegSIMD): Delete.
261 (union i386_operand_type): Remove regmmx and regsimd fields.
262 * i386-opc.tbl (RegMMX): Define.
263 (RegXMM, RegYMM, RegZMM): Add Class=.
264 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
266 * i386-init.h, i386-tbl.h: Re-generate.
268 2019-11-08 Jan Beulich <jbeulich@suse.com>
270 * i386-gen.c (operand_type_init): Add Class= to
271 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
273 (operand_classes): Add RegCR, RegDR, and RegTR entries.
274 (operand_types): Drop Control, Debug, and Test entries.
275 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
276 (Control, Debug, Test): Delete.
277 (union i386_operand_type): Remove control, debug, and test
279 * i386-opc.tbl (Control, Debug, Test): Define.
280 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
281 Class=RegDR, and Test by Class=RegTR.
282 * i386-init.h, i386-tbl.h: Re-generate.
284 2019-11-08 Jan Beulich <jbeulich@suse.com>
286 * i386-gen.c (operand_type_init): Add Class= to
287 OPERAND_TYPE_SREG entry.
288 (operand_classes): Add SReg entry.
289 (operand_types): Drop SReg entry.
290 * i386-opc.h (enum operand_class): Add SReg.
292 (union i386_operand_type): Remove sreg field.
293 * i386-opc.tbl (SReg): Define.
294 * i386-reg.tbl: Replace SReg by Class=SReg.
295 * i386-init.h, i386-tbl.h: Re-generate.
297 2019-11-08 Jan Beulich <jbeulich@suse.com>
299 * i386-gen.c (operand_type_init): Add Class=. New
300 OPERAND_TYPE_ANYIMM entry.
301 (operand_classes): New.
302 (operand_types): Drop Reg entry.
303 (output_operand_type): New parameter "class". Process it.
304 (process_i386_operand_type): New local variable "class".
305 (main): Adjust static assertions.
306 * i386-opc.h (CLASS_WIDTH): Define.
307 (enum operand_class): New.
308 (Reg): Replace by Class. Adjust comment.
309 (union i386_operand_type): Replace reg by class.
310 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
312 * i386-reg.tbl: Replace Reg by Class=Reg.
313 * i386-init.h: Re-generate.
315 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
317 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
318 (aarch64_opcode_table): Add data gathering hint mnemonic.
319 * opcodes/aarch64-dis-2.c: Account for new instruction.
321 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
323 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
326 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
328 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
329 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
330 aarch64_feature_f64mm): New feature sets.
331 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
332 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
334 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
336 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
337 (OP_SVE_QQQ): New qualifier.
338 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
339 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
340 the movprfx constraint.
341 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
342 (aarch64_opcode_table): Define new instructions smmla,
343 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
345 * aarch64-opc.c (operand_general_constraint_met_p): Handle
346 AARCH64_OPND_SVE_ADDR_RI_S4x32.
347 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
348 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
349 Account for new instructions.
350 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
352 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
354 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
355 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
357 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
359 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
360 (neon_opcodes): Add bfloat SIMD instructions.
361 (print_insn_coprocessor): Add new control character %b to print
362 condition code without checking cp_num.
363 (print_insn_neon): Account for BFloat16 instructions that have no
364 special top-byte handling.
366 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
367 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
369 * arm-dis.c (print_insn_coprocessor,
370 print_insn_generic_coprocessor): Create wrapper functions around
371 the implementation of the print_insn_coprocessor control codes.
372 (print_insn_coprocessor_1): Original print_insn_coprocessor
373 function that now takes which array to look at as an argument.
374 (print_insn_arm): Use both print_insn_coprocessor and
375 print_insn_generic_coprocessor.
376 (print_insn_thumb32): As above.
378 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
379 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
381 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
382 in reglane special case.
383 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
384 aarch64_find_next_opcode): Account for new instructions.
385 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
386 in reglane special case.
387 * aarch64-opc.c (struct operand_qualifier_data): Add data for
388 new AARCH64_OPND_QLF_S_2H qualifier.
389 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
390 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
391 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
393 (BFLOAT_SVE, BFLOAT): New feature set macros.
394 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
396 (aarch64_opcode_table): Define new instructions bfdot,
397 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
400 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
401 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
403 * aarch64-tbl.h (ARMV8_6): New macro.
405 2019-11-07 Jan Beulich <jbeulich@suse.com>
407 * i386-dis.c (prefix_table): Add mcommit.
408 (rm_table): Add rdpru.
409 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
410 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
411 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
412 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
413 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
414 * i386-opc.tbl (mcommit, rdpru): New.
415 * i386-init.h, i386-tbl.h: Re-generate.
417 2019-11-07 Jan Beulich <jbeulich@suse.com>
419 * i386-dis.c (OP_Mwait): Drop local variable "names", use
421 (OP_Monitor): Drop local variable "op1_names", re-purpose
422 "names" for it instead, and replace former "names" uses by
425 2019-11-07 Jan Beulich <jbeulich@suse.com>
428 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
430 * opcodes/i386-tbl.h: Re-generate.
432 2019-11-05 Jan Beulich <jbeulich@suse.com>
434 * i386-dis.c (OP_Mwaitx): Delete.
435 (prefix_table): Use OP_Mwait for mwaitx entry.
436 (OP_Mwait): Also handle mwaitx.
438 2019-11-05 Jan Beulich <jbeulich@suse.com>
440 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
441 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
442 (prefix_table): Add respective entries.
443 (rm_table): Link to those entries.
445 2019-11-05 Jan Beulich <jbeulich@suse.com>
447 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
448 (REG_0F1C_P_0_MOD_0): ... this.
449 (REG_0F1E_MOD_3): Rename to ...
450 (REG_0F1E_P_1_MOD_3): ... this.
451 (RM_0F01_REG_5): Rename to ...
452 (RM_0F01_REG_5_MOD_3): ... this.
453 (RM_0F01_REG_7): Rename to ...
454 (RM_0F01_REG_7_MOD_3): ... this.
455 (RM_0F1E_MOD_3_REG_7): Rename to ...
456 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
457 (RM_0FAE_REG_6): Rename to ...
458 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
459 (RM_0FAE_REG_7): Rename to ...
460 (RM_0FAE_REG_7_MOD_3): ... this.
461 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
462 (PREFIX_0F01_REG_5_MOD_0): ... this.
463 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
464 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
465 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
466 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
467 (PREFIX_0FAE_REG_0): Rename to ...
468 (PREFIX_0FAE_REG_0_MOD_3): ... this.
469 (PREFIX_0FAE_REG_1): Rename to ...
470 (PREFIX_0FAE_REG_1_MOD_3): ... this.
471 (PREFIX_0FAE_REG_2): Rename to ...
472 (PREFIX_0FAE_REG_2_MOD_3): ... this.
473 (PREFIX_0FAE_REG_3): Rename to ...
474 (PREFIX_0FAE_REG_3_MOD_3): ... this.
475 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
476 (PREFIX_0FAE_REG_4_MOD_0): ... this.
477 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
478 (PREFIX_0FAE_REG_4_MOD_3): ... this.
479 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
480 (PREFIX_0FAE_REG_5_MOD_0): ... this.
481 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
482 (PREFIX_0FAE_REG_5_MOD_3): ... this.
483 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
484 (PREFIX_0FAE_REG_6_MOD_0): ... this.
485 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
486 (PREFIX_0FAE_REG_6_MOD_3): ... this.
487 (PREFIX_0FAE_REG_7): Rename to ...
488 (PREFIX_0FAE_REG_7_MOD_0): ... this.
489 (PREFIX_MOD_0_0FC3): Rename to ...
490 (PREFIX_0FC3_MOD_0): ... this.
491 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
492 (PREFIX_0FC7_REG_6_MOD_0): ... this.
493 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
494 (PREFIX_0FC7_REG_6_MOD_3): ... this.
495 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
496 (PREFIX_0FC7_REG_7_MOD_3): ... this.
497 (reg_table, prefix_table, mod_table, rm_table): Adjust
500 2019-11-04 Nick Clifton <nickc@redhat.com>
502 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
503 of a v850 system register. Move the v850_sreg_names array into
505 (get_v850_reg_name): Likewise for ordinary register names.
506 (get_v850_vreg_name): Likewise for vector register names.
507 (get_v850_cc_name): Likewise for condition codes.
508 * get_v850_float_cc_name): Likewise for floating point condition
510 (get_v850_cacheop_name): Likewise for cache-ops.
511 (get_v850_prefop_name): Likewise for pref-ops.
512 (disassemble): Use the new accessor functions.
514 2019-10-30 Delia Burduv <delia.burduv@arm.com>
516 * aarch64-opc.c (print_immediate_offset_address): Don't print the
517 immediate for the writeback form of ldraa/ldrab if it is 0.
518 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
519 * aarch64-opc-2.c: Regenerated.
521 2019-10-30 Jan Beulich <jbeulich@suse.com>
523 * i386-gen.c (operand_type_shorthands): Delete.
524 (operand_type_init): Expand previous shorthands.
525 (set_bitfield_from_shorthand): Rename back to ...
526 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
527 of operand_type_init[].
528 (set_bitfield): Adjust call to the above function.
529 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
530 RegXMM, RegYMM, RegZMM): Define.
531 * i386-reg.tbl: Expand prior shorthands.
533 2019-10-30 Jan Beulich <jbeulich@suse.com>
535 * i386-gen.c (output_i386_opcode): Change order of fields
537 * i386-opc.h (struct insn_template): Move operands field.
538 Convert extension_opcode field to unsigned short.
539 * i386-tbl.h: Re-generate.
541 2019-10-30 Jan Beulich <jbeulich@suse.com>
543 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
545 * i386-opc.h (W): Extend comment.
546 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
547 general purpose variants not allowing for byte operands.
548 * i386-tbl.h: Re-generate.
550 2019-10-29 Nick Clifton <nickc@redhat.com>
552 * tic30-dis.c (print_branch): Correct size of operand array.
554 2019-10-29 Nick Clifton <nickc@redhat.com>
556 * d30v-dis.c (print_insn): Check that operand index is valid
557 before attempting to access the operands array.
559 2019-10-29 Nick Clifton <nickc@redhat.com>
561 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
562 locating the bit to be tested.
564 2019-10-29 Nick Clifton <nickc@redhat.com>
566 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
568 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
569 (print_insn_s12z): Check for illegal size values.
571 2019-10-28 Nick Clifton <nickc@redhat.com>
573 * csky-dis.c (csky_chars_to_number): Check for a negative
574 count. Use an unsigned integer to construct the return value.
576 2019-10-28 Nick Clifton <nickc@redhat.com>
578 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
579 operand buffer. Set value to 15 not 13.
580 (get_register_operand): Use OPERAND_BUFFER_LEN.
581 (get_indirect_operand): Likewise.
582 (print_two_operand): Likewise.
583 (print_three_operand): Likewise.
584 (print_oar_insn): Likewise.
586 2019-10-28 Nick Clifton <nickc@redhat.com>
588 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
589 (bit_extract_simple): Likewise.
590 (bit_copy): Likewise.
591 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
592 index_offset array are not accessed.
594 2019-10-28 Nick Clifton <nickc@redhat.com>
596 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
599 2019-10-25 Nick Clifton <nickc@redhat.com>
601 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
602 access to opcodes.op array element.
604 2019-10-23 Nick Clifton <nickc@redhat.com>
606 * rx-dis.c (get_register_name): Fix spelling typo in error
608 (get_condition_name, get_flag_name, get_double_register_name)
609 (get_double_register_high_name, get_double_register_low_name)
610 (get_double_control_register_name, get_double_condition_name)
611 (get_opsize_name, get_size_name): Likewise.
613 2019-10-22 Nick Clifton <nickc@redhat.com>
615 * rx-dis.c (get_size_name): New function. Provides safe
616 access to name array.
617 (get_opsize_name): Likewise.
618 (print_insn_rx): Use the accessor functions.
620 2019-10-16 Nick Clifton <nickc@redhat.com>
622 * rx-dis.c (get_register_name): New function. Provides safe
623 access to name array.
624 (get_condition_name, get_flag_name, get_double_register_name)
625 (get_double_register_high_name, get_double_register_low_name)
626 (get_double_control_register_name, get_double_condition_name):
628 (print_insn_rx): Use the accessor functions.
630 2019-10-09 Nick Clifton <nickc@redhat.com>
633 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
636 2019-10-07 Jan Beulich <jbeulich@suse.com>
638 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
639 (cmpsd): Likewise. Move EsSeg to other operand.
640 * opcodes/i386-tbl.h: Re-generate.
642 2019-09-23 Alan Modra <amodra@gmail.com>
644 * m68k-dis.c: Include cpu-m68k.h
646 2019-09-23 Alan Modra <amodra@gmail.com>
648 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
649 "elf/mips.h" earlier.
651 2018-09-20 Jan Beulich <jbeulich@suse.com>
654 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
656 * i386-tbl.h: Re-generate.
658 2019-09-18 Alan Modra <amodra@gmail.com>
660 * arc-ext.c: Update throughout for bfd section macro changes.
662 2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
664 * Makefile.in: Re-generate.
665 * configure: Re-generate.
667 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
669 * riscv-opc.c (riscv_opcodes): Change subset field
670 to insn_class field for all instructions.
671 (riscv_insn_types): Likewise.
673 2019-09-16 Phil Blundell <pb@pbcl.net>
675 * configure: Regenerated.
677 2019-09-10 Miod Vallat <miod@online.fr>
680 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
682 2019-09-09 Phil Blundell <pb@pbcl.net>
684 binutils 2.33 branch created.
686 2019-09-03 Nick Clifton <nickc@redhat.com>
689 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
690 greater than zero before indexing via (bufcnt -1).
692 2019-09-03 Nick Clifton <nickc@redhat.com>
695 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
696 (MAX_SPEC_REG_NAME_LEN): Define.
697 (struct mmix_dis_info): Use defined constants for array lengths.
698 (get_reg_name): New function.
699 (get_sprec_reg_name): New function.
700 (print_insn_mmix): Use new functions.
702 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
704 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
705 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
706 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
708 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
710 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
711 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
712 (aarch64_sys_reg_supported_p): Update checks for the above.
714 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
716 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
717 cases MVE_SQRSHRL and MVE_UQRSHLL.
718 (print_insn_mve): Add case for specifier 'k' to check
719 specific bit of the instruction.
721 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
724 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
725 encountering an unknown machine type.
726 (print_insn_arc): Handle arc_insn_length returning 0. In error
727 cases return -1 rather than calling abort.
729 2019-08-07 Jan Beulich <jbeulich@suse.com>
731 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
732 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
734 * i386-tbl.h: Re-generate.
736 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
738 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
741 2019-07-30 Mel Chen <mel.chen@sifive.com>
743 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
744 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
746 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
749 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
751 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
752 and MPY class instructions.
753 (parse_option): Add nps400 option.
754 (print_arc_disassembler_options): Add nps400 info.
756 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
758 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
761 * arc-opc.c (RAD_CHK): Add.
762 * arc-tbl.h: Regenerate.
764 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
766 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
767 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
769 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
771 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
772 instructions as UNPREDICTABLE.
774 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
776 * bpf-desc.c: Regenerated.
778 2019-07-17 Jan Beulich <jbeulich@suse.com>
780 * i386-gen.c (static_assert): Define.
782 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
783 (Opcode_Modifier_Num): ... this.
786 2019-07-16 Jan Beulich <jbeulich@suse.com>
788 * i386-gen.c (operand_types): Move RegMem ...
789 (opcode_modifiers): ... here.
790 * i386-opc.h (RegMem): Move to opcode modifer enum.
791 (union i386_operand_type): Move regmem field ...
792 (struct i386_opcode_modifier): ... here.
793 * i386-opc.tbl (RegMem): Define.
794 (mov, movq): Move RegMem on segment, control, debug, and test
796 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
797 to non-SSE2AVX flavor.
798 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
799 Move RegMem on register only flavors. Drop IgnoreSize from
800 legacy encoding flavors.
801 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
803 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
804 register only flavors.
805 (vmovd): Move RegMem and drop IgnoreSize on register only
806 flavor. Change opcode and operand order to store form.
807 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
809 2019-07-16 Jan Beulich <jbeulich@suse.com>
811 * i386-gen.c (operand_type_init, operand_types): Replace SReg
813 * i386-opc.h (SReg2, SReg3): Replace by ...
815 (union i386_operand_type): Replace sreg fields.
816 * i386-opc.tbl (mov, ): Use SReg.
817 (push, pop): Likewies. Drop i386 and x86-64 specific segment
819 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
820 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
822 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
824 * bpf-desc.c: Regenerate.
825 * bpf-opc.c: Likewise.
826 * bpf-opc.h: Likewise.
828 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
830 * bpf-desc.c: Regenerate.
831 * bpf-opc.c: Likewise.
833 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
835 * arm-dis.c (print_insn_coprocessor): Rename index to
838 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
840 * riscv-opc.c (riscv_insn_types): Add r4 type.
842 * riscv-opc.c (riscv_insn_types): Add b and j type.
844 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
845 format for sb type and correct s type.
847 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
849 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
850 SVE FMOV alias of FCPY.
852 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
854 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
855 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
857 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
859 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
860 registers in an instruction prefixed by MOVPRFX.
862 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
864 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
865 sve_size_13 icode to account for variant behaviour of
867 * aarch64-dis-2.c: Regenerate.
868 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
869 sve_size_13 icode to account for variant behaviour of
871 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
872 (OP_SVE_VVV_Q_D): Add new qualifier.
873 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
874 (struct aarch64_opcode): Split pmull{t,b} into those requiring
877 2019-07-01 Jan Beulich <jbeulich@suse.com>
879 * opcodes/i386-gen.c (operand_type_init): Remove
880 OPERAND_TYPE_VEC_IMM4 entry.
881 (operand_types): Remove Vec_Imm4.
882 * opcodes/i386-opc.h (Vec_Imm4): Delete.
883 (union i386_operand_type): Remove vec_imm4.
884 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
885 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
887 2019-07-01 Jan Beulich <jbeulich@suse.com>
889 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
890 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
891 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
892 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
893 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
894 monitorx, mwaitx): Drop ImmExt from operand-less forms.
895 * i386-tbl.h: Re-generate.
897 2019-07-01 Jan Beulich <jbeulich@suse.com>
899 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
901 * i386-tbl.h: Re-generate.
903 2019-07-01 Jan Beulich <jbeulich@suse.com>
905 * i386-opc.tbl (C): New.
906 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
907 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
908 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
909 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
910 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
911 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
912 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
913 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
914 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
915 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
916 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
917 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
918 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
919 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
920 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
921 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
922 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
923 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
924 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
925 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
926 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
927 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
928 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
929 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
930 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
931 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
933 * i386-tbl.h: Re-generate.
935 2019-07-01 Jan Beulich <jbeulich@suse.com>
937 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
939 * i386-tbl.h: Re-generate.
941 2019-07-01 Jan Beulich <jbeulich@suse.com>
943 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
944 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
945 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
946 * i386-tbl.h: Re-generate.
948 2019-07-01 Jan Beulich <jbeulich@suse.com>
950 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
951 Disp8MemShift from register only templates.
952 * i386-tbl.h: Re-generate.
954 2019-07-01 Jan Beulich <jbeulich@suse.com>
956 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
957 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
958 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
959 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
960 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
961 EVEX_W_0F11_P_3_M_1): Delete.
962 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
963 EVEX_W_0F11_P_3): New.
964 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
965 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
966 MOD_EVEX_0F11_PREFIX_3 table entries.
967 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
968 PREFIX_EVEX_0F11 table entries.
969 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
970 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
971 EVEX_W_0F11_P_3_M_{0,1} table entries.
973 2019-07-01 Jan Beulich <jbeulich@suse.com>
975 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
978 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
981 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
982 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
983 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
984 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
985 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
986 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
987 EVEX_LEN_0F38C7_R_6_P_2_W_1.
988 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
989 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
990 PREFIX_EVEX_0F38C6_REG_6 entries.
991 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
992 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
993 EVEX_W_0F38C7_R_6_P_2 entries.
994 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
995 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
996 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
997 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
998 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
999 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1000 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1002 2019-06-27 Jan Beulich <jbeulich@suse.com>
1004 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1005 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1006 VEX_LEN_0F2D_P_3): Delete.
1007 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1008 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1009 (prefix_table): ... here.
1011 2019-06-27 Jan Beulich <jbeulich@suse.com>
1013 * i386-dis.c (Iq): Delete.
1015 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1017 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1018 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1019 (OP_E_memory): Also honor needindex when deciding whether an
1020 address size prefix needs printing.
1021 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1023 2019-06-26 Jim Wilson <jimw@sifive.com>
1026 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1027 Set info->display_endian to info->endian_code.
1029 2019-06-25 Jan Beulich <jbeulich@suse.com>
1031 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1032 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1033 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1034 OPERAND_TYPE_ACC64 entries.
1035 * i386-init.h: Re-generate.
1037 2019-06-25 Jan Beulich <jbeulich@suse.com>
1039 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1041 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1043 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1045 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1046 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1048 2019-06-25 Jan Beulich <jbeulich@suse.com>
1050 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1053 2019-06-25 Jan Beulich <jbeulich@suse.com>
1055 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1056 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1058 * i386-opc.tbl (movnti): Add IgnoreSize.
1059 * i386-tbl.h: Re-generate.
1061 2019-06-25 Jan Beulich <jbeulich@suse.com>
1063 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1064 * i386-tbl.h: Re-generate.
1066 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1068 * i386-dis-evex.h: Break into ...
1069 * i386-dis-evex-len.h: New file.
1070 * i386-dis-evex-mod.h: Likewise.
1071 * i386-dis-evex-prefix.h: Likewise.
1072 * i386-dis-evex-reg.h: Likewise.
1073 * i386-dis-evex-w.h: Likewise.
1074 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1075 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1076 i386-dis-evex-mod.h.
1078 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1081 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1082 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1084 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1085 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1086 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1087 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1088 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1089 EVEX_LEN_0F385B_P_2_W_1.
1090 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1091 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1092 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1093 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1094 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1095 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1096 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1097 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1098 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1099 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1101 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1104 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1105 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1106 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1107 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1108 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1109 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1110 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1111 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1112 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1113 EVEX_LEN_0F3A43_P_2_W_1.
1114 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1115 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1116 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1117 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1118 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1119 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1120 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1121 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1122 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1123 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1124 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1125 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1127 2019-06-14 Nick Clifton <nickc@redhat.com>
1129 * po/fr.po; Updated French translation.
1131 2019-06-13 Stafford Horne <shorne@gmail.com>
1133 * or1k-asm.c: Regenerated.
1134 * or1k-desc.c: Regenerated.
1135 * or1k-desc.h: Regenerated.
1136 * or1k-dis.c: Regenerated.
1137 * or1k-ibld.c: Regenerated.
1138 * or1k-opc.c: Regenerated.
1139 * or1k-opc.h: Regenerated.
1140 * or1k-opinst.c: Regenerated.
1142 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
1144 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1146 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1149 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1150 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1151 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1152 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1153 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1154 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1155 EVEX_LEN_0F3A1B_P_2_W_1.
1156 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1157 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1158 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1159 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1160 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1161 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1162 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1163 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1165 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1168 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1169 EVEX.vvvv when disassembling VEX and EVEX instructions.
1170 (OP_VEX): Set vex.register_specifier to 0 after readding
1171 vex.register_specifier.
1172 (OP_Vex_2src_1): Likewise.
1173 (OP_Vex_2src_2): Likewise.
1174 (OP_LWP_E): Likewise.
1175 (OP_EX_Vex): Don't check vex.register_specifier.
1176 (OP_XMM_Vex): Likewise.
1178 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1179 Lili Cui <lili.cui@intel.com>
1181 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1182 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1184 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1185 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1186 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1187 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1188 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1189 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1190 * i386-init.h: Regenerated.
1191 * i386-tbl.h: Likewise.
1193 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1194 Lili Cui <lili.cui@intel.com>
1196 * doc/c-i386.texi: Document enqcmd.
1197 * testsuite/gas/i386/enqcmd-intel.d: New file.
1198 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1199 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1200 * testsuite/gas/i386/enqcmd.d: Likewise.
1201 * testsuite/gas/i386/enqcmd.s: Likewise.
1202 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1203 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1204 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1205 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1206 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1207 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1208 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1211 2019-06-04 Alan Hayward <alan.hayward@arm.com>
1213 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1215 2019-06-03 Alan Modra <amodra@gmail.com>
1217 * ppc-dis.c (prefix_opcd_indices): Correct size.
1219 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1222 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1224 * i386-tbl.h: Regenerated.
1226 2019-05-24 Alan Modra <amodra@gmail.com>
1228 * po/POTFILES.in: Regenerate.
1230 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1231 Alan Modra <amodra@gmail.com>
1233 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1234 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1235 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1236 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1237 XTOP>): Define and add entries.
1238 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1239 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1240 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1241 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1243 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1244 Alan Modra <amodra@gmail.com>
1246 * ppc-dis.c (ppc_opts): Add "future" entry.
1247 (PREFIX_OPCD_SEGS): Define.
1248 (prefix_opcd_indices): New array.
1249 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1250 (lookup_prefix): New function.
1251 (print_insn_powerpc): Handle 64-bit prefix instructions.
1252 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1253 (PMRR, POWERXX): Define.
1254 (prefix_opcodes): New instruction table.
1255 (prefix_num_opcodes): New constant.
1257 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1259 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1260 * configure: Regenerated.
1261 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1263 (HFILES): Add bpf-desc.h and bpf-opc.h.
1264 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1265 bpf-ibld.c and bpf-opc.c.
1267 * Makefile.in: Regenerated.
1268 * disassemble.c (ARCH_bpf): Define.
1269 (disassembler): Add case for bfd_arch_bpf.
1270 (disassemble_init_for_target): Likewise.
1271 (enum epbf_isa_attr): Define.
1272 * disassemble.h: extern print_insn_bpf.
1273 * bpf-asm.c: Generated.
1274 * bpf-opc.h: Likewise.
1275 * bpf-opc.c: Likewise.
1276 * bpf-ibld.c: Likewise.
1277 * bpf-dis.c: Likewise.
1278 * bpf-desc.h: Likewise.
1279 * bpf-desc.c: Likewise.
1281 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1283 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1284 and VMSR with the new operands.
1286 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1288 * arm-dis.c (enum mve_instructions): New enum
1289 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1291 (mve_opcodes): New instructions as above.
1292 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1294 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1296 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1298 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1299 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1300 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1301 uqshl, urshrl and urshr.
1302 (is_mve_okay_in_it): Add new instructions to TRUE list.
1303 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1304 (print_insn_mve): Updated to accept new %j,
1305 %<bitfield>m and %<bitfield>n patterns.
1307 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1309 * mips-opc.c (mips_builtin_opcodes): Change source register
1310 constraint for DAUI.
1312 2019-05-20 Nick Clifton <nickc@redhat.com>
1314 * po/fr.po: Updated French translation.
1316 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1317 Michael Collison <michael.collison@arm.com>
1319 * arm-dis.c (thumb32_opcodes): Add new instructions.
1320 (enum mve_instructions): Likewise.
1321 (enum mve_undefined): Add new reasons.
1322 (is_mve_encoding_conflict): Handle new instructions.
1323 (is_mve_undefined): Likewise.
1324 (is_mve_unpredictable): Likewise.
1325 (print_mve_undefined): Likewise.
1326 (print_mve_size): Likewise.
1328 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1329 Michael Collison <michael.collison@arm.com>
1331 * arm-dis.c (thumb32_opcodes): Add new instructions.
1332 (enum mve_instructions): Likewise.
1333 (is_mve_encoding_conflict): Handle new instructions.
1334 (is_mve_undefined): Likewise.
1335 (is_mve_unpredictable): Likewise.
1336 (print_mve_size): Likewise.
1338 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1339 Michael Collison <michael.collison@arm.com>
1341 * arm-dis.c (thumb32_opcodes): Add new instructions.
1342 (enum mve_instructions): Likewise.
1343 (is_mve_encoding_conflict): Likewise.
1344 (is_mve_unpredictable): Likewise.
1345 (print_mve_size): Likewise.
1347 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1348 Michael Collison <michael.collison@arm.com>
1350 * arm-dis.c (thumb32_opcodes): Add new instructions.
1351 (enum mve_instructions): Likewise.
1352 (is_mve_encoding_conflict): Handle new instructions.
1353 (is_mve_undefined): Likewise.
1354 (is_mve_unpredictable): Likewise.
1355 (print_mve_size): Likewise.
1357 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1358 Michael Collison <michael.collison@arm.com>
1360 * arm-dis.c (thumb32_opcodes): Add new instructions.
1361 (enum mve_instructions): Likewise.
1362 (is_mve_encoding_conflict): Handle new instructions.
1363 (is_mve_undefined): Likewise.
1364 (is_mve_unpredictable): Likewise.
1365 (print_mve_size): Likewise.
1366 (print_insn_mve): Likewise.
1368 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1369 Michael Collison <michael.collison@arm.com>
1371 * arm-dis.c (thumb32_opcodes): Add new instructions.
1372 (print_insn_thumb32): Handle new instructions.
1374 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1375 Michael Collison <michael.collison@arm.com>
1377 * arm-dis.c (enum mve_instructions): Add new instructions.
1378 (enum mve_undefined): Add new reasons.
1379 (is_mve_encoding_conflict): Handle new instructions.
1380 (is_mve_undefined): Likewise.
1381 (is_mve_unpredictable): Likewise.
1382 (print_mve_undefined): Likewise.
1383 (print_mve_size): Likewise.
1384 (print_mve_shift_n): Likewise.
1385 (print_insn_mve): Likewise.
1387 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1388 Michael Collison <michael.collison@arm.com>
1390 * arm-dis.c (enum mve_instructions): Add new instructions.
1391 (is_mve_encoding_conflict): Handle new instructions.
1392 (is_mve_unpredictable): Likewise.
1393 (print_mve_rotate): Likewise.
1394 (print_mve_size): Likewise.
1395 (print_insn_mve): Likewise.
1397 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1398 Michael Collison <michael.collison@arm.com>
1400 * arm-dis.c (enum mve_instructions): Add new instructions.
1401 (is_mve_encoding_conflict): Handle new instructions.
1402 (is_mve_unpredictable): Likewise.
1403 (print_mve_size): Likewise.
1404 (print_insn_mve): Likewise.
1406 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1407 Michael Collison <michael.collison@arm.com>
1409 * arm-dis.c (enum mve_instructions): Add new instructions.
1410 (enum mve_undefined): Add new reasons.
1411 (is_mve_encoding_conflict): Handle new instructions.
1412 (is_mve_undefined): Likewise.
1413 (is_mve_unpredictable): Likewise.
1414 (print_mve_undefined): Likewise.
1415 (print_mve_size): Likewise.
1416 (print_insn_mve): Likewise.
1418 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1419 Michael Collison <michael.collison@arm.com>
1421 * arm-dis.c (enum mve_instructions): Add new instructions.
1422 (is_mve_encoding_conflict): Handle new instructions.
1423 (is_mve_undefined): Likewise.
1424 (is_mve_unpredictable): Likewise.
1425 (print_mve_size): Likewise.
1426 (print_insn_mve): Likewise.
1428 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1429 Michael Collison <michael.collison@arm.com>
1431 * arm-dis.c (enum mve_instructions): Add new instructions.
1432 (enum mve_unpredictable): Add new reasons.
1433 (enum mve_undefined): Likewise.
1434 (is_mve_okay_in_it): Handle new isntructions.
1435 (is_mve_encoding_conflict): Likewise.
1436 (is_mve_undefined): Likewise.
1437 (is_mve_unpredictable): Likewise.
1438 (print_mve_vmov_index): Likewise.
1439 (print_simd_imm8): Likewise.
1440 (print_mve_undefined): Likewise.
1441 (print_mve_unpredictable): Likewise.
1442 (print_mve_size): Likewise.
1443 (print_insn_mve): Likewise.
1445 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1446 Michael Collison <michael.collison@arm.com>
1448 * arm-dis.c (enum mve_instructions): Add new instructions.
1449 (enum mve_unpredictable): Add new reasons.
1450 (enum mve_undefined): Likewise.
1451 (is_mve_encoding_conflict): Handle new instructions.
1452 (is_mve_undefined): Likewise.
1453 (is_mve_unpredictable): Likewise.
1454 (print_mve_undefined): Likewise.
1455 (print_mve_unpredictable): Likewise.
1456 (print_mve_rounding_mode): Likewise.
1457 (print_mve_vcvt_size): Likewise.
1458 (print_mve_size): Likewise.
1459 (print_insn_mve): Likewise.
1461 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1462 Michael Collison <michael.collison@arm.com>
1464 * arm-dis.c (enum mve_instructions): Add new instructions.
1465 (enum mve_unpredictable): Add new reasons.
1466 (enum mve_undefined): Likewise.
1467 (is_mve_undefined): Handle new instructions.
1468 (is_mve_unpredictable): Likewise.
1469 (print_mve_undefined): Likewise.
1470 (print_mve_unpredictable): Likewise.
1471 (print_mve_size): Likewise.
1472 (print_insn_mve): Likewise.
1474 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1475 Michael Collison <michael.collison@arm.com>
1477 * arm-dis.c (enum mve_instructions): Add new instructions.
1478 (enum mve_undefined): Add new reasons.
1479 (insns): Add new instructions.
1480 (is_mve_encoding_conflict):
1481 (print_mve_vld_str_addr): New print function.
1482 (is_mve_undefined): Handle new instructions.
1483 (is_mve_unpredictable): Likewise.
1484 (print_mve_undefined): Likewise.
1485 (print_mve_size): Likewise.
1486 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1487 (print_insn_mve): Handle new operands.
1489 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1490 Michael Collison <michael.collison@arm.com>
1492 * arm-dis.c (enum mve_instructions): Add new instructions.
1493 (enum mve_unpredictable): Add new reasons.
1494 (is_mve_encoding_conflict): Handle new instructions.
1495 (is_mve_unpredictable): Likewise.
1496 (mve_opcodes): Add new instructions.
1497 (print_mve_unpredictable): Handle new reasons.
1498 (print_mve_register_blocks): New print function.
1499 (print_mve_size): Handle new instructions.
1500 (print_insn_mve): Likewise.
1502 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1503 Michael Collison <michael.collison@arm.com>
1505 * arm-dis.c (enum mve_instructions): Add new instructions.
1506 (enum mve_unpredictable): Add new reasons.
1507 (enum mve_undefined): Likewise.
1508 (is_mve_encoding_conflict): Handle new instructions.
1509 (is_mve_undefined): Likewise.
1510 (is_mve_unpredictable): Likewise.
1511 (coprocessor_opcodes): Move NEON VDUP from here...
1512 (neon_opcodes): ... to here.
1513 (mve_opcodes): Add new instructions.
1514 (print_mve_undefined): Handle new reasons.
1515 (print_mve_unpredictable): Likewise.
1516 (print_mve_size): Handle new instructions.
1517 (print_insn_neon): Handle vdup.
1518 (print_insn_mve): Handle new operands.
1520 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1521 Michael Collison <michael.collison@arm.com>
1523 * arm-dis.c (enum mve_instructions): Add new instructions.
1524 (enum mve_unpredictable): Add new values.
1525 (mve_opcodes): Add new instructions.
1526 (vec_condnames): New array with vector conditions.
1527 (mve_predicatenames): New array with predicate suffixes.
1528 (mve_vec_sizename): New array with vector sizes.
1529 (enum vpt_pred_state): New enum with vector predication states.
1530 (struct vpt_block): New struct type for vpt blocks.
1531 (vpt_block_state): Global struct to keep track of state.
1532 (mve_extract_pred_mask): New helper function.
1533 (num_instructions_vpt_block): Likewise.
1534 (mark_outside_vpt_block): Likewise.
1535 (mark_inside_vpt_block): Likewise.
1536 (invert_next_predicate_state): Likewise.
1537 (update_next_predicate_state): Likewise.
1538 (update_vpt_block_state): Likewise.
1539 (is_vpt_instruction): Likewise.
1540 (is_mve_encoding_conflict): Add entries for new instructions.
1541 (is_mve_unpredictable): Likewise.
1542 (print_mve_unpredictable): Handle new cases.
1543 (print_instruction_predicate): Likewise.
1544 (print_mve_size): New function.
1545 (print_vec_condition): New function.
1546 (print_insn_mve): Handle vpt blocks and new print operands.
1548 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1550 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1551 8, 14 and 15 for Armv8.1-M Mainline.
1553 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1554 Michael Collison <michael.collison@arm.com>
1556 * arm-dis.c (enum mve_instructions): New enum.
1557 (enum mve_unpredictable): Likewise.
1558 (enum mve_undefined): Likewise.
1559 (struct mopcode32): New struct.
1560 (is_mve_okay_in_it): New function.
1561 (is_mve_architecture): Likewise.
1562 (arm_decode_field): Likewise.
1563 (arm_decode_field_multiple): Likewise.
1564 (is_mve_encoding_conflict): Likewise.
1565 (is_mve_undefined): Likewise.
1566 (is_mve_unpredictable): Likewise.
1567 (print_mve_undefined): Likewise.
1568 (print_mve_unpredictable): Likewise.
1569 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1570 (print_insn_mve): New function.
1571 (print_insn_thumb32): Handle MVE architecture.
1572 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1574 2019-05-10 Nick Clifton <nickc@redhat.com>
1577 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1578 end of the table prematurely.
1580 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1582 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1585 2019-05-11 Alan Modra <amodra@gmail.com>
1587 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1588 when -Mraw is in effect.
1590 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1592 * aarch64-dis-2.c: Regenerate.
1593 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1594 (OP_SVE_BBB): New variant set.
1595 (OP_SVE_DDDD): New variant set.
1596 (OP_SVE_HHH): New variant set.
1597 (OP_SVE_HHHU): New variant set.
1598 (OP_SVE_SSS): New variant set.
1599 (OP_SVE_SSSU): New variant set.
1600 (OP_SVE_SHH): New variant set.
1601 (OP_SVE_SBBU): New variant set.
1602 (OP_SVE_DSS): New variant set.
1603 (OP_SVE_DHHU): New variant set.
1604 (OP_SVE_VMV_HSD_BHS): New variant set.
1605 (OP_SVE_VVU_HSD_BHS): New variant set.
1606 (OP_SVE_VVVU_SD_BH): New variant set.
1607 (OP_SVE_VVVU_BHSD): New variant set.
1608 (OP_SVE_VVV_QHD_DBS): New variant set.
1609 (OP_SVE_VVV_HSD_BHS): New variant set.
1610 (OP_SVE_VVV_HSD_BHS2): New variant set.
1611 (OP_SVE_VVV_BHS_HSD): New variant set.
1612 (OP_SVE_VV_BHS_HSD): New variant set.
1613 (OP_SVE_VVV_SD): New variant set.
1614 (OP_SVE_VVU_BHS_HSD): New variant set.
1615 (OP_SVE_VZVV_SD): New variant set.
1616 (OP_SVE_VZVV_BH): New variant set.
1617 (OP_SVE_VZV_SD): New variant set.
1618 (aarch64_opcode_table): Add sve2 instructions.
1620 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1622 * aarch64-asm-2.c: Regenerated.
1623 * aarch64-dis-2.c: Regenerated.
1624 * aarch64-opc-2.c: Regenerated.
1625 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1626 for SVE_SHLIMM_UNPRED_22.
1627 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1628 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1631 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1633 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1634 sve_size_tsz_bhs iclass encode.
1635 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1636 sve_size_tsz_bhs iclass decode.
1638 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1640 * aarch64-asm-2.c: Regenerated.
1641 * aarch64-dis-2.c: Regenerated.
1642 * aarch64-opc-2.c: Regenerated.
1643 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1644 for SVE_Zm4_11_INDEX.
1645 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1646 (fields): Handle SVE_i2h field.
1647 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1648 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1650 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1652 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1653 sve_shift_tsz_bhsd iclass encode.
1654 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1655 sve_shift_tsz_bhsd iclass decode.
1657 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1659 * aarch64-asm-2.c: Regenerated.
1660 * aarch64-dis-2.c: Regenerated.
1661 * aarch64-opc-2.c: Regenerated.
1662 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1663 (aarch64_encode_variant_using_iclass): Handle
1664 sve_shift_tsz_hsd iclass encode.
1665 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1666 sve_shift_tsz_hsd iclass decode.
1667 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1668 for SVE_SHRIMM_UNPRED_22.
1669 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1670 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1673 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1675 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1676 sve_size_013 iclass encode.
1677 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1678 sve_size_013 iclass decode.
1680 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1682 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1683 sve_size_bh iclass encode.
1684 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1685 sve_size_bh iclass decode.
1687 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1689 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1690 sve_size_sd2 iclass encode.
1691 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1692 sve_size_sd2 iclass decode.
1693 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1694 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1696 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1698 * aarch64-asm-2.c: Regenerated.
1699 * aarch64-dis-2.c: Regenerated.
1700 * aarch64-opc-2.c: Regenerated.
1701 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1703 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1704 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1706 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1708 * aarch64-asm-2.c: Regenerated.
1709 * aarch64-dis-2.c: Regenerated.
1710 * aarch64-opc-2.c: Regenerated.
1711 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1712 for SVE_Zm3_11_INDEX.
1713 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1714 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1715 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1717 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1719 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1721 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1722 sve_size_hsd2 iclass encode.
1723 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1724 sve_size_hsd2 iclass decode.
1725 * aarch64-opc.c (fields): Handle SVE_size field.
1726 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1728 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1730 * aarch64-asm-2.c: Regenerated.
1731 * aarch64-dis-2.c: Regenerated.
1732 * aarch64-opc-2.c: Regenerated.
1733 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1735 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1736 (fields): Handle SVE_rot3 field.
1737 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1738 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1740 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1742 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1745 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1748 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1749 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1750 aarch64_feature_sve2bitperm): New feature sets.
1751 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1752 for feature set addresses.
1753 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1754 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1756 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1757 Faraz Shahbazker <fshahbazker@wavecomp.com>
1759 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1760 argument and set ASE_EVA_R6 appropriately.
1761 (set_default_mips_dis_options): Pass ISA to above.
1762 (parse_mips_dis_option): Likewise.
1763 * mips-opc.c (EVAR6): New macro.
1764 (mips_builtin_opcodes): Add llwpe, scwpe.
1766 2019-05-01 Sudakshina Das <sudi.das@arm.com>
1768 * aarch64-asm-2.c: Regenerated.
1769 * aarch64-dis-2.c: Regenerated.
1770 * aarch64-opc-2.c: Regenerated.
1771 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1772 AARCH64_OPND_TME_UIMM16.
1773 (aarch64_print_operand): Likewise.
1774 * aarch64-tbl.h (QL_IMM_NIL): New.
1777 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1779 2019-04-29 John Darrington <john@darrington.wattle.id.au>
1781 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1783 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1784 Faraz Shahbazker <fshahbazker@wavecomp.com>
1786 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1788 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1790 * s12z-opc.h: Add extern "C" bracketing to help
1791 users who wish to use this interface in c++ code.
1793 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1795 * s12z-opc.c (bm_decode): Handle bit map operations with the
1798 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1800 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1801 specifier. Add entries for VLDR and VSTR of system registers.
1802 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1803 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1804 of %J and %K format specifier.
1806 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1808 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1809 Add new entries for VSCCLRM instruction.
1810 (print_insn_coprocessor): Handle new %C format control code.
1812 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1814 * arm-dis.c (enum isa): New enum.
1815 (struct sopcode32): New structure.
1816 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1817 set isa field of all current entries to ANY.
1818 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1819 Only match an entry if its isa field allows the current mode.
1821 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1823 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1825 (print_insn_thumb32): Add logic to print %n CLRM register list.
1827 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1829 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1832 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1834 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1835 (print_insn_thumb32): Edit the switch case for %Z.
1837 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1839 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1841 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1843 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1845 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1847 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1849 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1851 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1852 Arm register with r13 and r15 unpredictable.
1853 (thumb32_opcodes): New instructions for bfx and bflx.
1855 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1857 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1859 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1861 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1863 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1865 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1867 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1869 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1871 2019-04-12 John Darrington <john@darrington.wattle.id.au>
1873 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1874 "optr". ("operator" is a reserved word in c++).
1876 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1878 * aarch64-opc.c (aarch64_print_operand): Add case for
1880 (verify_constraints): Likewise.
1881 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1882 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1883 to accept Rt|SP as first operand.
1884 (AARCH64_OPERANDS): Add new Rt_SP.
1885 * aarch64-asm-2.c: Regenerated.
1886 * aarch64-dis-2.c: Regenerated.
1887 * aarch64-opc-2.c: Regenerated.
1889 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1891 * aarch64-asm-2.c: Regenerated.
1892 * aarch64-dis-2.c: Likewise.
1893 * aarch64-opc-2.c: Likewise.
1894 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1896 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1898 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1900 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1902 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1903 * i386-init.h: Regenerated.
1905 2019-04-07 Alan Modra <amodra@gmail.com>
1907 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1908 op_separator to control printing of spaces, comma and parens
1909 rather than need_comma, need_paren and spaces vars.
1911 2019-04-07 Alan Modra <amodra@gmail.com>
1914 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1915 (print_insn_neon, print_insn_arm): Likewise.
1917 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1919 * i386-dis-evex.h (evex_table): Updated to support BF16
1921 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1922 and EVEX_W_0F3872_P_3.
1923 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1924 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1925 * i386-opc.h (enum): Add CpuAVX512_BF16.
1926 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1927 * i386-opc.tbl: Add AVX512 BF16 instructions.
1928 * i386-init.h: Regenerated.
1929 * i386-tbl.h: Likewise.
1931 2019-04-05 Alan Modra <amodra@gmail.com>
1933 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1934 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1935 to favour printing of "-" branch hint when using the "y" bit.
1936 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1938 2019-04-05 Alan Modra <amodra@gmail.com>
1940 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1941 opcode until first operand is output.
1943 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1946 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1947 (valid_bo_post_v2): Add support for 'at' branch hints.
1948 (insert_bo): Only error on branch on ctr.
1949 (get_bo_hint_mask): New function.
1950 (insert_boe): Add new 'branch_taken' formal argument. Add support
1951 for inserting 'at' branch hints.
1952 (extract_boe): Add new 'branch_taken' formal argument. Add support
1953 for extracting 'at' branch hints.
1954 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1955 (BOE): Delete operand.
1956 (BOM, BOP): New operands.
1958 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1959 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1960 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1961 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1962 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1963 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1964 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1965 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1966 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1967 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1968 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1969 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1970 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1971 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1972 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1973 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1974 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1975 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1976 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1977 bttarl+>: New extended mnemonics.
1979 2019-03-28 Alan Modra <amodra@gmail.com>
1982 * ppc-opc.c (BTF): Define.
1983 (powerpc_opcodes): Use for mtfsb*.
1984 * ppc-dis.c (print_insn_powerpc): Print fields with both
1985 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1987 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1989 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1990 (mapping_symbol_for_insn): Implement new algorithm.
1991 (print_insn): Remove duplicate code.
1993 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1995 * aarch64-dis.c (print_insn_aarch64):
1998 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2000 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2003 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2005 * aarch64-dis.c (last_stop_offset): New.
2006 (print_insn_aarch64): Use stop_offset.
2008 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2011 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2013 * i386-init.h: Regenerated.
2015 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2018 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2019 vmovdqu16, vmovdqu32 and vmovdqu64.
2020 * i386-tbl.h: Regenerated.
2022 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2024 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2025 from vstrszb, vstrszh, and vstrszf.
2027 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2029 * s390-opc.txt: Add instruction descriptions.
2031 2019-02-08 Jim Wilson <jimw@sifive.com>
2033 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2036 2019-02-07 Tamar Christina <tamar.christina@arm.com>
2038 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2040 2019-02-07 Tamar Christina <tamar.christina@arm.com>
2043 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2044 * aarch64-opc.c (verify_elem_sd): New.
2045 (fields): Add FLD_sz entr.
2046 * aarch64-tbl.h (_SIMD_INSN): New.
2047 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2048 fmulx scalar and vector by element isns.
2050 2019-02-07 Nick Clifton <nickc@redhat.com>
2052 * po/sv.po: Updated Swedish translation.
2054 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2056 * s390-mkopc.c (main): Accept arch13 as cpu string.
2057 * s390-opc.c: Add new instruction formats and instruction opcode
2059 * s390-opc.txt: Add new arch13 instructions.
2061 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2063 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2064 (aarch64_opcode): Change encoding for stg, stzg
2066 * aarch64-asm-2.c: Regenerated.
2067 * aarch64-dis-2.c: Regenerated.
2068 * aarch64-opc-2.c: Regenerated.
2070 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2072 * aarch64-asm-2.c: Regenerated.
2073 * aarch64-dis-2.c: Likewise.
2074 * aarch64-opc-2.c: Likewise.
2075 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2077 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2078 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2080 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2081 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2082 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2083 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2084 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2085 case for ldstgv_indexed.
2086 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2087 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2088 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2089 * aarch64-asm-2.c: Regenerated.
2090 * aarch64-dis-2.c: Regenerated.
2091 * aarch64-opc-2.c: Regenerated.
2093 2019-01-23 Nick Clifton <nickc@redhat.com>
2095 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2097 2019-01-21 Nick Clifton <nickc@redhat.com>
2099 * po/de.po: Updated German translation.
2100 * po/uk.po: Updated Ukranian translation.
2102 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2103 * mips-dis.c (mips_arch_choices): Fix typo in
2104 gs464, gs464e and gs264e descriptors.
2106 2019-01-19 Nick Clifton <nickc@redhat.com>
2108 * configure: Regenerate.
2109 * po/opcodes.pot: Regenerate.
2111 2018-06-24 Nick Clifton <nickc@redhat.com>
2113 2.32 branch created.
2115 2019-01-09 John Darrington <john@darrington.wattle.id.au>
2117 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2119 -dis.c (opr_emit_disassembly): Do not omit an index if it is
2122 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2124 * configure: Regenerate.
2126 2019-01-07 Alan Modra <amodra@gmail.com>
2128 * configure: Regenerate.
2129 * po/POTFILES.in: Regenerate.
2131 2019-01-03 John Darrington <john@darrington.wattle.id.au>
2133 * s12z-opc.c: New file.
2134 * s12z-opc.h: New file.
2135 * s12z-dis.c: Removed all code not directly related to display
2136 of instructions. Used the interface provided by the new files
2138 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2139 * Makefile.in: Regenerate.
2140 * configure.ac (bfd_s12z_arch): Correct the dependencies.
2141 * configure: Regenerate.
2143 2019-01-01 Alan Modra <amodra@gmail.com>
2145 Update year range in copyright notice of all files.
2147 For older changes see ChangeLog-2018
2149 Copyright (C) 2019 Free Software Foundation, Inc.
2151 Copying and distribution of this file, with or without modification,
2152 are permitted in any medium without royalty provided the copyright
2153 notice and this notice are preserved.
2159 version-control: never