1 2019-06-27 Jan Beulich <jbeulich@suse.com>
3 * i386-dis.c (Iq): Delete.
5 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
7 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
8 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
9 (OP_E_memory): Also honor needindex when deciding whether an
10 address size prefix needs printing.
11 (OP_I): Remove handling of q_mode. Add handling of d_mode.
13 2019-06-26 Jim Wilson <jimw@sifive.com>
16 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
17 Set info->display_endian to info->endian_code.
19 2019-06-25 Jan Beulich <jbeulich@suse.com>
21 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
22 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
23 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
24 OPERAND_TYPE_ACC64 entries.
25 * i386-init.h: Re-generate.
27 2019-06-25 Jan Beulich <jbeulich@suse.com>
29 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
31 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
33 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
35 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
36 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
38 2019-06-25 Jan Beulich <jbeulich@suse.com>
40 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
43 2019-06-25 Jan Beulich <jbeulich@suse.com>
45 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
46 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
48 * i386-opc.tbl (movnti): Add IgnoreSize.
49 * i386-tbl.h: Re-generate.
51 2019-06-25 Jan Beulich <jbeulich@suse.com>
53 * i386-opc.tbl (and): Mark Imm8S form for optimization.
54 * i386-tbl.h: Re-generate.
56 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
58 * i386-dis-evex.h: Break into ...
59 * i386-dis-evex-len.h: New file.
60 * i386-dis-evex-mod.h: Likewise.
61 * i386-dis-evex-prefix.h: Likewise.
62 * i386-dis-evex-reg.h: Likewise.
63 * i386-dis-evex-w.h: Likewise.
64 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
65 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
68 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
71 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
72 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
74 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
75 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
76 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
77 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
78 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
79 EVEX_LEN_0F385B_P_2_W_1.
80 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
81 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
82 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
83 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
84 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
85 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
86 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
87 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
88 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
89 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
91 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
94 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
95 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
96 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
97 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
98 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
99 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
100 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
101 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
102 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
103 EVEX_LEN_0F3A43_P_2_W_1.
104 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
105 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
106 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
107 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
108 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
109 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
110 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
111 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
112 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
113 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
114 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
115 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
117 2019-06-14 Nick Clifton <nickc@redhat.com>
119 * po/fr.po; Updated French translation.
121 2019-06-13 Stafford Horne <shorne@gmail.com>
123 * or1k-asm.c: Regenerated.
124 * or1k-desc.c: Regenerated.
125 * or1k-desc.h: Regenerated.
126 * or1k-dis.c: Regenerated.
127 * or1k-ibld.c: Regenerated.
128 * or1k-opc.c: Regenerated.
129 * or1k-opc.h: Regenerated.
130 * or1k-opinst.c: Regenerated.
132 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
134 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
136 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
139 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
140 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
141 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
142 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
143 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
144 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
145 EVEX_LEN_0F3A1B_P_2_W_1.
146 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
147 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
148 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
149 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
150 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
151 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
152 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
153 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
155 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
158 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
159 EVEX.vvvv when disassembling VEX and EVEX instructions.
160 (OP_VEX): Set vex.register_specifier to 0 after readding
161 vex.register_specifier.
162 (OP_Vex_2src_1): Likewise.
163 (OP_Vex_2src_2): Likewise.
164 (OP_LWP_E): Likewise.
165 (OP_EX_Vex): Don't check vex.register_specifier.
166 (OP_XMM_Vex): Likewise.
168 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
169 Lili Cui <lili.cui@intel.com>
171 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
172 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
174 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
175 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
176 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
177 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
178 (i386_cpu_flags): Add cpuavx512_vp2intersect.
179 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
180 * i386-init.h: Regenerated.
181 * i386-tbl.h: Likewise.
183 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
184 Lili Cui <lili.cui@intel.com>
186 * doc/c-i386.texi: Document enqcmd.
187 * testsuite/gas/i386/enqcmd-intel.d: New file.
188 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
189 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
190 * testsuite/gas/i386/enqcmd.d: Likewise.
191 * testsuite/gas/i386/enqcmd.s: Likewise.
192 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
193 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
194 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
195 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
196 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
197 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
198 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
201 2019-06-04 Alan Hayward <alan.hayward@arm.com>
203 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
205 2019-06-03 Alan Modra <amodra@gmail.com>
207 * ppc-dis.c (prefix_opcd_indices): Correct size.
209 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
212 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
214 * i386-tbl.h: Regenerated.
216 2019-05-24 Alan Modra <amodra@gmail.com>
218 * po/POTFILES.in: Regenerate.
220 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
221 Alan Modra <amodra@gmail.com>
223 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
224 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
225 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
226 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
227 XTOP>): Define and add entries.
228 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
229 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
230 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
231 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
233 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
234 Alan Modra <amodra@gmail.com>
236 * ppc-dis.c (ppc_opts): Add "future" entry.
237 (PREFIX_OPCD_SEGS): Define.
238 (prefix_opcd_indices): New array.
239 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
240 (lookup_prefix): New function.
241 (print_insn_powerpc): Handle 64-bit prefix instructions.
242 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
243 (PMRR, POWERXX): Define.
244 (prefix_opcodes): New instruction table.
245 (prefix_num_opcodes): New constant.
247 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
249 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
250 * configure: Regenerated.
251 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
253 (HFILES): Add bpf-desc.h and bpf-opc.h.
254 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
255 bpf-ibld.c and bpf-opc.c.
257 * Makefile.in: Regenerated.
258 * disassemble.c (ARCH_bpf): Define.
259 (disassembler): Add case for bfd_arch_bpf.
260 (disassemble_init_for_target): Likewise.
261 (enum epbf_isa_attr): Define.
262 * disassemble.h: extern print_insn_bpf.
263 * bpf-asm.c: Generated.
264 * bpf-opc.h: Likewise.
265 * bpf-opc.c: Likewise.
266 * bpf-ibld.c: Likewise.
267 * bpf-dis.c: Likewise.
268 * bpf-desc.h: Likewise.
269 * bpf-desc.c: Likewise.
271 2019-05-21 Sudakshina Das <sudi.das@arm.com>
273 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
274 and VMSR with the new operands.
276 2019-05-21 Sudakshina Das <sudi.das@arm.com>
278 * arm-dis.c (enum mve_instructions): New enum
279 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
281 (mve_opcodes): New instructions as above.
282 (is_mve_encoding_conflict): Add cases for csinc, csinv,
284 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
286 2019-05-21 Sudakshina Das <sudi.das@arm.com>
288 * arm-dis.c (emun mve_instructions): Updated for new instructions.
289 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
290 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
291 uqshl, urshrl and urshr.
292 (is_mve_okay_in_it): Add new instructions to TRUE list.
293 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
294 (print_insn_mve): Updated to accept new %j,
295 %<bitfield>m and %<bitfield>n patterns.
297 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
299 * mips-opc.c (mips_builtin_opcodes): Change source register
302 2019-05-20 Nick Clifton <nickc@redhat.com>
304 * po/fr.po: Updated French translation.
306 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
307 Michael Collison <michael.collison@arm.com>
309 * arm-dis.c (thumb32_opcodes): Add new instructions.
310 (enum mve_instructions): Likewise.
311 (enum mve_undefined): Add new reasons.
312 (is_mve_encoding_conflict): Handle new instructions.
313 (is_mve_undefined): Likewise.
314 (is_mve_unpredictable): Likewise.
315 (print_mve_undefined): Likewise.
316 (print_mve_size): Likewise.
318 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
319 Michael Collison <michael.collison@arm.com>
321 * arm-dis.c (thumb32_opcodes): Add new instructions.
322 (enum mve_instructions): Likewise.
323 (is_mve_encoding_conflict): Handle new instructions.
324 (is_mve_undefined): Likewise.
325 (is_mve_unpredictable): Likewise.
326 (print_mve_size): Likewise.
328 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
329 Michael Collison <michael.collison@arm.com>
331 * arm-dis.c (thumb32_opcodes): Add new instructions.
332 (enum mve_instructions): Likewise.
333 (is_mve_encoding_conflict): Likewise.
334 (is_mve_unpredictable): Likewise.
335 (print_mve_size): Likewise.
337 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
338 Michael Collison <michael.collison@arm.com>
340 * arm-dis.c (thumb32_opcodes): Add new instructions.
341 (enum mve_instructions): Likewise.
342 (is_mve_encoding_conflict): Handle new instructions.
343 (is_mve_undefined): Likewise.
344 (is_mve_unpredictable): Likewise.
345 (print_mve_size): Likewise.
347 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
348 Michael Collison <michael.collison@arm.com>
350 * arm-dis.c (thumb32_opcodes): Add new instructions.
351 (enum mve_instructions): Likewise.
352 (is_mve_encoding_conflict): Handle new instructions.
353 (is_mve_undefined): Likewise.
354 (is_mve_unpredictable): Likewise.
355 (print_mve_size): Likewise.
356 (print_insn_mve): Likewise.
358 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
359 Michael Collison <michael.collison@arm.com>
361 * arm-dis.c (thumb32_opcodes): Add new instructions.
362 (print_insn_thumb32): Handle new instructions.
364 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
365 Michael Collison <michael.collison@arm.com>
367 * arm-dis.c (enum mve_instructions): Add new instructions.
368 (enum mve_undefined): Add new reasons.
369 (is_mve_encoding_conflict): Handle new instructions.
370 (is_mve_undefined): Likewise.
371 (is_mve_unpredictable): Likewise.
372 (print_mve_undefined): Likewise.
373 (print_mve_size): Likewise.
374 (print_mve_shift_n): Likewise.
375 (print_insn_mve): Likewise.
377 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
378 Michael Collison <michael.collison@arm.com>
380 * arm-dis.c (enum mve_instructions): Add new instructions.
381 (is_mve_encoding_conflict): Handle new instructions.
382 (is_mve_unpredictable): Likewise.
383 (print_mve_rotate): Likewise.
384 (print_mve_size): Likewise.
385 (print_insn_mve): Likewise.
387 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
388 Michael Collison <michael.collison@arm.com>
390 * arm-dis.c (enum mve_instructions): Add new instructions.
391 (is_mve_encoding_conflict): Handle new instructions.
392 (is_mve_unpredictable): Likewise.
393 (print_mve_size): Likewise.
394 (print_insn_mve): Likewise.
396 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
397 Michael Collison <michael.collison@arm.com>
399 * arm-dis.c (enum mve_instructions): Add new instructions.
400 (enum mve_undefined): Add new reasons.
401 (is_mve_encoding_conflict): Handle new instructions.
402 (is_mve_undefined): Likewise.
403 (is_mve_unpredictable): Likewise.
404 (print_mve_undefined): Likewise.
405 (print_mve_size): Likewise.
406 (print_insn_mve): Likewise.
408 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
409 Michael Collison <michael.collison@arm.com>
411 * arm-dis.c (enum mve_instructions): Add new instructions.
412 (is_mve_encoding_conflict): Handle new instructions.
413 (is_mve_undefined): Likewise.
414 (is_mve_unpredictable): Likewise.
415 (print_mve_size): Likewise.
416 (print_insn_mve): Likewise.
418 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
419 Michael Collison <michael.collison@arm.com>
421 * arm-dis.c (enum mve_instructions): Add new instructions.
422 (enum mve_unpredictable): Add new reasons.
423 (enum mve_undefined): Likewise.
424 (is_mve_okay_in_it): Handle new isntructions.
425 (is_mve_encoding_conflict): Likewise.
426 (is_mve_undefined): Likewise.
427 (is_mve_unpredictable): Likewise.
428 (print_mve_vmov_index): Likewise.
429 (print_simd_imm8): Likewise.
430 (print_mve_undefined): Likewise.
431 (print_mve_unpredictable): Likewise.
432 (print_mve_size): Likewise.
433 (print_insn_mve): Likewise.
435 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
436 Michael Collison <michael.collison@arm.com>
438 * arm-dis.c (enum mve_instructions): Add new instructions.
439 (enum mve_unpredictable): Add new reasons.
440 (enum mve_undefined): Likewise.
441 (is_mve_encoding_conflict): Handle new instructions.
442 (is_mve_undefined): Likewise.
443 (is_mve_unpredictable): Likewise.
444 (print_mve_undefined): Likewise.
445 (print_mve_unpredictable): Likewise.
446 (print_mve_rounding_mode): Likewise.
447 (print_mve_vcvt_size): Likewise.
448 (print_mve_size): Likewise.
449 (print_insn_mve): Likewise.
451 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
452 Michael Collison <michael.collison@arm.com>
454 * arm-dis.c (enum mve_instructions): Add new instructions.
455 (enum mve_unpredictable): Add new reasons.
456 (enum mve_undefined): Likewise.
457 (is_mve_undefined): Handle new instructions.
458 (is_mve_unpredictable): Likewise.
459 (print_mve_undefined): Likewise.
460 (print_mve_unpredictable): Likewise.
461 (print_mve_size): Likewise.
462 (print_insn_mve): Likewise.
464 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
465 Michael Collison <michael.collison@arm.com>
467 * arm-dis.c (enum mve_instructions): Add new instructions.
468 (enum mve_undefined): Add new reasons.
469 (insns): Add new instructions.
470 (is_mve_encoding_conflict):
471 (print_mve_vld_str_addr): New print function.
472 (is_mve_undefined): Handle new instructions.
473 (is_mve_unpredictable): Likewise.
474 (print_mve_undefined): Likewise.
475 (print_mve_size): Likewise.
476 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
477 (print_insn_mve): Handle new operands.
479 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
480 Michael Collison <michael.collison@arm.com>
482 * arm-dis.c (enum mve_instructions): Add new instructions.
483 (enum mve_unpredictable): Add new reasons.
484 (is_mve_encoding_conflict): Handle new instructions.
485 (is_mve_unpredictable): Likewise.
486 (mve_opcodes): Add new instructions.
487 (print_mve_unpredictable): Handle new reasons.
488 (print_mve_register_blocks): New print function.
489 (print_mve_size): Handle new instructions.
490 (print_insn_mve): Likewise.
492 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
493 Michael Collison <michael.collison@arm.com>
495 * arm-dis.c (enum mve_instructions): Add new instructions.
496 (enum mve_unpredictable): Add new reasons.
497 (enum mve_undefined): Likewise.
498 (is_mve_encoding_conflict): Handle new instructions.
499 (is_mve_undefined): Likewise.
500 (is_mve_unpredictable): Likewise.
501 (coprocessor_opcodes): Move NEON VDUP from here...
502 (neon_opcodes): ... to here.
503 (mve_opcodes): Add new instructions.
504 (print_mve_undefined): Handle new reasons.
505 (print_mve_unpredictable): Likewise.
506 (print_mve_size): Handle new instructions.
507 (print_insn_neon): Handle vdup.
508 (print_insn_mve): Handle new operands.
510 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
511 Michael Collison <michael.collison@arm.com>
513 * arm-dis.c (enum mve_instructions): Add new instructions.
514 (enum mve_unpredictable): Add new values.
515 (mve_opcodes): Add new instructions.
516 (vec_condnames): New array with vector conditions.
517 (mve_predicatenames): New array with predicate suffixes.
518 (mve_vec_sizename): New array with vector sizes.
519 (enum vpt_pred_state): New enum with vector predication states.
520 (struct vpt_block): New struct type for vpt blocks.
521 (vpt_block_state): Global struct to keep track of state.
522 (mve_extract_pred_mask): New helper function.
523 (num_instructions_vpt_block): Likewise.
524 (mark_outside_vpt_block): Likewise.
525 (mark_inside_vpt_block): Likewise.
526 (invert_next_predicate_state): Likewise.
527 (update_next_predicate_state): Likewise.
528 (update_vpt_block_state): Likewise.
529 (is_vpt_instruction): Likewise.
530 (is_mve_encoding_conflict): Add entries for new instructions.
531 (is_mve_unpredictable): Likewise.
532 (print_mve_unpredictable): Handle new cases.
533 (print_instruction_predicate): Likewise.
534 (print_mve_size): New function.
535 (print_vec_condition): New function.
536 (print_insn_mve): Handle vpt blocks and new print operands.
538 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
540 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
541 8, 14 and 15 for Armv8.1-M Mainline.
543 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
544 Michael Collison <michael.collison@arm.com>
546 * arm-dis.c (enum mve_instructions): New enum.
547 (enum mve_unpredictable): Likewise.
548 (enum mve_undefined): Likewise.
549 (struct mopcode32): New struct.
550 (is_mve_okay_in_it): New function.
551 (is_mve_architecture): Likewise.
552 (arm_decode_field): Likewise.
553 (arm_decode_field_multiple): Likewise.
554 (is_mve_encoding_conflict): Likewise.
555 (is_mve_undefined): Likewise.
556 (is_mve_unpredictable): Likewise.
557 (print_mve_undefined): Likewise.
558 (print_mve_unpredictable): Likewise.
559 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
560 (print_insn_mve): New function.
561 (print_insn_thumb32): Handle MVE architecture.
562 (select_arm_features): Force thumb for Armv8.1-m Mainline.
564 2019-05-10 Nick Clifton <nickc@redhat.com>
567 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
568 end of the table prematurely.
570 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
572 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
575 2019-05-11 Alan Modra <amodra@gmail.com>
577 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
578 when -Mraw is in effect.
580 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
582 * aarch64-dis-2.c: Regenerate.
583 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
584 (OP_SVE_BBB): New variant set.
585 (OP_SVE_DDDD): New variant set.
586 (OP_SVE_HHH): New variant set.
587 (OP_SVE_HHHU): New variant set.
588 (OP_SVE_SSS): New variant set.
589 (OP_SVE_SSSU): New variant set.
590 (OP_SVE_SHH): New variant set.
591 (OP_SVE_SBBU): New variant set.
592 (OP_SVE_DSS): New variant set.
593 (OP_SVE_DHHU): New variant set.
594 (OP_SVE_VMV_HSD_BHS): New variant set.
595 (OP_SVE_VVU_HSD_BHS): New variant set.
596 (OP_SVE_VVVU_SD_BH): New variant set.
597 (OP_SVE_VVVU_BHSD): New variant set.
598 (OP_SVE_VVV_QHD_DBS): New variant set.
599 (OP_SVE_VVV_HSD_BHS): New variant set.
600 (OP_SVE_VVV_HSD_BHS2): New variant set.
601 (OP_SVE_VVV_BHS_HSD): New variant set.
602 (OP_SVE_VV_BHS_HSD): New variant set.
603 (OP_SVE_VVV_SD): New variant set.
604 (OP_SVE_VVU_BHS_HSD): New variant set.
605 (OP_SVE_VZVV_SD): New variant set.
606 (OP_SVE_VZVV_BH): New variant set.
607 (OP_SVE_VZV_SD): New variant set.
608 (aarch64_opcode_table): Add sve2 instructions.
610 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
612 * aarch64-asm-2.c: Regenerated.
613 * aarch64-dis-2.c: Regenerated.
614 * aarch64-opc-2.c: Regenerated.
615 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
616 for SVE_SHLIMM_UNPRED_22.
617 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
618 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
621 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
623 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
624 sve_size_tsz_bhs iclass encode.
625 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
626 sve_size_tsz_bhs iclass decode.
628 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
630 * aarch64-asm-2.c: Regenerated.
631 * aarch64-dis-2.c: Regenerated.
632 * aarch64-opc-2.c: Regenerated.
633 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
634 for SVE_Zm4_11_INDEX.
635 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
636 (fields): Handle SVE_i2h field.
637 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
638 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
640 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
642 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
643 sve_shift_tsz_bhsd iclass encode.
644 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
645 sve_shift_tsz_bhsd iclass decode.
647 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
649 * aarch64-asm-2.c: Regenerated.
650 * aarch64-dis-2.c: Regenerated.
651 * aarch64-opc-2.c: Regenerated.
652 * aarch64-asm.c (aarch64_ins_sve_shrimm):
653 (aarch64_encode_variant_using_iclass): Handle
654 sve_shift_tsz_hsd iclass encode.
655 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
656 sve_shift_tsz_hsd iclass decode.
657 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
658 for SVE_SHRIMM_UNPRED_22.
659 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
660 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
663 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
665 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
666 sve_size_013 iclass encode.
667 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
668 sve_size_013 iclass decode.
670 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
672 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
673 sve_size_bh iclass encode.
674 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
675 sve_size_bh iclass decode.
677 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
679 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
680 sve_size_sd2 iclass encode.
681 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
682 sve_size_sd2 iclass decode.
683 * aarch64-opc.c (fields): Handle SVE_sz2 field.
684 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
686 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
688 * aarch64-asm-2.c: Regenerated.
689 * aarch64-dis-2.c: Regenerated.
690 * aarch64-opc-2.c: Regenerated.
691 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
693 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
694 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
696 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
698 * aarch64-asm-2.c: Regenerated.
699 * aarch64-dis-2.c: Regenerated.
700 * aarch64-opc-2.c: Regenerated.
701 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
702 for SVE_Zm3_11_INDEX.
703 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
704 (fields): Handle SVE_i3l and SVE_i3h2 fields.
705 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
707 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
709 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
711 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
712 sve_size_hsd2 iclass encode.
713 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
714 sve_size_hsd2 iclass decode.
715 * aarch64-opc.c (fields): Handle SVE_size field.
716 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
718 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
720 * aarch64-asm-2.c: Regenerated.
721 * aarch64-dis-2.c: Regenerated.
722 * aarch64-opc-2.c: Regenerated.
723 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
725 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
726 (fields): Handle SVE_rot3 field.
727 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
728 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
730 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
732 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
735 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
738 (aarch64_feature_sve2, aarch64_feature_sve2aes,
739 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
740 aarch64_feature_sve2bitperm): New feature sets.
741 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
742 for feature set addresses.
743 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
744 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
746 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
747 Faraz Shahbazker <fshahbazker@wavecomp.com>
749 * mips-dis.c (mips_calculate_combination_ases): Add ISA
750 argument and set ASE_EVA_R6 appropriately.
751 (set_default_mips_dis_options): Pass ISA to above.
752 (parse_mips_dis_option): Likewise.
753 * mips-opc.c (EVAR6): New macro.
754 (mips_builtin_opcodes): Add llwpe, scwpe.
756 2019-05-01 Sudakshina Das <sudi.das@arm.com>
758 * aarch64-asm-2.c: Regenerated.
759 * aarch64-dis-2.c: Regenerated.
760 * aarch64-opc-2.c: Regenerated.
761 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
762 AARCH64_OPND_TME_UIMM16.
763 (aarch64_print_operand): Likewise.
764 * aarch64-tbl.h (QL_IMM_NIL): New.
767 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
769 2019-04-29 John Darrington <john@darrington.wattle.id.au>
771 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
773 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
774 Faraz Shahbazker <fshahbazker@wavecomp.com>
776 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
778 2019-04-24 John Darrington <john@darrington.wattle.id.au>
780 * s12z-opc.h: Add extern "C" bracketing to help
781 users who wish to use this interface in c++ code.
783 2019-04-24 John Darrington <john@darrington.wattle.id.au>
785 * s12z-opc.c (bm_decode): Handle bit map operations with the
788 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
790 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
791 specifier. Add entries for VLDR and VSTR of system registers.
792 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
793 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
794 of %J and %K format specifier.
796 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
798 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
799 Add new entries for VSCCLRM instruction.
800 (print_insn_coprocessor): Handle new %C format control code.
802 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
804 * arm-dis.c (enum isa): New enum.
805 (struct sopcode32): New structure.
806 (coprocessor_opcodes): change type of entries to struct sopcode32 and
807 set isa field of all current entries to ANY.
808 (print_insn_coprocessor): Change type of insn to struct sopcode32.
809 Only match an entry if its isa field allows the current mode.
811 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
813 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
815 (print_insn_thumb32): Add logic to print %n CLRM register list.
817 2019-04-15 Sudakshina Das <sudi.das@arm.com>
819 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
822 2019-04-15 Sudakshina Das <sudi.das@arm.com>
824 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
825 (print_insn_thumb32): Edit the switch case for %Z.
827 2019-04-15 Sudakshina Das <sudi.das@arm.com>
829 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
831 2019-04-15 Sudakshina Das <sudi.das@arm.com>
833 * arm-dis.c (thumb32_opcodes): New instruction bfl.
835 2019-04-15 Sudakshina Das <sudi.das@arm.com>
837 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
839 2019-04-15 Sudakshina Das <sudi.das@arm.com>
841 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
842 Arm register with r13 and r15 unpredictable.
843 (thumb32_opcodes): New instructions for bfx and bflx.
845 2019-04-15 Sudakshina Das <sudi.das@arm.com>
847 * arm-dis.c (thumb32_opcodes): New instructions for bf.
849 2019-04-15 Sudakshina Das <sudi.das@arm.com>
851 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
853 2019-04-15 Sudakshina Das <sudi.das@arm.com>
855 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
857 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
859 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
861 2019-04-12 John Darrington <john@darrington.wattle.id.au>
863 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
864 "optr". ("operator" is a reserved word in c++).
866 2019-04-11 Sudakshina Das <sudi.das@arm.com>
868 * aarch64-opc.c (aarch64_print_operand): Add case for
870 (verify_constraints): Likewise.
871 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
872 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
873 to accept Rt|SP as first operand.
874 (AARCH64_OPERANDS): Add new Rt_SP.
875 * aarch64-asm-2.c: Regenerated.
876 * aarch64-dis-2.c: Regenerated.
877 * aarch64-opc-2.c: Regenerated.
879 2019-04-11 Sudakshina Das <sudi.das@arm.com>
881 * aarch64-asm-2.c: Regenerated.
882 * aarch64-dis-2.c: Likewise.
883 * aarch64-opc-2.c: Likewise.
884 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
886 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
888 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
890 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
892 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
893 * i386-init.h: Regenerated.
895 2019-04-07 Alan Modra <amodra@gmail.com>
897 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
898 op_separator to control printing of spaces, comma and parens
899 rather than need_comma, need_paren and spaces vars.
901 2019-04-07 Alan Modra <amodra@gmail.com>
904 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
905 (print_insn_neon, print_insn_arm): Likewise.
907 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
909 * i386-dis-evex.h (evex_table): Updated to support BF16
911 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
912 and EVEX_W_0F3872_P_3.
913 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
914 (cpu_flags): Add bitfield for CpuAVX512_BF16.
915 * i386-opc.h (enum): Add CpuAVX512_BF16.
916 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
917 * i386-opc.tbl: Add AVX512 BF16 instructions.
918 * i386-init.h: Regenerated.
919 * i386-tbl.h: Likewise.
921 2019-04-05 Alan Modra <amodra@gmail.com>
923 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
924 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
925 to favour printing of "-" branch hint when using the "y" bit.
926 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
928 2019-04-05 Alan Modra <amodra@gmail.com>
930 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
931 opcode until first operand is output.
933 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
936 * ppc-opc.c (valid_bo_pre_v2): Add comments.
937 (valid_bo_post_v2): Add support for 'at' branch hints.
938 (insert_bo): Only error on branch on ctr.
939 (get_bo_hint_mask): New function.
940 (insert_boe): Add new 'branch_taken' formal argument. Add support
941 for inserting 'at' branch hints.
942 (extract_boe): Add new 'branch_taken' formal argument. Add support
943 for extracting 'at' branch hints.
944 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
945 (BOE): Delete operand.
946 (BOM, BOP): New operands.
948 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
949 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
950 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
951 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
952 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
953 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
954 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
955 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
956 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
957 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
958 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
959 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
960 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
961 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
962 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
963 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
964 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
965 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
966 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
967 bttarl+>: New extended mnemonics.
969 2019-03-28 Alan Modra <amodra@gmail.com>
972 * ppc-opc.c (BTF): Define.
973 (powerpc_opcodes): Use for mtfsb*.
974 * ppc-dis.c (print_insn_powerpc): Print fields with both
975 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
977 2019-03-25 Tamar Christina <tamar.christina@arm.com>
979 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
980 (mapping_symbol_for_insn): Implement new algorithm.
981 (print_insn): Remove duplicate code.
983 2019-03-25 Tamar Christina <tamar.christina@arm.com>
985 * aarch64-dis.c (print_insn_aarch64):
988 2019-03-25 Tamar Christina <tamar.christina@arm.com>
990 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
993 2019-03-25 Tamar Christina <tamar.christina@arm.com>
995 * aarch64-dis.c (last_stop_offset): New.
996 (print_insn_aarch64): Use stop_offset.
998 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1001 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1003 * i386-init.h: Regenerated.
1005 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1008 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1009 vmovdqu16, vmovdqu32 and vmovdqu64.
1010 * i386-tbl.h: Regenerated.
1012 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1014 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1015 from vstrszb, vstrszh, and vstrszf.
1017 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1019 * s390-opc.txt: Add instruction descriptions.
1021 2019-02-08 Jim Wilson <jimw@sifive.com>
1023 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1026 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1028 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1030 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1033 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1034 * aarch64-opc.c (verify_elem_sd): New.
1035 (fields): Add FLD_sz entr.
1036 * aarch64-tbl.h (_SIMD_INSN): New.
1037 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1038 fmulx scalar and vector by element isns.
1040 2019-02-07 Nick Clifton <nickc@redhat.com>
1042 * po/sv.po: Updated Swedish translation.
1044 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1046 * s390-mkopc.c (main): Accept arch13 as cpu string.
1047 * s390-opc.c: Add new instruction formats and instruction opcode
1049 * s390-opc.txt: Add new arch13 instructions.
1051 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1053 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1054 (aarch64_opcode): Change encoding for stg, stzg
1056 * aarch64-asm-2.c: Regenerated.
1057 * aarch64-dis-2.c: Regenerated.
1058 * aarch64-opc-2.c: Regenerated.
1060 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1062 * aarch64-asm-2.c: Regenerated.
1063 * aarch64-dis-2.c: Likewise.
1064 * aarch64-opc-2.c: Likewise.
1065 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1067 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1068 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1070 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1071 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1072 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1073 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1074 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1075 case for ldstgv_indexed.
1076 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1077 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1078 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1079 * aarch64-asm-2.c: Regenerated.
1080 * aarch64-dis-2.c: Regenerated.
1081 * aarch64-opc-2.c: Regenerated.
1083 2019-01-23 Nick Clifton <nickc@redhat.com>
1085 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1087 2019-01-21 Nick Clifton <nickc@redhat.com>
1089 * po/de.po: Updated German translation.
1090 * po/uk.po: Updated Ukranian translation.
1092 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1093 * mips-dis.c (mips_arch_choices): Fix typo in
1094 gs464, gs464e and gs264e descriptors.
1096 2019-01-19 Nick Clifton <nickc@redhat.com>
1098 * configure: Regenerate.
1099 * po/opcodes.pot: Regenerate.
1101 2018-06-24 Nick Clifton <nickc@redhat.com>
1103 2.32 branch created.
1105 2019-01-09 John Darrington <john@darrington.wattle.id.au>
1107 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1109 -dis.c (opr_emit_disassembly): Do not omit an index if it is
1112 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1114 * configure: Regenerate.
1116 2019-01-07 Alan Modra <amodra@gmail.com>
1118 * configure: Regenerate.
1119 * po/POTFILES.in: Regenerate.
1121 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1123 * s12z-opc.c: New file.
1124 * s12z-opc.h: New file.
1125 * s12z-dis.c: Removed all code not directly related to display
1126 of instructions. Used the interface provided by the new files
1128 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1129 * Makefile.in: Regenerate.
1130 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1131 * configure: Regenerate.
1133 2019-01-01 Alan Modra <amodra@gmail.com>
1135 Update year range in copyright notice of all files.
1137 For older changes see ChangeLog-2018
1139 Copyright (C) 2019 Free Software Foundation, Inc.
1141 Copying and distribution of this file, with or without modification,
1142 are permitted in any medium without royalty provided the copyright
1143 notice and this notice are preserved.
1149 version-control: never