opcodes/ChangeLog

   1 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
   2             Lili Cui  <lili.cui@intel.com>
   3
   4         * doc/c-i386.texi: Document enqcmd.
   5         * testsuite/gas/i386/enqcmd-intel.d: New file.
   6         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
   7         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
   8         * testsuite/gas/i386/enqcmd.d: Likewise.
   9         * testsuite/gas/i386/enqcmd.s: Likewise.
  10         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
  11         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
  12         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
  13         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
  14         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
  15         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
  16         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
  17         and x86-64-enqcmd.
  18
  19 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
  20
  21         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
  22
  23 2019-06-03  Alan Modra  <amodra@gmail.com>
  24
  25         * ppc-dis.c (prefix_opcd_indices): Correct size.
  26
  27 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
  28
  29         PR gas/24625
  30         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
  31         Disp8ShiftVL.
  32         * i386-tbl.h: Regenerated.
  33
  34 2019-05-24  Alan Modra  <amodra@gmail.com>
  35
  36         * po/POTFILES.in: Regenerate.
  37
  38 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
  39             Alan Modra  <amodra@gmail.com>
  40
  41         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
  42         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
  43         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
  44         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
  45         XTOP>): Define and add entries.
  46         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
  47         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
  48         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
  49         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
  50
  51 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
  52             Alan Modra  <amodra@gmail.com>
  53
  54         * ppc-dis.c (ppc_opts): Add "future" entry.
  55         (PREFIX_OPCD_SEGS): Define.
  56         (prefix_opcd_indices): New array.
  57         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
  58         (lookup_prefix): New function.
  59         (print_insn_powerpc): Handle 64-bit prefix instructions.
  60         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
  61         (PMRR, POWERXX): Define.
  62         (prefix_opcodes): New instruction table.
  63         (prefix_num_opcodes): New constant.
  64
  65 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
  66
  67         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
  68         * configure: Regenerated.
  69         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
  70         and cpu/bpf.opc.
  71         (HFILES): Add bpf-desc.h and bpf-opc.h.
  72         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
  73         bpf-ibld.c and bpf-opc.c.
  74         (BPF_DEPS): Define.
  75         * Makefile.in: Regenerated.
  76         * disassemble.c (ARCH_bpf): Define.
  77         (disassembler): Add case for bfd_arch_bpf.
  78         (disassemble_init_for_target): Likewise.
  79         (enum epbf_isa_attr): Define.
  80         * disassemble.h: extern print_insn_bpf.
  81         * bpf-asm.c: Generated.
  82         * bpf-opc.h: Likewise.
  83         * bpf-opc.c: Likewise.
  84         * bpf-ibld.c: Likewise.
  85         * bpf-dis.c: Likewise.
  86         * bpf-desc.h: Likewise.
  87         * bpf-desc.c: Likewise.
  88
  89 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
  90
  91         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
  92         and VMSR with the new operands.
  93
  94 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
  95
  96         * arm-dis.c (enum mve_instructions): New enum
  97         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
  98         and cneg.
  99         (mve_opcodes): New instructions as above.
 100         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 101         csneg and csel.
 102         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 103
 104 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 105
 106         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 107         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 108         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 109         uqshl, urshrl and urshr.
 110         (is_mve_okay_in_it): Add new instructions to TRUE list.
 111         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 112         (print_insn_mve): Updated to accept new %j,
 113         %<bitfield>m and %<bitfield>n patterns.
 114
 115 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 116
 117         * mips-opc.c (mips_builtin_opcodes): Change source register
 118         constraint for DAUI.
 119
 120 2019-05-20  Nick Clifton  <nickc@redhat.com>
 121
 122         * po/fr.po: Updated French translation.
 123
 124 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 125             Michael Collison <michael.collison@arm.com>
 126
 127         * arm-dis.c (thumb32_opcodes): Add new instructions.
 128         (enum mve_instructions): Likewise.
 129         (enum mve_undefined): Add new reasons.
 130         (is_mve_encoding_conflict): Handle new instructions.
 131         (is_mve_undefined): Likewise.
 132         (is_mve_unpredictable): Likewise.
 133         (print_mve_undefined): Likewise.
 134         (print_mve_size): Likewise.
 135
 136 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 137             Michael Collison <michael.collison@arm.com>
 138
 139         * arm-dis.c (thumb32_opcodes): Add new instructions.
 140         (enum mve_instructions): Likewise.
 141         (is_mve_encoding_conflict): Handle new instructions.
 142         (is_mve_undefined): Likewise.
 143         (is_mve_unpredictable): Likewise.
 144         (print_mve_size): Likewise.
 145
 146 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 147             Michael Collison <michael.collison@arm.com>
 148
 149         * arm-dis.c (thumb32_opcodes): Add new instructions.
 150         (enum mve_instructions): Likewise.
 151         (is_mve_encoding_conflict): Likewise.
 152         (is_mve_unpredictable): Likewise.
 153         (print_mve_size): Likewise.
 154
 155 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 156             Michael Collison <michael.collison@arm.com>
 157
 158         * arm-dis.c (thumb32_opcodes): Add new instructions.
 159         (enum mve_instructions): Likewise.
 160         (is_mve_encoding_conflict): Handle new instructions.
 161         (is_mve_undefined): Likewise.
 162         (is_mve_unpredictable): Likewise.
 163         (print_mve_size): Likewise.
 164
 165 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 166             Michael Collison <michael.collison@arm.com>
 167
 168         * arm-dis.c (thumb32_opcodes): Add new instructions.
 169         (enum mve_instructions): Likewise.
 170         (is_mve_encoding_conflict): Handle new instructions.
 171         (is_mve_undefined): Likewise.
 172         (is_mve_unpredictable): Likewise.
 173         (print_mve_size): Likewise.
 174         (print_insn_mve): Likewise.
 175
 176 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 177             Michael Collison <michael.collison@arm.com>
 178
 179         * arm-dis.c (thumb32_opcodes): Add new instructions.
 180         (print_insn_thumb32): Handle new instructions.
 181
 182 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 183             Michael Collison <michael.collison@arm.com>
 184
 185         * arm-dis.c (enum mve_instructions): Add new instructions.
 186         (enum mve_undefined): Add new reasons.
 187         (is_mve_encoding_conflict): Handle new instructions.
 188         (is_mve_undefined): Likewise.
 189         (is_mve_unpredictable): Likewise.
 190         (print_mve_undefined): Likewise.
 191         (print_mve_size): Likewise.
 192         (print_mve_shift_n): Likewise.
 193         (print_insn_mve): Likewise.
 194
 195 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 196             Michael Collison <michael.collison@arm.com>
 197
 198         * arm-dis.c (enum mve_instructions): Add new instructions.
 199         (is_mve_encoding_conflict): Handle new instructions.
 200         (is_mve_unpredictable): Likewise.
 201         (print_mve_rotate): Likewise.
 202         (print_mve_size): Likewise.
 203         (print_insn_mve): Likewise.
 204
 205 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 206             Michael Collison <michael.collison@arm.com>
 207
 208         * arm-dis.c (enum mve_instructions): Add new instructions.
 209         (is_mve_encoding_conflict): Handle new instructions.
 210         (is_mve_unpredictable): Likewise.
 211         (print_mve_size): Likewise.
 212         (print_insn_mve): Likewise.
 213
 214 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 215             Michael Collison <michael.collison@arm.com>
 216
 217         * arm-dis.c (enum mve_instructions): Add new instructions.
 218         (enum mve_undefined): Add new reasons.
 219         (is_mve_encoding_conflict): Handle new instructions.
 220         (is_mve_undefined): Likewise.
 221         (is_mve_unpredictable): Likewise.
 222         (print_mve_undefined): Likewise.
 223         (print_mve_size): Likewise.
 224         (print_insn_mve): Likewise.
 225
 226 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 227             Michael Collison <michael.collison@arm.com>
 228
 229         * arm-dis.c (enum mve_instructions): Add new instructions.
 230         (is_mve_encoding_conflict): Handle new instructions.
 231         (is_mve_undefined): Likewise.
 232         (is_mve_unpredictable): Likewise.
 233         (print_mve_size): Likewise.
 234         (print_insn_mve): Likewise.
 235
 236 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 237             Michael Collison <michael.collison@arm.com>
 238
 239         * arm-dis.c (enum mve_instructions): Add new instructions.
 240         (enum mve_unpredictable): Add new reasons.
 241         (enum mve_undefined): Likewise.
 242         (is_mve_okay_in_it): Handle new isntructions.
 243         (is_mve_encoding_conflict): Likewise.
 244         (is_mve_undefined): Likewise.
 245         (is_mve_unpredictable): Likewise.
 246         (print_mve_vmov_index): Likewise.
 247         (print_simd_imm8): Likewise.
 248         (print_mve_undefined): Likewise.
 249         (print_mve_unpredictable): Likewise.
 250         (print_mve_size): Likewise.
 251         (print_insn_mve): Likewise.
 252
 253 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 254             Michael Collison <michael.collison@arm.com>
 255
 256         * arm-dis.c (enum mve_instructions): Add new instructions.
 257         (enum mve_unpredictable): Add new reasons.
 258         (enum mve_undefined): Likewise.
 259         (is_mve_encoding_conflict): Handle new instructions.
 260         (is_mve_undefined): Likewise.
 261         (is_mve_unpredictable): Likewise.
 262         (print_mve_undefined): Likewise.
 263         (print_mve_unpredictable): Likewise.
 264         (print_mve_rounding_mode): Likewise.
 265         (print_mve_vcvt_size): Likewise.
 266         (print_mve_size): Likewise.
 267         (print_insn_mve): Likewise.
 268
 269 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 270             Michael Collison <michael.collison@arm.com>
 271
 272         * arm-dis.c (enum mve_instructions): Add new instructions.
 273         (enum mve_unpredictable): Add new reasons.
 274         (enum mve_undefined): Likewise.
 275         (is_mve_undefined): Handle new instructions.
 276         (is_mve_unpredictable): Likewise.
 277         (print_mve_undefined): Likewise.
 278         (print_mve_unpredictable): Likewise.
 279         (print_mve_size): Likewise.
 280         (print_insn_mve): Likewise.
 281
 282 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 283             Michael Collison <michael.collison@arm.com>
 284
 285         * arm-dis.c (enum mve_instructions): Add new instructions.
 286         (enum mve_undefined): Add new reasons.
 287         (insns): Add new instructions.
 288         (is_mve_encoding_conflict):
 289         (print_mve_vld_str_addr): New print function.
 290         (is_mve_undefined): Handle new instructions.
 291         (is_mve_unpredictable): Likewise.
 292         (print_mve_undefined): Likewise.
 293         (print_mve_size): Likewise.
 294         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 295         (print_insn_mve):  Handle new operands.
 296
 297 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 298             Michael Collison <michael.collison@arm.com>
 299
 300         * arm-dis.c (enum mve_instructions): Add new instructions.
 301         (enum mve_unpredictable): Add new reasons.
 302         (is_mve_encoding_conflict): Handle new instructions.
 303         (is_mve_unpredictable): Likewise.
 304         (mve_opcodes): Add new instructions.
 305         (print_mve_unpredictable): Handle new reasons.
 306         (print_mve_register_blocks): New print function.
 307         (print_mve_size): Handle new instructions.
 308         (print_insn_mve): Likewise.
 309
 310 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 311             Michael Collison <michael.collison@arm.com>
 312
 313         * arm-dis.c (enum mve_instructions): Add new instructions.
 314         (enum mve_unpredictable): Add new reasons.
 315         (enum mve_undefined): Likewise.
 316         (is_mve_encoding_conflict): Handle new instructions.
 317         (is_mve_undefined): Likewise.
 318         (is_mve_unpredictable): Likewise.
 319         (coprocessor_opcodes): Move NEON VDUP from here...
 320         (neon_opcodes): ... to here.
 321         (mve_opcodes): Add new instructions.
 322         (print_mve_undefined):  Handle new reasons.
 323         (print_mve_unpredictable): Likewise.
 324         (print_mve_size): Handle new instructions.
 325         (print_insn_neon): Handle vdup.
 326         (print_insn_mve): Handle new operands.
 327
 328 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 329             Michael Collison <michael.collison@arm.com>
 330
 331         * arm-dis.c (enum mve_instructions): Add new instructions.
 332         (enum mve_unpredictable): Add new values.
 333         (mve_opcodes): Add new instructions.
 334         (vec_condnames): New array with vector conditions.
 335         (mve_predicatenames): New array with predicate suffixes.
 336         (mve_vec_sizename): New array with vector sizes.
 337         (enum vpt_pred_state): New enum with vector predication states.
 338         (struct vpt_block): New struct type for vpt blocks.
 339         (vpt_block_state): Global struct to keep track of state.
 340         (mve_extract_pred_mask): New helper function.
 341         (num_instructions_vpt_block): Likewise.
 342         (mark_outside_vpt_block): Likewise.
 343         (mark_inside_vpt_block): Likewise.
 344         (invert_next_predicate_state): Likewise.
 345         (update_next_predicate_state): Likewise.
 346         (update_vpt_block_state): Likewise.
 347         (is_vpt_instruction): Likewise.
 348         (is_mve_encoding_conflict): Add entries for new instructions.
 349         (is_mve_unpredictable): Likewise.
 350         (print_mve_unpredictable): Handle new cases.
 351         (print_instruction_predicate): Likewise.
 352         (print_mve_size): New function.
 353         (print_vec_condition): New function.
 354         (print_insn_mve): Handle vpt blocks and new print operands.
 355
 356 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 357
 358         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 359         8, 14 and 15 for Armv8.1-M Mainline.
 360
 361 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 362             Michael Collison <michael.collison@arm.com>
 363
 364         * arm-dis.c (enum mve_instructions): New enum.
 365         (enum mve_unpredictable): Likewise.
 366         (enum mve_undefined): Likewise.
 367         (struct mopcode32): New struct.
 368         (is_mve_okay_in_it): New function.
 369         (is_mve_architecture): Likewise.
 370         (arm_decode_field): Likewise.
 371         (arm_decode_field_multiple): Likewise.
 372         (is_mve_encoding_conflict): Likewise.
 373         (is_mve_undefined): Likewise.
 374         (is_mve_unpredictable): Likewise.
 375         (print_mve_undefined): Likewise.
 376         (print_mve_unpredictable): Likewise.
 377         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 378         (print_insn_mve): New function.
 379         (print_insn_thumb32): Handle MVE architecture.
 380         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 381
 382 2019-05-10  Nick Clifton  <nickc@redhat.com>
 383
 384         PR 24538
 385         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 386         end of the table prematurely.
 387
 388 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 389
 390         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 391         macros for R6.
 392
 393 2019-05-11  Alan Modra  <amodra@gmail.com>
 394
 395         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 396         when -Mraw is in effect.
 397
 398 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 399
 400         * aarch64-dis-2.c: Regenerate.
 401         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 402         (OP_SVE_BBB): New variant set.
 403         (OP_SVE_DDDD): New variant set.
 404         (OP_SVE_HHH): New variant set.
 405         (OP_SVE_HHHU): New variant set.
 406         (OP_SVE_SSS): New variant set.
 407         (OP_SVE_SSSU): New variant set.
 408         (OP_SVE_SHH): New variant set.
 409         (OP_SVE_SBBU): New variant set.
 410         (OP_SVE_DSS): New variant set.
 411         (OP_SVE_DHHU): New variant set.
 412         (OP_SVE_VMV_HSD_BHS): New variant set.
 413         (OP_SVE_VVU_HSD_BHS): New variant set.
 414         (OP_SVE_VVVU_SD_BH): New variant set.
 415         (OP_SVE_VVVU_BHSD): New variant set.
 416         (OP_SVE_VVV_QHD_DBS): New variant set.
 417         (OP_SVE_VVV_HSD_BHS): New variant set.
 418         (OP_SVE_VVV_HSD_BHS2): New variant set.
 419         (OP_SVE_VVV_BHS_HSD): New variant set.
 420         (OP_SVE_VV_BHS_HSD): New variant set.
 421         (OP_SVE_VVV_SD): New variant set.
 422         (OP_SVE_VVU_BHS_HSD): New variant set.
 423         (OP_SVE_VZVV_SD): New variant set.
 424         (OP_SVE_VZVV_BH): New variant set.
 425         (OP_SVE_VZV_SD): New variant set.
 426         (aarch64_opcode_table): Add sve2 instructions.
 427
 428 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 429
 430         * aarch64-asm-2.c: Regenerated.
 431         * aarch64-dis-2.c: Regenerated.
 432         * aarch64-opc-2.c: Regenerated.
 433         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 434         for SVE_SHLIMM_UNPRED_22.
 435         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 436         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 437         operand.
 438
 439 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 440
 441         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 442         sve_size_tsz_bhs iclass encode.
 443         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 444         sve_size_tsz_bhs iclass decode.
 445
 446 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 447
 448         * aarch64-asm-2.c: Regenerated.
 449         * aarch64-dis-2.c: Regenerated.
 450         * aarch64-opc-2.c: Regenerated.
 451         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 452         for SVE_Zm4_11_INDEX.
 453         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 454         (fields): Handle SVE_i2h field.
 455         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 456         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 457
 458 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 459
 460         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 461         sve_shift_tsz_bhsd iclass encode.
 462         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 463         sve_shift_tsz_bhsd iclass decode.
 464
 465 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 466
 467         * aarch64-asm-2.c: Regenerated.
 468         * aarch64-dis-2.c: Regenerated.
 469         * aarch64-opc-2.c: Regenerated.
 470         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 471         (aarch64_encode_variant_using_iclass): Handle
 472         sve_shift_tsz_hsd iclass encode.
 473         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 474         sve_shift_tsz_hsd iclass decode.
 475         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 476         for SVE_SHRIMM_UNPRED_22.
 477         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 478         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 479         operand.
 480
 481 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 482
 483         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 484         sve_size_013 iclass encode.
 485         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 486         sve_size_013 iclass decode.
 487
 488 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 489
 490         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 491         sve_size_bh iclass encode.
 492         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 493         sve_size_bh iclass decode.
 494
 495 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 496
 497         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 498         sve_size_sd2 iclass encode.
 499         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 500         sve_size_sd2 iclass decode.
 501         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 502         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 503
 504 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 505
 506         * aarch64-asm-2.c: Regenerated.
 507         * aarch64-dis-2.c: Regenerated.
 508         * aarch64-opc-2.c: Regenerated.
 509         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 510         for SVE_ADDR_ZX.
 511         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 512         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 513
 514 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 515
 516         * aarch64-asm-2.c: Regenerated.
 517         * aarch64-dis-2.c: Regenerated.
 518         * aarch64-opc-2.c: Regenerated.
 519         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 520         for SVE_Zm3_11_INDEX.
 521         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 522         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 523         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 524         fields.
 525         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 526
 527 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 528
 529         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 530         sve_size_hsd2 iclass encode.
 531         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 532         sve_size_hsd2 iclass decode.
 533         * aarch64-opc.c (fields): Handle SVE_size field.
 534         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 535
 536 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 537
 538         * aarch64-asm-2.c: Regenerated.
 539         * aarch64-dis-2.c: Regenerated.
 540         * aarch64-opc-2.c: Regenerated.
 541         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 542         for SVE_IMM_ROT3.
 543         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 544         (fields): Handle SVE_rot3 field.
 545         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 546         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 547
 548 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 549
 550         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 551         instructions.
 552
 553 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 554
 555         * aarch64-tbl.h
 556         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 557         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 558         aarch64_feature_sve2bitperm): New feature sets.
 559         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 560         for feature set addresses.
 561         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 562         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 563
 564 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 565             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 566
 567         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 568         argument and set ASE_EVA_R6 appropriately.
 569         (set_default_mips_dis_options): Pass ISA to above.
 570         (parse_mips_dis_option): Likewise.
 571         * mips-opc.c (EVAR6): New macro.
 572         (mips_builtin_opcodes): Add llwpe, scwpe.
 573
 574 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 575
 576         * aarch64-asm-2.c: Regenerated.
 577         * aarch64-dis-2.c: Regenerated.
 578         * aarch64-opc-2.c: Regenerated.
 579         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 580         AARCH64_OPND_TME_UIMM16.
 581         (aarch64_print_operand): Likewise.
 582         * aarch64-tbl.h (QL_IMM_NIL): New.
 583         (TME): New.
 584         (_TME_INSN): New.
 585         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 586
 587 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 588
 589         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 590
 591 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 592             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 593
 594         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 595
 596 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 597
 598         * s12z-opc.h: Add extern "C" bracketing to help
 599         users who wish to use this interface in c++ code.
 600
 601 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 602
 603         * s12z-opc.c (bm_decode): Handle bit map operations with the
 604         "reserved0" mode.
 605
 606 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 607
 608         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 609         specifier.  Add entries for VLDR and VSTR of system registers.
 610         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 611         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 612         of %J and %K format specifier.
 613
 614 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 615
 616         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 617         Add new entries for VSCCLRM instruction.
 618         (print_insn_coprocessor): Handle new %C format control code.
 619
 620 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 621
 622         * arm-dis.c (enum isa): New enum.
 623         (struct sopcode32): New structure.
 624         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 625         set isa field of all current entries to ANY.
 626         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 627         Only match an entry if its isa field allows the current mode.
 628
 629 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 630
 631         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 632         CLRM.
 633         (print_insn_thumb32): Add logic to print %n CLRM register list.
 634
 635 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 636
 637         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 638         and %Q patterns.
 639
 640 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 641
 642         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 643         (print_insn_thumb32): Edit the switch case for %Z.
 644
 645 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 646
 647         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 648
 649 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 650
 651         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 652
 653 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 654
 655         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 656
 657 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 658
 659         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 660         Arm register with r13 and r15 unpredictable.
 661         (thumb32_opcodes): New instructions for bfx and bflx.
 662
 663 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 664
 665         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 666
 667 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 668
 669         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 670
 671 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 672
 673         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 674
 675 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 676
 677         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 678
 679 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 680
 681         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 682         "optr". ("operator" is a reserved word in c++).
 683
 684 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 685
 686         * aarch64-opc.c (aarch64_print_operand): Add case for
 687         AARCH64_OPND_Rt_SP.
 688         (verify_constraints): Likewise.
 689         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 690         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 691         to accept Rt|SP as first operand.
 692         (AARCH64_OPERANDS): Add new Rt_SP.
 693         * aarch64-asm-2.c: Regenerated.
 694         * aarch64-dis-2.c: Regenerated.
 695         * aarch64-opc-2.c: Regenerated.
 696
 697 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 698
 699         * aarch64-asm-2.c: Regenerated.
 700         * aarch64-dis-2.c: Likewise.
 701         * aarch64-opc-2.c: Likewise.
 702         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 703
 704 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 705
 706         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 707
 708 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 709
 710         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 711         * i386-init.h: Regenerated.
 712
 713 2019-04-07  Alan Modra  <amodra@gmail.com>
 714
 715         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 716         op_separator to control printing of spaces, comma and parens
 717         rather than need_comma, need_paren and spaces vars.
 718
 719 2019-04-07  Alan Modra  <amodra@gmail.com>
 720
 721         PR 24421
 722         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 723         (print_insn_neon, print_insn_arm): Likewise.
 724
 725 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 726
 727         * i386-dis-evex.h (evex_table): Updated to support BF16
 728         instructions.
 729         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 730         and EVEX_W_0F3872_P_3.
 731         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 732         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 733         * i386-opc.h (enum): Add CpuAVX512_BF16.
 734         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 735         * i386-opc.tbl: Add AVX512 BF16 instructions.
 736         * i386-init.h: Regenerated.
 737         * i386-tbl.h: Likewise.
 738
 739 2019-04-05  Alan Modra  <amodra@gmail.com>
 740
 741         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 742         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 743         to favour printing of "-" branch hint when using the "y" bit.
 744         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 745
 746 2019-04-05  Alan Modra  <amodra@gmail.com>
 747
 748         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 749         opcode until first operand is output.
 750
 751 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 752
 753         PR gas/24349
 754         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 755         (valid_bo_post_v2): Add support for 'at' branch hints.
 756         (insert_bo): Only error on branch on ctr.
 757         (get_bo_hint_mask): New function.
 758         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 759         for inserting 'at' branch hints.
 760         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 761         for extracting 'at' branch hints.
 762         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 763         (BOE): Delete operand.
 764         (BOM, BOP): New operands.
 765         (RM): Update value.
 766         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 767         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 768         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 769         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 770         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 771         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 772         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 773         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 774         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 775         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 776         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 777         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 778         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 779         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 780         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 781         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 782         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 783         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 784         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 785         bttarl+>: New extended mnemonics.
 786
 787 2019-03-28  Alan Modra  <amodra@gmail.com>
 788
 789         PR 24390
 790         * ppc-opc.c (BTF): Define.
 791         (powerpc_opcodes): Use for mtfsb*.
 792         * ppc-dis.c (print_insn_powerpc): Print fields with both
 793         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 794
 795 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 796
 797         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 798         (mapping_symbol_for_insn): Implement new algorithm.
 799         (print_insn): Remove duplicate code.
 800
 801 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 802
 803         * aarch64-dis.c (print_insn_aarch64):
 804         Implement override.
 805
 806 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 807
 808         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 809         order.
 810
 811 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 812
 813         * aarch64-dis.c (last_stop_offset): New.
 814         (print_insn_aarch64): Use stop_offset.
 815
 816 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 817
 818         PR gas/24359
 819         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 820         CPU_ANY_AVX2_FLAGS.
 821         * i386-init.h: Regenerated.
 822
 823 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 824
 825         PR gas/24348
 826         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 827         vmovdqu16, vmovdqu32 and vmovdqu64.
 828         * i386-tbl.h: Regenerated.
 829
 830 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 831
 832         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 833         from vstrszb, vstrszh, and vstrszf.
 834
 835 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 836
 837         * s390-opc.txt: Add instruction descriptions.
 838
 839 2019-02-08  Jim Wilson  <jimw@sifive.com>
 840
 841         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 842         <bne>: Likewise.
 843
 844 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 845
 846         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 847
 848 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 849
 850         PR binutils/23212
 851         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 852         * aarch64-opc.c (verify_elem_sd): New.
 853         (fields): Add FLD_sz entr.
 854         * aarch64-tbl.h (_SIMD_INSN): New.
 855         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 856         fmulx scalar and vector by element isns.
 857
 858 2019-02-07  Nick Clifton  <nickc@redhat.com>
 859
 860         * po/sv.po: Updated Swedish translation.
 861
 862 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 863
 864         * s390-mkopc.c (main): Accept arch13 as cpu string.
 865         * s390-opc.c: Add new instruction formats and instruction opcode
 866         masks.
 867         * s390-opc.txt: Add new arch13 instructions.
 868
 869 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 870
 871         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 872         (aarch64_opcode): Change encoding for stg, stzg
 873         st2g and st2zg.
 874         * aarch64-asm-2.c: Regenerated.
 875         * aarch64-dis-2.c: Regenerated.
 876         * aarch64-opc-2.c: Regenerated.
 877
 878 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 879
 880         * aarch64-asm-2.c: Regenerated.
 881         * aarch64-dis-2.c: Likewise.
 882         * aarch64-opc-2.c: Likewise.
 883         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 884
 885 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 886             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 887
 888         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 889         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 890         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 891         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 892         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 893         case for ldstgv_indexed.
 894         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 895         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 896         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 897         * aarch64-asm-2.c: Regenerated.
 898         * aarch64-dis-2.c: Regenerated.
 899         * aarch64-opc-2.c: Regenerated.
 900
 901 2019-01-23  Nick Clifton  <nickc@redhat.com>
 902
 903         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 904
 905 2019-01-21  Nick Clifton  <nickc@redhat.com>
 906
 907         * po/de.po: Updated German translation.
 908         * po/uk.po: Updated Ukranian translation.
 909
 910 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 911         * mips-dis.c (mips_arch_choices): Fix typo in
 912         gs464, gs464e and gs264e descriptors.
 913
 914 2019-01-19  Nick Clifton  <nickc@redhat.com>
 915
 916         * configure: Regenerate.
 917         * po/opcodes.pot: Regenerate.
 918
 919 2018-06-24  Nick Clifton  <nickc@redhat.com>
 920
 921         2.32 branch created.
 922
 923 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 924
 925         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 926         if it is null.
 927         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 928         zero.
 929
 930 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 931
 932         * configure: Regenerate.
 933
 934 2019-01-07  Alan Modra  <amodra@gmail.com>
 935
 936         * configure: Regenerate.
 937         * po/POTFILES.in: Regenerate.
 938
 939 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 940
 941         * s12z-opc.c: New file.
 942         * s12z-opc.h: New file.
 943         * s12z-dis.c: Removed all code not directly related to display
 944         of instructions.  Used the interface provided by the new files
 945         instead.
 946         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 947         * Makefile.in: Regenerate.
 948         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 949         * configure: Regenerate.
 950
 951 2019-01-01  Alan Modra  <amodra@gmail.com>
 952
 953         Update year range in copyright notice of all files.
 954
 955 For older changes see ChangeLog-2018
 956 \f
 957 Copyright (C) 2019 Free Software Foundation, Inc.
 958
 959 Copying and distribution of this file, with or without modification,
 960 are permitted in any medium without royalty provided the copyright
 961 notice and this notice are preserved.
 962
 963 Local Variables:
 964 mode: change-log
 965 left-margin: 8
 966 fill-column: 74
 967 version-control: never
 968 End: