opcodes/ChangeLog

   1 2004-07-27  Tomer Levi  <Tomer.Levi@nsc.com>
   2
   3         * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
   4
   5 2004-07-22  Nick Clifton  <nickc@redhat.com>
   6
   7         PR/280
   8         * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
   9         insns - this is done by objdump itself.
  10         * h8500-dis.c (print_insn_h8500): Likewise.
  11
  12 2004-07-21  Jan Beulich <jbeulich@novell.com>
  13
  14         * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
  15         regardless of address size prefix in effect.
  16         (ptr_reg): Size or address registers does not depend on rex64, but
  17         on the presence of an address size override.
  18         (OP_MMX): Use rex.x only for xmm registers.
  19         (OP_EM): Use rex.z only for xmm registers.
  20
  21 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
  22
  23         * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
  24         move/branch operations to the bottom so that VR5400 multimedia
  25         instructions take precedence in disassembly.
  26
  27 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
  28
  29         * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
  30         ISA-specific "break" encoding.
  31
  32 2004-07-13  Elvis Chiang  <elvisfb@gmail.com>
  33
  34         * arm-opc.h: Fix typo in comment.
  35
  36 2004-07-11  Andreas Schwab  <schwab@suse.de>
  37
  38         * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
  39
  40 2004-07-09  Andreas Schwab  <schwab@suse.de>
  41
  42         * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
  43
  44 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
  45
  46         * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
  47         (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
  48         (crx-dis.lo): New target.
  49         (crx-opc.lo): Likewise.
  50         * Makefile.in: Regenerate.
  51         * configure.in: Handle bfd_crx_arch.
  52         * configure: Regenerate.
  53         * crx-dis.c: New file.
  54         * crx-opc.c: New file.
  55         * disassemble.c (ARCH_crx): Define.
  56         (disassembler): Handle ARCH_crx.
  57
  58 2004-06-29  James E Wilson  <wilson@specifixinc.com>
  59
  60         * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
  61         * ia64-asmtab.c: Regnerate.
  62
  63 2004-06-28  Alan Modra  <amodra@bigpond.net.au>
  64
  65         * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
  66         (extract_fxm): Don't test dialect.
  67         (XFXFXM_MASK): Include the power4 bit.
  68         (XFXM): Add p4 param.
  69         (powerpc_opcodes): Add mfocrf and mtocrf.  Adjust mtcr.
  70
  71 2004-06-27  Alexandre Oliva  <aoliva@redhat.com>
  72
  73         2003-07-21  Richard Sandiford  <rsandifo@redhat.com>
  74         * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
  75
  76 2004-06-26  Alan Modra  <amodra@bigpond.net.au>
  77
  78         * ppc-opc.c (BH, XLBH_MASK): Define.
  79         (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
  80
  81 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
  82
  83         * i386-dis.c (x_mode): Comment.
  84         (two_source_ops): File scope.
  85         (float_mem): Correct fisttpll and fistpll.
  86         (float_mem_mode): New table.
  87         (dofloat): Use it.
  88         (OP_E): Correct intel mode PTR output.
  89         (ptr_reg): Use open_char and close_char.
  90         (PNI_Fixup): Handle possible suffix on sidt.  Use op1out etc. for
  91         operands.  Set two_source_ops.
  92
  93 2004-06-15  Alan Modra  <amodra@bigpond.net.au>
  94
  95         * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
  96         instead of _raw_size.
  97
  98 2004-06-08  Jakub Jelinek  <jakub@redhat.com>
  99
 100         * ia64-gen.c (in_iclass): Handle more postinc st
 101         and ld variants.
 102         * ia64-asmtab.c: Rebuilt.
 103
 104 2004-06-01  Martin Schwidefsky  <schwidefsky@de.ibm.com>
 105
 106         * s390-opc.txt: Correct architecture mask for some opcodes.
 107         lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
 108         in the esa mode as well.
 109
 110 2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
 111
 112         * sh-dis.c (target_arch): Make unsigned.
 113         (print_insn_sh): Replace (most of) switch with a call to
 114         sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
 115         * sh-opc.h: Redefine architecture flags values.
 116         Add sh3-nommu architecture.
 117         Reorganise <arch>_up macros so they make more visual sense.
 118         (SH_MERGE_ARCH_SET): Define new macro.
 119         (SH_VALID_BASE_ARCH_SET): Likewise.
 120         (SH_VALID_MMU_ARCH_SET): Likewise.
 121         (SH_VALID_CO_ARCH_SET): Likewise.
 122         (SH_VALID_ARCH_SET): Likewise.
 123         (SH_MERGE_ARCH_SET_VALID): Likewise.
 124         (SH_ARCH_SET_HAS_FPU): Likewise.
 125         (SH_ARCH_SET_HAS_DSP): Likewise.
 126         (SH_ARCH_UNKNOWN_ARCH): Likewise.
 127         (sh_get_arch_from_bfd_mach): Add prototype.
 128         (sh_get_arch_up_from_bfd_mach): Likewise.
 129         (sh_get_bfd_mach_from_arch_set): Likewise.
 130         (sh_merge_bfd_arc): Likewise.
 131
 132 2004-05-24  Peter Barada  <peter@the-baradas.com>
 133
 134         * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
 135         into new match_insn_m68k function.  Loop over canidate
 136         matches and select first that completely matches.
 137         * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
 138         * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
 139         to verify addressing for MAC/EMAC.
 140         * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
 141         reigster halves since 'fpu' and 'spl' look misleading.
 142         * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
 143         * m68k-opc.c: Rearragne mac/emac cases to use longest for
 144         first, tighten up match masks.
 145         * m68k-opc.c: Add 'size' field to struct m68k_opcode.  Produce
 146         'size' from special case code in print_insn_m68k to
 147         determine decode size of insns.
 148
 149 2004-05-19  Alan Modra  <amodra@bigpond.net.au>
 150
 151         * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
 152         well as when -mpower4.
 153
 154 2004-05-13  Nick Clifton  <nickc@redhat.com>
 155
 156         * po/fr.po: Updated French translation.
 157
 158 2004-05-05  Peter Barada  <peter@the-baradas.com>
 159
 160         * m68k-dis.c(print_insn_m68k): Add new chips, use core
 161         variants in arch_mask.  Only set m68881/68851 for 68k chips.
 162         * m68k-op.c: Switch from ColdFire chips to core variants.
 163
 164 2004-05-05  Alan Modra  <amodra@bigpond.net.au>
 165
 166         PR 147.
 167         * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
 168
 169 2004-04-29  Ben Elliston  <bje@au.ibm.com>
 170
 171         * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
 172         (powerpc_opcodes): Add "dbczl" instruction for PPC970.
 173
 174 2004-04-22  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
 175
 176         * sh-dis.c (print_insn_sh): Print the value in constant pool
 177         as a symbol if it looks like a symbol.
 178
 179 2004-04-22  Peter Barada <peter@the-baradas.com>
 180
 181         * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
 182         appropriate ColdFire architectures.
 183         (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
 184         mask addressing.
 185         Add EMAC instructions, fix MAC instructions. Remove
 186         macmw/macml/msacmw/msacml instructions since mask addressing now
 187         supported.
 188
 189 2004-04-20  Jakub Jelinek  <jakub@redhat.com>
 190
 191         * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
 192         (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
 193         suffix.  Use fmov*x macros, create all 3 fpsize variants in one
 194         macro.  Adjust all users.
 195
 196 2004-04-15  Anil Paranjpe  <anilp1@kpitcummins.com>
 197
 198         * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
 199         separately.
 200
 201 2004-03-30  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 202
 203         * m32r-asm.c: Regenerate.
 204
 205 2004-03-29  Stan Shebs  <shebs@apple.com>
 206
 207         * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
 208         used.
 209
 210 2004-03-19  Alan Modra  <amodra@bigpond.net.au>
 211
 212         * aclocal.m4: Regenerate.
 213         * config.in: Regenerate.
 214         * configure: Regenerate.
 215         * po/POTFILES.in: Regenerate.
 216         * po/opcodes.pot: Regenerate.
 217
 218 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 219
 220         * ppc-dis.c (print_insn_powerpc): Don't print tabs.  Handle
 221         PPC_OPERANDS_GPR_0.
 222         * ppc-opc.c (RA0): Define.
 223         (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
 224         (RAOPT): Rename from RAO.  Update all uses.
 225         (powerpc_opcodes): Use RA0 as appropriate.
 226
 227 2004-03-15  Aldy Hernandez  <aldyh@redhat.com>
 228
 229         * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
 230
 231 2004-03-15  Alan Modra  <amodra@bigpond.net.au>
 232
 233         * sparc-dis.c (print_insn_sparc): Update getword prototype.
 234
 235 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 236
 237         * i386-dis.c (GRPPLOCK): Delete.
 238         (grps): Delete GRPPLOCK entry.
 239
 240 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 241
 242         * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
 243         (M, Mp): Use OP_M.
 244         (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
 245         (GRPPADLCK): Define.
 246         (dis386): Use NOP_Fixup on "nop".
 247         (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
 248         (twobyte_has_modrm): Set for 0xa7.
 249         (padlock_table): Delete.  Move to..
 250         (grps): ..here, using OP_0f07.  Use OP_Ofae on lfence, mfence
 251         and clflush.
 252         (print_insn): Revert PADLOCK_SPECIAL code.
 253         (OP_E): Delete sfence, lfence, mfence checks.
 254
 255 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 256
 257         * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
 258         (INVLPG_Fixup): New function.
 259         (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
 260
 261 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 262
 263         * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
 264         (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
 265         (padlock_table): New struct with PadLock instructions.
 266         (print_insn): Handle PADLOCK_SPECIAL.
 267
 268 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 269
 270         * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
 271         (OP_E): Twiddle clflush to sfence here.
 272
 273 2004-03-08  Nick Clifton  <nickc@redhat.com>
 274
 275         * po/de.po: Updated German translation.
 276
 277 2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
 278
 279         * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
 280         nofpu mode.  Add BFD type bfd_mach_sh4_nommu_nofpu.
 281         * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
 282         accordingly.
 283
 284 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 285
 286         * frv-asm.c: Regenerate.
 287         * frv-desc.c: Regenerate.
 288         * frv-desc.h: Regenerate.
 289         * frv-dis.c: Regenerate.
 290         * frv-ibld.c: Regenerate.
 291         * frv-opc.c: Regenerate.
 292         * frv-opc.h: Regenerate.
 293
 294 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 295
 296         * frv-desc.c, frv-opc.c: Regenerate.
 297
 298 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 299
 300         * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
 301
 302 2004-02-26  Andrew Stubbs  <andrew.stubbs@superh.com>
 303
 304         * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
 305         Also correct mistake in the comment.
 306
 307 2004-02-26  Andrew Stubbs <andrew.stubbs@superh.com>
 308
 309         * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
 310         ensure that double registers have even numbers.
 311         Add REG_N_B01 for nn01 (binary 01) nibble to ensure
 312         that reserved instruction 0xfffd does not decode the same
 313         as 0xfdfd (ftrv).
 314         * sh-opc.h: Add REG_N_D nibble type and use it whereever
 315         REG_N refers to a double register.
 316         Add REG_N_B01 nibble type and use it instead of REG_NM
 317         in ftrv.
 318         Adjust the bit patterns in a few comments.
 319
 320 2004-02-25  Aldy Hernandez  <aldyh@redhat.com>
 321
 322         * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
 323
 324 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 325
 326         * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
 327
 328 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 329
 330         * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
 331
 332 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 333
 334         * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
 335         mtivor32, mtivor33, mtivor34.
 336
 337 2004-02-19  Aldy Hernandez  <aldyh@redhat.com>
 338
 339         * ppc-opc.c (powerpc_opcodes): Add mfmcar.
 340
 341 2004-02-10  Petko Manolov  <petkan@nucleusys.com>
 342
 343         * arm-opc.h Maverick accumulator register opcode fixes.
 344
 345 2004-02-13  Ben Elliston  <bje@wasabisystems.com>
 346
 347         * m32r-dis.c: Regenerate.
 348
 349 2004-01-27  Michael Snyder  <msnyder@redhat.com>
 350
 351         * sh-opc.h (sh_table): "fsrra", not "fssra".
 352
 353 2004-01-23  Andrew Over <andrew.over@cs.anu.edu.au>
 354
 355         * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
 356         contraints.
 357
 358 2004-01-19  Andrew Over  <andrew.over@cs.anu.edu.au>
 359
 360         * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
 361
 362 2004-01-19  Alan Modra  <amodra@bigpond.net.au>
 363
 364         * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
 365         1.  Don't print scale factor on AT&T mode when index missing.
 366
 367 2004-01-16  Alexandre Oliva  <aoliva@redhat.com>
 368
 369         * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
 370         when loaded into XR registers.
 371
 372 2004-01-14  Richard Sandiford  <rsandifo@redhat.com>
 373
 374         * frv-desc.h: Regenerate.
 375         * frv-desc.c: Regenerate.
 376         * frv-opc.c: Regenerate.
 377
 378 2004-01-13  Michael Snyder  <msnyder@redhat.com>
 379
 380         * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
 381
 382 2004-01-09  Paul Brook  <paul@codesourcery.com>
 383
 384         * arm-opc.h (arm_opcodes): Move generic mcrr after known
 385         specific opcodes.
 386
 387 2004-01-07  Daniel Jacobowitz  <drow@mvista.com>
 388
 389         * Makefile.am (libopcodes_la_DEPENDENCIES)
 390         (libopcodes_la_LIBADD): Revert 2003-05-17 change.  Add explanatory
 391         comment about the problem.
 392         * Makefile.in: Regenerate.
 393
 394 2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
 395
 396         2003-12-19  Alexandre Oliva  <aoliva@redhat.com>
 397         * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
 398         cut&paste errors in shifting/truncating numerical operands.
 399         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 400         * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
 401         (parse_uslo16): Likewise.
 402         (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
 403         (parse_d12): Parse gotoff12 and gotofffuncdesc12.
 404         (parse_s12): Likewise.
 405         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 406         * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
 407         (parse_uslo16): Likewise.
 408         (parse_uhi16): Parse gothi and gotfuncdeschi.
 409         (parse_d12): Parse got12 and gotfuncdesc12.
 410         (parse_s12): Likewise.
 411
 412 2004-01-02  Albert Bartoszko  <albar@nt.kegel.com.pl>
 413
 414         * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
 415         instruction which looks similar to an 'rla' instruction.
 416
 417 For older changes see ChangeLog-0203
 418 \f
 419 Local Variables:
 420 mode: change-log
 421 left-margin: 8
 422 fill-column: 74
 423 version-control: never
 424 End: