1 2020-03-20 Alan Modra <amodra@gmail.com>
3 * metag-dis.c (print_insn_metag): Don't ignore status from
6 2020-03-20 Alan Modra <amodra@gmail.com>
8 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
9 Initialize parts of buffer not written when handling a possible
10 2-byte insn at end of section. Don't attempt decoding of such
11 an insn by the 4-byte machinery.
13 2020-03-20 Alan Modra <amodra@gmail.com>
15 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
16 partially filled buffer. Prevent lookup of 4-byte insns when
17 only VLE 2-byte insns are possible due to section size. Print
18 ".word" rather than ".long" for 2-byte leftovers.
20 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
23 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
25 2020-03-13 Jan Beulich <jbeulich@suse.com>
27 * i386-dis.c (X86_64_0D): Rename to ...
28 (X86_64_0E): ... this.
30 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
32 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
33 * Makefile.in: Regenerated.
35 2020-03-09 Jan Beulich <jbeulich@suse.com>
37 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
39 * i386-tbl.h: Re-generate.
41 2020-03-09 Jan Beulich <jbeulich@suse.com>
43 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
44 vprot*, vpsha*, and vpshl*.
45 * i386-tbl.h: Re-generate.
47 2020-03-09 Jan Beulich <jbeulich@suse.com>
49 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
50 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
51 * i386-tbl.h: Re-generate.
53 2020-03-09 Jan Beulich <jbeulich@suse.com>
55 * i386-gen.c (set_bitfield): Ignore zero-length field names.
56 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
57 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
58 * i386-tbl.h: Re-generate.
60 2020-03-09 Jan Beulich <jbeulich@suse.com>
62 * i386-gen.c (struct template_arg, struct template_instance,
63 struct template_param, struct template, templates,
64 parse_template, expand_templates): New.
65 (process_i386_opcodes): Various local variables moved to
66 expand_templates. Call parse_template and expand_templates.
67 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
68 * i386-tbl.h: Re-generate.
70 2020-03-06 Jan Beulich <jbeulich@suse.com>
72 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
73 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
74 register and memory source templates. Replace VexW= by VexW*
76 * i386-tbl.h: Re-generate.
78 2020-03-06 Jan Beulich <jbeulich@suse.com>
80 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
81 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
82 * i386-tbl.h: Re-generate.
84 2020-03-06 Jan Beulich <jbeulich@suse.com>
86 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
87 * i386-tbl.h: Re-generate.
89 2020-03-06 Jan Beulich <jbeulich@suse.com>
91 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
92 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
93 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
94 VexW0 on SSE2AVX variants.
95 (vmovq): Drop NoRex64 from XMM/XMM variants.
96 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
97 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
99 * i386-tbl.h: Re-generate.
101 2020-03-06 Jan Beulich <jbeulich@suse.com>
103 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
104 * i386-opc.h (Rex64): Delete.
105 (struct i386_opcode_modifier): Remove rex64 field.
106 * i386-opc.tbl (crc32): Drop Rex64.
107 Replace Rex64 with Size64 everywhere else.
108 * i386-tbl.h: Re-generate.
110 2020-03-06 Jan Beulich <jbeulich@suse.com>
112 * i386-dis.c (OP_E_memory): Exclude recording of used address
113 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
114 addressed memory operands for MPX insns.
116 2020-03-06 Jan Beulich <jbeulich@suse.com>
118 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
119 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
120 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
121 (ptwrite): Split into non-64-bit and 64-bit forms.
122 * i386-tbl.h: Re-generate.
124 2020-03-06 Jan Beulich <jbeulich@suse.com>
126 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
128 * i386-tbl.h: Re-generate.
130 2020-03-04 Jan Beulich <jbeulich@suse.com>
132 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
133 (prefix_table): Move vmmcall here. Add vmgexit.
134 (rm_table): Replace vmmcall entry by prefix_table[] escape.
135 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
136 (cpu_flags): Add CpuSEV_ES entry.
137 * i386-opc.h (CpuSEV_ES): New.
138 (union i386_cpu_flags): Add cpusev_es field.
139 * i386-opc.tbl (vmgexit): New.
140 * i386-init.h, i386-tbl.h: Re-generate.
142 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
144 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
146 * i386-opc.h (IGNORESIZE): New.
147 (DEFAULTSIZE): Likewise.
148 (IgnoreSize): Removed.
149 (DefaultSize): Likewise.
151 (i386_opcode_modifier): Replace ignoresize/defaultsize with
153 * i386-opc.tbl (IgnoreSize): New.
154 (DefaultSize): Likewise.
155 * i386-tbl.h: Regenerated.
157 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
160 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
163 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
166 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
167 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
168 * i386-tbl.h: Regenerated.
170 2020-02-26 Alan Modra <amodra@gmail.com>
172 * aarch64-asm.c: Indent labels correctly.
173 * aarch64-dis.c: Likewise.
174 * aarch64-gen.c: Likewise.
175 * aarch64-opc.c: Likewise.
176 * alpha-dis.c: Likewise.
177 * i386-dis.c: Likewise.
178 * nds32-asm.c: Likewise.
179 * nfp-dis.c: Likewise.
180 * visium-dis.c: Likewise.
182 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
184 * arc-regs.h (int_vector_base): Make it available for all ARC
187 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
189 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
192 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
194 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
195 c.mv/c.li if rs1 is zero.
197 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
199 * i386-gen.c (cpu_flag_init): Replace CpuABM with
200 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
202 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
203 * i386-opc.h (CpuABM): Removed.
205 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
206 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
207 popcnt. Remove CpuABM from lzcnt.
208 * i386-init.h: Regenerated.
209 * i386-tbl.h: Likewise.
211 2020-02-17 Jan Beulich <jbeulich@suse.com>
213 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
214 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
215 VexW1 instead of open-coding them.
216 * i386-tbl.h: Re-generate.
218 2020-02-17 Jan Beulich <jbeulich@suse.com>
220 * i386-opc.tbl (AddrPrefixOpReg): Define.
221 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
222 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
223 templates. Drop NoRex64.
224 * i386-tbl.h: Re-generate.
226 2020-02-17 Jan Beulich <jbeulich@suse.com>
229 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
230 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
231 into Intel syntax instance (with Unpsecified) and AT&T one
233 (vcvtneps2bf16): Likewise, along with folding the two so far
235 * i386-tbl.h: Re-generate.
237 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
239 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
242 2020-02-17 Alan Modra <amodra@gmail.com>
244 * i386-gen.c (cpu_flag_init): Correct last change.
246 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
248 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
251 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
253 * i386-opc.tbl (movsx): Remove Intel syntax comments.
256 2020-02-14 Jan Beulich <jbeulich@suse.com>
259 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
260 destination for Cpu64-only variant.
261 (movzx): Fold patterns.
262 * i386-tbl.h: Re-generate.
264 2020-02-13 Jan Beulich <jbeulich@suse.com>
266 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
267 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
268 CPU_ANY_SSE4_FLAGS entry.
269 * i386-init.h: Re-generate.
271 2020-02-12 Jan Beulich <jbeulich@suse.com>
273 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
274 with Unspecified, making the present one AT&T syntax only.
275 * i386-tbl.h: Re-generate.
277 2020-02-12 Jan Beulich <jbeulich@suse.com>
279 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
280 * i386-tbl.h: Re-generate.
282 2020-02-12 Jan Beulich <jbeulich@suse.com>
285 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
286 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
287 Amd64 and Intel64 templates.
288 (call, jmp): Likewise for far indirect variants. Dro
290 * i386-tbl.h: Re-generate.
292 2020-02-11 Jan Beulich <jbeulich@suse.com>
294 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
295 * i386-opc.h (ShortForm): Delete.
296 (struct i386_opcode_modifier): Remove shortform field.
297 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
298 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
299 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
300 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
302 * i386-tbl.h: Re-generate.
304 2020-02-11 Jan Beulich <jbeulich@suse.com>
306 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
307 fucompi): Drop ShortForm from operand-less templates.
308 * i386-tbl.h: Re-generate.
310 2020-02-11 Alan Modra <amodra@gmail.com>
312 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
313 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
314 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
315 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
316 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
318 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
320 * arm-dis.c (print_insn_cde): Define 'V' parse character.
321 (cde_opcodes): Add VCX* instructions.
323 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
324 Matthew Malcomson <matthew.malcomson@arm.com>
326 * arm-dis.c (struct cdeopcode32): New.
327 (CDE_OPCODE): New macro.
328 (cde_opcodes): New disassembly table.
329 (regnames): New option to table.
330 (cde_coprocs): New global variable.
331 (print_insn_cde): New
332 (print_insn_thumb32): Use print_insn_cde.
333 (parse_arm_disassembler_options): Parse coprocN args.
335 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
338 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
340 * i386-opc.h (AMD64): Removed.
344 (INTEL64ONLY): Likewise.
345 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
346 * i386-opc.tbl (Amd64): New.
348 (Intel64Only): Likewise.
349 Replace AMD64 with Amd64. Update sysenter/sysenter with
350 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
351 * i386-tbl.h: Regenerated.
353 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
356 * z80-dis.c: Add support for GBZ80 opcodes.
358 2020-02-04 Alan Modra <amodra@gmail.com>
360 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
362 2020-02-03 Alan Modra <amodra@gmail.com>
364 * m32c-ibld.c: Regenerate.
366 2020-02-01 Alan Modra <amodra@gmail.com>
368 * frv-ibld.c: Regenerate.
370 2020-01-31 Jan Beulich <jbeulich@suse.com>
372 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
373 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
374 (OP_E_memory): Replace xmm_mdq_mode case label by
375 vex_scalar_w_dq_mode one.
376 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
378 2020-01-31 Jan Beulich <jbeulich@suse.com>
380 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
381 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
382 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
383 (intel_operand_size): Drop vex_w_dq_mode case label.
385 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
387 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
388 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
390 2020-01-30 Alan Modra <amodra@gmail.com>
392 * m32c-ibld.c: Regenerate.
394 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
396 * bpf-opc.c: Regenerate.
398 2020-01-30 Jan Beulich <jbeulich@suse.com>
400 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
401 (dis386): Use them to replace C2/C3 table entries.
402 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
403 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
404 ones. Use Size64 instead of DefaultSize on Intel64 ones.
405 * i386-tbl.h: Re-generate.
407 2020-01-30 Jan Beulich <jbeulich@suse.com>
409 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
411 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
413 * i386-tbl.h: Re-generate.
415 2020-01-30 Alan Modra <amodra@gmail.com>
417 * tic4x-dis.c (tic4x_dp): Make unsigned.
419 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
420 Jan Beulich <jbeulich@suse.com>
423 * i386-dis.c (MOVSXD_Fixup): New function.
424 (movsxd_mode): New enum.
425 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
426 (intel_operand_size): Handle movsxd_mode.
427 (OP_E_register): Likewise.
429 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
430 register on movsxd. Add movsxd with 16-bit destination register
431 for AMD64 and Intel64 ISAs.
432 * i386-tbl.h: Regenerated.
434 2020-01-27 Tamar Christina <tamar.christina@arm.com>
437 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
438 * aarch64-asm-2.c: Regenerate
439 * aarch64-dis-2.c: Likewise.
440 * aarch64-opc-2.c: Likewise.
442 2020-01-21 Jan Beulich <jbeulich@suse.com>
444 * i386-opc.tbl (sysret): Drop DefaultSize.
445 * i386-tbl.h: Re-generate.
447 2020-01-21 Jan Beulich <jbeulich@suse.com>
449 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
451 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
452 * i386-tbl.h: Re-generate.
454 2020-01-20 Nick Clifton <nickc@redhat.com>
456 * po/de.po: Updated German translation.
457 * po/pt_BR.po: Updated Brazilian Portuguese translation.
458 * po/uk.po: Updated Ukranian translation.
460 2020-01-20 Alan Modra <amodra@gmail.com>
462 * hppa-dis.c (fput_const): Remove useless cast.
464 2020-01-20 Alan Modra <amodra@gmail.com>
466 * arm-dis.c (print_insn_arm): Wrap 'T' value.
468 2020-01-18 Nick Clifton <nickc@redhat.com>
470 * configure: Regenerate.
471 * po/opcodes.pot: Regenerate.
473 2020-01-18 Nick Clifton <nickc@redhat.com>
475 Binutils 2.34 branch created.
477 2020-01-17 Christian Biesinger <cbiesinger@google.com>
479 * opintl.h: Fix spelling error (seperate).
481 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
483 * i386-opc.tbl: Add {vex} pseudo prefix.
484 * i386-tbl.h: Regenerated.
486 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
489 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
490 (neon_opcodes): Likewise.
491 (select_arm_features): Make sure we enable MVE bits when selecting
492 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
495 2020-01-16 Jan Beulich <jbeulich@suse.com>
497 * i386-opc.tbl: Drop stale comment from XOP section.
499 2020-01-16 Jan Beulich <jbeulich@suse.com>
501 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
502 (extractps): Add VexWIG to SSE2AVX forms.
503 * i386-tbl.h: Re-generate.
505 2020-01-16 Jan Beulich <jbeulich@suse.com>
507 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
508 Size64 from and use VexW1 on SSE2AVX forms.
509 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
510 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
511 * i386-tbl.h: Re-generate.
513 2020-01-15 Alan Modra <amodra@gmail.com>
515 * tic4x-dis.c (tic4x_version): Make unsigned long.
516 (optab, optab_special, registernames): New file scope vars.
517 (tic4x_print_register): Set up registernames rather than
518 malloc'd registertable.
519 (tic4x_disassemble): Delete optable and optable_special. Use
520 optab and optab_special instead. Throw away old optab,
521 optab_special and registernames when info->mach changes.
523 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
526 * z80-dis.c (suffix): Use .db instruction to generate double
529 2020-01-14 Alan Modra <amodra@gmail.com>
531 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
532 values to unsigned before shifting.
534 2020-01-13 Thomas Troeger <tstroege@gmx.de>
536 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
538 (print_insn_thumb16, print_insn_thumb32): Likewise.
539 (print_insn): Initialize the insn info.
540 * i386-dis.c (print_insn): Initialize the insn info fields, and
543 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
545 * arc-opc.c (C_NE): Make it required.
547 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
549 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
550 reserved register name.
552 2020-01-13 Alan Modra <amodra@gmail.com>
554 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
555 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
557 2020-01-13 Alan Modra <amodra@gmail.com>
559 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
560 result of wasm_read_leb128 in a uint64_t and check that bits
561 are not lost when copying to other locals. Use uint32_t for
562 most locals. Use PRId64 when printing int64_t.
564 2020-01-13 Alan Modra <amodra@gmail.com>
566 * score-dis.c: Formatting.
567 * score7-dis.c: Formatting.
569 2020-01-13 Alan Modra <amodra@gmail.com>
571 * score-dis.c (print_insn_score48): Use unsigned variables for
572 unsigned values. Don't left shift negative values.
573 (print_insn_score32): Likewise.
574 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
576 2020-01-13 Alan Modra <amodra@gmail.com>
578 * tic4x-dis.c (tic4x_print_register): Remove dead code.
580 2020-01-13 Alan Modra <amodra@gmail.com>
582 * fr30-ibld.c: Regenerate.
584 2020-01-13 Alan Modra <amodra@gmail.com>
586 * xgate-dis.c (print_insn): Don't left shift signed value.
587 (ripBits): Formatting, use 1u.
589 2020-01-10 Alan Modra <amodra@gmail.com>
591 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
592 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
594 2020-01-10 Alan Modra <amodra@gmail.com>
596 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
597 and XRREG value earlier to avoid a shift with negative exponent.
598 * m10200-dis.c (disassemble): Similarly.
600 2020-01-09 Nick Clifton <nickc@redhat.com>
603 * z80-dis.c (ld_ii_ii): Use correct cast.
605 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
608 * z80-dis.c (ld_ii_ii): Use character constant when checking
611 2020-01-09 Jan Beulich <jbeulich@suse.com>
613 * i386-dis.c (SEP_Fixup): New.
615 (dis386_twobyte): Use it for sysenter/sysexit.
616 (enum x86_64_isa): Change amd64 enumerator to value 1.
617 (OP_J): Compare isa64 against intel64 instead of amd64.
618 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
620 * i386-tbl.h: Re-generate.
622 2020-01-08 Alan Modra <amodra@gmail.com>
624 * z8k-dis.c: Include libiberty.h
625 (instr_data_s): Make max_fetched unsigned.
626 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
627 Don't exceed byte_info bounds.
628 (output_instr): Make num_bytes unsigned.
629 (unpack_instr): Likewise for nibl_count and loop.
630 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
632 * z8k-opc.h: Regenerate.
634 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
636 * arc-tbl.h (llock): Use 'LLOCK' as class.
638 (scond): Use 'SCOND' as class.
640 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
643 2020-01-06 Alan Modra <amodra@gmail.com>
645 * m32c-ibld.c: Regenerate.
647 2020-01-06 Alan Modra <amodra@gmail.com>
650 * z80-dis.c (suffix): Don't use a local struct buffer copy.
651 Peek at next byte to prevent recursion on repeated prefix bytes.
652 Ensure uninitialised "mybuf" is not accessed.
653 (print_insn_z80): Don't zero n_fetch and n_used here,..
654 (print_insn_z80_buf): ..do it here instead.
656 2020-01-04 Alan Modra <amodra@gmail.com>
658 * m32r-ibld.c: Regenerate.
660 2020-01-04 Alan Modra <amodra@gmail.com>
662 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
664 2020-01-04 Alan Modra <amodra@gmail.com>
666 * crx-dis.c (match_opcode): Avoid shift left of signed value.
668 2020-01-04 Alan Modra <amodra@gmail.com>
670 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
672 2020-01-03 Jan Beulich <jbeulich@suse.com>
674 * aarch64-tbl.h (aarch64_opcode_table): Use
675 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
677 2020-01-03 Jan Beulich <jbeulich@suse.com>
679 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
680 forms of SUDOT and USDOT.
682 2020-01-03 Jan Beulich <jbeulich@suse.com>
684 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
686 * opcodes/aarch64-dis-2.c: Re-generate.
688 2020-01-03 Jan Beulich <jbeulich@suse.com>
690 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
692 * opcodes/aarch64-dis-2.c: Re-generate.
694 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
696 * z80-dis.c: Add support for eZ80 and Z80 instructions.
698 2020-01-01 Alan Modra <amodra@gmail.com>
700 Update year range in copyright notice of all files.
702 For older changes see ChangeLog-2019
704 Copyright (C) 2020 Free Software Foundation, Inc.
706 Copying and distribution of this file, with or without modification,
707 are permitted in any medium without royalty provided the copyright
708 notice and this notice are preserved.
714 version-control: never