opcodes/ChangeLog

   1 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
   2
   3         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
   4         cmode 1101.
   5         (is_mve_encoding_conflict): Update cmode conflict checks for
   6         MVE_VMVN_IMM.
   7
   8 2019-11-12  Jan Beulich  <jbeulich@suse.com>
   9
  10         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
  11         entry.
  12         (operand_types): Remove EsSeg entry.
  13         (main): Replace stale use of OTMax.
  14         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
  15         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
  16         (EsSeg): Delete.
  17         (OTUnused): Comment out.
  18         (union i386_operand_type): Remove esseg field.
  19         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
  20         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
  21         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
  22         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
  23         * i386-init.h, i386-tbl.h: Re-generate.
  24
  25 2019-11-12  Jan Beulich  <jbeulich@suse.com>
  26
  27         * i386-gen.c (operand_instances): Add RegB entry.
  28         * i386-opc.h (enum operand_instance): Add RegB.
  29         * i386-opc.tbl (RegC, RegD, RegB): Define.
  30         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
  31         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
  32         monitorx, mwaitx): Drop ImmExt and convert encodings
  33         accordingly.
  34         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
  35         (edx, rdx): Add Instance=RegD.
  36         (ebx, rbx): Add Instance=RegB.
  37         * i386-tbl.h: Re-generate.
  38
  39 2019-11-12  Jan Beulich  <jbeulich@suse.com>
  40
  41         * i386-gen.c (operand_type_init): Adjust
  42         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
  43         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
  44         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
  45         (operand_instances): New.
  46         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
  47         (output_operand_type): New parameter "instance". Process it.
  48         (process_i386_operand_type): New local variable "instance".
  49         (main): Adjust static assertions.
  50         * i386-opc.h (INSTANCE_WIDTH): Define.
  51         (enum operand_instance): New.
  52         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
  53         (union i386_operand_type): Replace acc, inoutportreg, and
  54         shiftcount by instance.
  55         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
  56         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
  57         Add Instance=.
  58         * i386-init.h, i386-tbl.h: Re-generate.
  59
  60 2019-11-11  Jan Beulich  <jbeulich@suse.com>
  61
  62         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
  63         smaxp/sminp entries' "tied_operand" field to 2.
  64
  65 2019-11-11  Jan Beulich  <jbeulich@suse.com>
  66
  67         * aarch64-opc.c (operand_general_constraint_met_p): Replace
  68         "index" local variable by that of the already existing "num".
  69
  70 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
  71
  72         PR gas/25167
  73         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
  74         * i386-tbl.h: Regenerated.
  75
  76 2019-11-08  Jan Beulich  <jbeulich@suse.com>
  77
  78         * i386-gen.c (operand_type_init): Add Class= to
  79         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
  80         OPERAND_TYPE_REGBND entry.
  81         (operand_classes): Add RegMask and RegBND entries.
  82         (operand_types): Drop RegMask and RegBND entry.
  83         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
  84         (RegMask, RegBND): Delete.
  85         (union i386_operand_type): Remove regmask and regbnd fields.
  86         * i386-opc.tbl (RegMask, RegBND): Define.
  87         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
  88         Class=RegBND.
  89         * i386-init.h, i386-tbl.h: Re-generate.
  90
  91 2019-11-08  Jan Beulich  <jbeulich@suse.com>
  92
  93         * i386-gen.c (operand_type_init): Add Class= to
  94         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
  95         OPERAND_TYPE_REGZMM entries.
  96         (operand_classes): Add RegMMX and RegSIMD entries.
  97         (operand_types): Drop RegMMX and RegSIMD entries.
  98         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
  99         (RegMMX, RegSIMD): Delete.
 100         (union i386_operand_type): Remove regmmx and regsimd fields.
 101         * i386-opc.tbl (RegMMX): Define.
 102         (RegXMM, RegYMM, RegZMM): Add Class=.
 103         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 104         Class=RegSIMD.
 105         * i386-init.h, i386-tbl.h: Re-generate.
 106
 107 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 108
 109         * i386-gen.c (operand_type_init): Add Class= to
 110         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 111         entries.
 112         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 113         (operand_types): Drop Control, Debug, and Test entries.
 114         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 115         (Control, Debug, Test): Delete.
 116         (union i386_operand_type): Remove control, debug, and test
 117         fields.
 118         * i386-opc.tbl (Control, Debug, Test): Define.
 119         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 120         Class=RegDR, and Test by Class=RegTR.
 121         * i386-init.h, i386-tbl.h: Re-generate.
 122
 123 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 124
 125         * i386-gen.c (operand_type_init): Add Class= to
 126         OPERAND_TYPE_SREG entry.
 127         (operand_classes): Add SReg entry.
 128         (operand_types): Drop SReg entry.
 129         * i386-opc.h (enum operand_class): Add SReg.
 130         (SReg): Delete.
 131         (union i386_operand_type): Remove sreg field.
 132         * i386-opc.tbl (SReg): Define.
 133         * i386-reg.tbl: Replace SReg by Class=SReg.
 134         * i386-init.h, i386-tbl.h: Re-generate.
 135
 136 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 137
 138         * i386-gen.c (operand_type_init): Add Class=. New
 139         OPERAND_TYPE_ANYIMM entry.
 140         (operand_classes): New.
 141         (operand_types): Drop Reg entry.
 142         (output_operand_type): New parameter "class". Process it.
 143         (process_i386_operand_type): New local variable "class".
 144         (main): Adjust static assertions.
 145         * i386-opc.h (CLASS_WIDTH): Define.
 146         (enum operand_class): New.
 147         (Reg): Replace by Class. Adjust comment.
 148         (union i386_operand_type): Replace reg by class.
 149         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 150         Class=.
 151         * i386-reg.tbl: Replace Reg by Class=Reg.
 152         * i386-init.h: Re-generate.
 153
 154 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 155
 156         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 157         (aarch64_opcode_table): Add data gathering hint mnemonic.
 158         * opcodes/aarch64-dis-2.c: Account for new instruction.
 159
 160 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 161
 162         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 163
 164
 165 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 166
 167         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 168         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 169         aarch64_feature_f64mm): New feature sets.
 170         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 171         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 172         instructions.
 173         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 174         macros.
 175         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 176         (OP_SVE_QQQ): New qualifier.
 177         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 178         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 179         the movprfx constraint.
 180         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 181         (aarch64_opcode_table): Define new instructions smmla,
 182         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 183         uzip{1/2}, trn{1/2}.
 184         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 185         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 186         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 187         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 188         Account for new instructions.
 189         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 190         S4x32 operand.
 191         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 192
 193 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 194 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 195
 196         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 197         Armv8.6-A.
 198         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 199         (neon_opcodes): Add bfloat SIMD instructions.
 200         (print_insn_coprocessor): Add new control character %b to print
 201         condition code without checking cp_num.
 202         (print_insn_neon): Account for BFloat16 instructions that have no
 203         special top-byte handling.
 204
 205 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 206 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 207
 208         * arm-dis.c (print_insn_coprocessor,
 209         print_insn_generic_coprocessor): Create wrapper functions around
 210         the implementation of the print_insn_coprocessor control codes.
 211         (print_insn_coprocessor_1): Original print_insn_coprocessor
 212         function that now takes which array to look at as an argument.
 213         (print_insn_arm): Use both print_insn_coprocessor and
 214         print_insn_generic_coprocessor.
 215         (print_insn_thumb32): As above.
 216
 217 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 218 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 219
 220         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 221         in reglane special case.
 222         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 223         aarch64_find_next_opcode): Account for new instructions.
 224         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 225         in reglane special case.
 226         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 227         new AARCH64_OPND_QLF_S_2H qualifier.
 228         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 229         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 230         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 231         sets.
 232         (BFLOAT_SVE, BFLOAT): New feature set macros.
 233         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 234         instructions.
 235         (aarch64_opcode_table): Define new instructions bfdot,
 236         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 237         bfcvtn2, bfcvt.
 238
 239 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 240 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 241
 242         * aarch64-tbl.h (ARMV8_6): New macro.
 243
 244 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 245
 246         * i386-dis.c (prefix_table): Add mcommit.
 247         (rm_table): Add rdpru.
 248         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 249         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 250         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 251         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 252         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 253         * i386-opc.tbl (mcommit, rdpru): New.
 254         * i386-init.h, i386-tbl.h: Re-generate.
 255
 256 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 257
 258         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 259         "names32" instead.
 260         (OP_Monitor): Drop local variable "op1_names", re-purpose
 261         "names" for it instead, and replace former "names" uses by
 262         "names32" ones.
 263
 264 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 265
 266         PR/gas 25167
 267         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 268         operand-less forms.
 269         * opcodes/i386-tbl.h: Re-generate.
 270
 271 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 272
 273         * i386-dis.c (OP_Mwaitx): Delete.
 274         (prefix_table): Use OP_Mwait for mwaitx entry.
 275         (OP_Mwait): Also handle mwaitx.
 276
 277 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 278
 279         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 280         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 281         (prefix_table): Add respective entries.
 282         (rm_table): Link to those entries.
 283
 284 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 285
 286         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 287         (REG_0F1C_P_0_MOD_0): ... this.
 288         (REG_0F1E_MOD_3): Rename to ...
 289         (REG_0F1E_P_1_MOD_3): ... this.
 290         (RM_0F01_REG_5): Rename to ...
 291         (RM_0F01_REG_5_MOD_3): ... this.
 292         (RM_0F01_REG_7): Rename to ...
 293         (RM_0F01_REG_7_MOD_3): ... this.
 294         (RM_0F1E_MOD_3_REG_7): Rename to ...
 295         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 296         (RM_0FAE_REG_6): Rename to ...
 297         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 298         (RM_0FAE_REG_7): Rename to ...
 299         (RM_0FAE_REG_7_MOD_3): ... this.
 300         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 301         (PREFIX_0F01_REG_5_MOD_0): ... this.
 302         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 303         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 304         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 305         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 306         (PREFIX_0FAE_REG_0): Rename to ...
 307         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 308         (PREFIX_0FAE_REG_1): Rename to ...
 309         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 310         (PREFIX_0FAE_REG_2): Rename to ...
 311         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 312         (PREFIX_0FAE_REG_3): Rename to ...
 313         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 314         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 315         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 316         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 317         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 318         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 319         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 320         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 321         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 322         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 323         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 324         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 325         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 326         (PREFIX_0FAE_REG_7): Rename to ...
 327         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 328         (PREFIX_MOD_0_0FC3): Rename to ...
 329         (PREFIX_0FC3_MOD_0): ... this.
 330         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 331         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 332         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 333         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 334         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 335         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 336         (reg_table, prefix_table, mod_table, rm_table): Adjust
 337         accordingly.
 338
 339 2019-11-04  Nick Clifton  <nickc@redhat.com>
 340
 341         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 342         of a v850 system register.  Move the v850_sreg_names array into
 343         this function.
 344         (get_v850_reg_name): Likewise for ordinary register names.
 345         (get_v850_vreg_name): Likewise for vector register names.
 346         (get_v850_cc_name): Likewise for condition codes.
 347         * get_v850_float_cc_name): Likewise for floating point condition
 348         codes.
 349         (get_v850_cacheop_name): Likewise for cache-ops.
 350         (get_v850_prefop_name): Likewise for pref-ops.
 351         (disassemble): Use the new accessor functions.
 352
 353 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 354
 355         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 356         immediate for the writeback form of ldraa/ldrab if it is 0.
 357         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 358         * aarch64-opc-2.c: Regenerated.
 359
 360 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 361
 362         * i386-gen.c (operand_type_shorthands): Delete.
 363         (operand_type_init): Expand previous shorthands.
 364         (set_bitfield_from_shorthand): Rename back to ...
 365         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 366         of operand_type_init[].
 367         (set_bitfield): Adjust call to the above function.
 368         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 369         RegXMM, RegYMM, RegZMM): Define.
 370         * i386-reg.tbl: Expand prior shorthands.
 371
 372 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 373
 374         * i386-gen.c (output_i386_opcode): Change order of fields
 375         emitted to output.
 376         * i386-opc.h (struct insn_template): Move operands field.
 377         Convert extension_opcode field to unsigned short.
 378         * i386-tbl.h: Re-generate.
 379
 380 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 381
 382         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 383         of W.
 384         * i386-opc.h (W): Extend comment.
 385         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 386         general purpose variants not allowing for byte operands.
 387         * i386-tbl.h: Re-generate.
 388
 389 2019-10-29  Nick Clifton  <nickc@redhat.com>
 390
 391         * tic30-dis.c (print_branch): Correct size of operand array.
 392
 393 2019-10-29  Nick Clifton  <nickc@redhat.com>
 394
 395         * d30v-dis.c (print_insn): Check that operand index is valid
 396         before attempting to access the operands array.
 397
 398 2019-10-29  Nick Clifton  <nickc@redhat.com>
 399
 400         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 401         locating the bit to be tested.
 402
 403 2019-10-29  Nick Clifton  <nickc@redhat.com>
 404
 405         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 406         values.
 407         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 408         (print_insn_s12z):  Check for illegal size values.
 409
 410 2019-10-28  Nick Clifton  <nickc@redhat.com>
 411
 412         * csky-dis.c (csky_chars_to_number): Check for a negative
 413         count. Use an unsigned integer to construct the return value.
 414
 415 2019-10-28  Nick Clifton  <nickc@redhat.com>
 416
 417         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 418         operand buffer.  Set value to 15 not 13.
 419         (get_register_operand): Use OPERAND_BUFFER_LEN.
 420         (get_indirect_operand): Likewise.
 421         (print_two_operand): Likewise.
 422         (print_three_operand): Likewise.
 423         (print_oar_insn): Likewise.
 424
 425 2019-10-28  Nick Clifton  <nickc@redhat.com>
 426
 427         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 428         (bit_extract_simple): Likewise.
 429         (bit_copy): Likewise.
 430         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 431         index_offset array are not accessed.
 432
 433 2019-10-28  Nick Clifton  <nickc@redhat.com>
 434
 435         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 436         operand.
 437
 438 2019-10-25  Nick Clifton  <nickc@redhat.com>
 439
 440         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 441         access to opcodes.op array element.
 442
 443 2019-10-23  Nick Clifton  <nickc@redhat.com>
 444
 445         * rx-dis.c (get_register_name): Fix spelling typo in error
 446         message.
 447         (get_condition_name, get_flag_name, get_double_register_name)
 448         (get_double_register_high_name, get_double_register_low_name)
 449         (get_double_control_register_name, get_double_condition_name)
 450         (get_opsize_name, get_size_name): Likewise.
 451
 452 2019-10-22  Nick Clifton  <nickc@redhat.com>
 453
 454         * rx-dis.c (get_size_name): New function.  Provides safe
 455         access to name array.
 456         (get_opsize_name): Likewise.
 457         (print_insn_rx): Use the accessor functions.
 458
 459 2019-10-16  Nick Clifton  <nickc@redhat.com>
 460
 461         * rx-dis.c (get_register_name): New function.  Provides safe
 462         access to name array.
 463         (get_condition_name, get_flag_name, get_double_register_name)
 464         (get_double_register_high_name, get_double_register_low_name)
 465         (get_double_control_register_name, get_double_condition_name):
 466         Likewise.
 467         (print_insn_rx): Use the accessor functions.
 468
 469 2019-10-09  Nick Clifton  <nickc@redhat.com>
 470
 471         PR 25041
 472         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 473         instructions.
 474
 475 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 476
 477         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 478         (cmpsd): Likewise. Move EsSeg to other operand.
 479         * opcodes/i386-tbl.h: Re-generate.
 480
 481 2019-09-23  Alan Modra  <amodra@gmail.com>
 482
 483         * m68k-dis.c: Include cpu-m68k.h
 484
 485 2019-09-23  Alan Modra  <amodra@gmail.com>
 486
 487         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 488         "elf/mips.h" earlier.
 489
 490 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 491
 492         PR gas/25012
 493         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 494         with SReg operand.
 495         * i386-tbl.h: Re-generate.
 496
 497 2019-09-18  Alan Modra  <amodra@gmail.com>
 498
 499         * arc-ext.c: Update throughout for bfd section macro changes.
 500
 501 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 502
 503         * Makefile.in: Re-generate.
 504         * configure: Re-generate.
 505
 506 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 507
 508         * riscv-opc.c (riscv_opcodes): Change subset field
 509         to insn_class field for all instructions.
 510         (riscv_insn_types): Likewise.
 511
 512 2019-09-16  Phil Blundell  <pb@pbcl.net>
 513
 514         * configure: Regenerated.
 515
 516 2019-09-10  Miod Vallat  <miod@online.fr>
 517
 518         PR 24982
 519         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 520
 521 2019-09-09  Phil Blundell  <pb@pbcl.net>
 522
 523         binutils 2.33 branch created.
 524
 525 2019-09-03  Nick Clifton  <nickc@redhat.com>
 526
 527         PR 24961
 528         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 529         greater than zero before indexing via (bufcnt -1).
 530
 531 2019-09-03  Nick Clifton  <nickc@redhat.com>
 532
 533         PR 24958
 534         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 535         (MAX_SPEC_REG_NAME_LEN): Define.
 536         (struct mmix_dis_info): Use defined constants for array lengths.
 537         (get_reg_name): New function.
 538         (get_sprec_reg_name): New function.
 539         (print_insn_mmix): Use new functions.
 540
 541 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 542
 543         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 544         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 545         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 546
 547 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 548
 549         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 550         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 551         (aarch64_sys_reg_supported_p): Update checks for the above.
 552
 553 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 554
 555         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 556         cases MVE_SQRSHRL and MVE_UQRSHLL.
 557         (print_insn_mve): Add case for specifier 'k' to check
 558         specific bit of the instruction.
 559
 560 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 561
 562         PR 24854
 563         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 564         encountering an unknown machine type.
 565         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 566         cases return -1 rather than calling abort.
 567
 568 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 569
 570         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 571         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 572         IgnoreSize.
 573         * i386-tbl.h: Re-generate.
 574
 575 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 576
 577         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 578         instructions.
 579
 580 2019-07-30  Mel Chen <mel.chen@sifive.com>
 581
 582         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 583         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 584
 585         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 586         fscsr.
 587
 588 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 589
 590         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 591         and MPY class instructions.
 592         (parse_option): Add nps400 option.
 593         (print_arc_disassembler_options): Add nps400 info.
 594
 595 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 596
 597         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 598         (bspop): Likewise.
 599         (modapp): Likewise.
 600         * arc-opc.c (RAD_CHK): Add.
 601         * arc-tbl.h: Regenerate.
 602
 603 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 604
 605         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 606         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 607
 608 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 609
 610         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 611         instructions as UNPREDICTABLE.
 612
 613 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 614
 615         * bpf-desc.c: Regenerated.
 616
 617 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 618
 619         * i386-gen.c (static_assert): Define.
 620         (main): Use it.
 621         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 622         (Opcode_Modifier_Num): ... this.
 623         (Mem): Delete.
 624
 625 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 626
 627         * i386-gen.c (operand_types): Move RegMem ...
 628         (opcode_modifiers): ... here.
 629         * i386-opc.h (RegMem): Move to opcode modifer enum.
 630         (union i386_operand_type): Move regmem field ...
 631         (struct i386_opcode_modifier): ... here.
 632         * i386-opc.tbl (RegMem): Define.
 633         (mov, movq): Move RegMem on segment, control, debug, and test
 634         register flavors.
 635         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 636         to non-SSE2AVX flavor.
 637         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 638         Move RegMem on register only flavors. Drop IgnoreSize from
 639         legacy encoding flavors.
 640         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 641         flavors.
 642         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 643         register only flavors.
 644         (vmovd): Move RegMem and drop IgnoreSize on register only
 645         flavor. Change opcode and operand order to store form.
 646         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 647
 648 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 649
 650         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 651         entries.
 652         * i386-opc.h (SReg2, SReg3): Replace by ...
 653         (SReg): ... this.
 654         (union i386_operand_type): Replace sreg fields.
 655         * i386-opc.tbl (mov, ): Use SReg.
 656         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 657         register flavors.
 658         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 659         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 660
 661 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 662
 663         * bpf-desc.c: Regenerate.
 664         * bpf-opc.c: Likewise.
 665         * bpf-opc.h: Likewise.
 666
 667 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 668
 669         * bpf-desc.c: Regenerate.
 670         * bpf-opc.c: Likewise.
 671
 672 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 673
 674         * arm-dis.c (print_insn_coprocessor): Rename index to
 675         index_operand.
 676
 677 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 678
 679         * riscv-opc.c (riscv_insn_types): Add r4 type.
 680
 681         * riscv-opc.c (riscv_insn_types): Add b and j type.
 682
 683         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 684         format for sb type and correct s type.
 685
 686 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 687
 688         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 689         SVE FMOV alias of FCPY.
 690
 691 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 692
 693         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 694         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 695
 696 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 697
 698         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 699         registers in an instruction prefixed by MOVPRFX.
 700
 701 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 702
 703         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 704         sve_size_13 icode to account for variant behaviour of
 705         pmull{t,b}.
 706         * aarch64-dis-2.c: Regenerate.
 707         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 708         sve_size_13 icode to account for variant behaviour of
 709         pmull{t,b}.
 710         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 711         (OP_SVE_VVV_Q_D): Add new qualifier.
 712         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 713         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 714         AES and those not.
 715
 716 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 717
 718         * opcodes/i386-gen.c (operand_type_init): Remove
 719         OPERAND_TYPE_VEC_IMM4 entry.
 720         (operand_types): Remove Vec_Imm4.
 721         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 722         (union i386_operand_type): Remove vec_imm4.
 723         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 724         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 725
 726 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 727
 728         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 729         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 730         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 731         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 732         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 733         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 734         * i386-tbl.h: Re-generate.
 735
 736 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 737
 738         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 739         register operands.
 740         * i386-tbl.h: Re-generate.
 741
 742 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 743
 744         * i386-opc.tbl (C): New.
 745         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 746         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 747         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 748         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 749         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 750         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 751         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 752         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 753         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 754         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 755         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 756         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 757         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 758         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 759         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 760         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 761         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 762         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 763         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 764         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 765         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 766         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 767         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 768         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 769         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 770         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 771         flavors.
 772         * i386-tbl.h: Re-generate.
 773
 774 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 775
 776         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 777         register operands.
 778         * i386-tbl.h: Re-generate.
 779
 780 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 781
 782         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 783         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 784         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 785         * i386-tbl.h: Re-generate.
 786
 787 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 788
 789         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 790         Disp8MemShift from register only templates.
 791         * i386-tbl.h: Re-generate.
 792
 793 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 794
 795         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 796         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 797         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 798         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 799         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 800         EVEX_W_0F11_P_3_M_1): Delete.
 801         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 802         EVEX_W_0F11_P_3): New.
 803         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 804         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 805         MOD_EVEX_0F11_PREFIX_3 table entries.
 806         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 807         PREFIX_EVEX_0F11 table entries.
 808         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 809         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 810         EVEX_W_0F11_P_3_M_{0,1} table entries.
 811
 812 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 813
 814         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 815         Delete.
 816
 817 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 818
 819         PR binutils/24719
 820         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 821         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 822         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 823         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 824         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 825         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 826         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 827         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 828         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 829         PREFIX_EVEX_0F38C6_REG_6 entries.
 830         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 831         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 832         EVEX_W_0F38C7_R_6_P_2 entries.
 833         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 834         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 835         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 836         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 837         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 838         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 839         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 840
 841 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 842
 843         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 844         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 845         VEX_LEN_0F2D_P_3): Delete.
 846         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 847         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 848         (prefix_table): ... here.
 849
 850 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 851
 852         * i386-dis.c (Iq): Delete.
 853         (Id): New.
 854         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 855         TBM insns.
 856         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 857         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 858         (OP_E_memory): Also honor needindex when deciding whether an
 859         address size prefix needs printing.
 860         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 861
 862 2019-06-26  Jim Wilson  <jimw@sifive.com>
 863
 864         PR binutils/24739
 865         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 866         Set info->display_endian to info->endian_code.
 867
 868 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 869
 870         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 871         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 872         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 873         OPERAND_TYPE_ACC64 entries.
 874         * i386-init.h: Re-generate.
 875
 876 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 877
 878         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 879         Delete.
 880         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 881         of dqa_mode.
 882         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 883         entries here.
 884         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 885         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 886
 887 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 888
 889         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 890         variables.
 891
 892 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 893
 894         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 895         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 896         movnti.
 897         * i386-opc.tbl (movnti): Add IgnoreSize.
 898         * i386-tbl.h: Re-generate.
 899
 900 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 901
 902         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 903         * i386-tbl.h: Re-generate.
 904
 905 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 906
 907         * i386-dis-evex.h: Break into ...
 908         * i386-dis-evex-len.h: New file.
 909         * i386-dis-evex-mod.h: Likewise.
 910         * i386-dis-evex-prefix.h: Likewise.
 911         * i386-dis-evex-reg.h: Likewise.
 912         * i386-dis-evex-w.h: Likewise.
 913         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 914         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 915         i386-dis-evex-mod.h.
 916
 917 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 918
 919         PR binutils/24700
 920         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 921         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 922         EVEX_W_0F385B_P_2.
 923         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 924         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 925         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 926         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 927         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 928         EVEX_LEN_0F385B_P_2_W_1.
 929         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 930         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 931         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 932         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 933         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 934         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 935         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 936         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 937         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 938         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 939
 940 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 941
 942         PR binutils/24691
 943         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 944         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 945         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 946         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 947         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 948         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 949         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 950         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 951         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 952         EVEX_LEN_0F3A43_P_2_W_1.
 953         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 954         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 955         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 956         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 957         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 958         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 959         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 960         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 961         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 962         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 963         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 964         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 965
 966 2019-06-14  Nick Clifton  <nickc@redhat.com>
 967
 968         * po/fr.po; Updated French translation.
 969
 970 2019-06-13  Stafford Horne  <shorne@gmail.com>
 971
 972         * or1k-asm.c: Regenerated.
 973         * or1k-desc.c: Regenerated.
 974         * or1k-desc.h: Regenerated.
 975         * or1k-dis.c: Regenerated.
 976         * or1k-ibld.c: Regenerated.
 977         * or1k-opc.c: Regenerated.
 978         * or1k-opc.h: Regenerated.
 979         * or1k-opinst.c: Regenerated.
 980
 981 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 982
 983         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 984
 985 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 986
 987         PR binutils/24633
 988         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 989         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 990         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 991         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 992         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 993         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 994         EVEX_LEN_0F3A1B_P_2_W_1.
 995         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 996         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 997         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 998         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 999         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1000         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1001         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1002         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1003
1004 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1005
1006         PR binutils/24626
1007         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1008         EVEX.vvvv when disassembling VEX and EVEX instructions.
1009         (OP_VEX): Set vex.register_specifier to 0 after readding
1010         vex.register_specifier.
1011         (OP_Vex_2src_1): Likewise.
1012         (OP_Vex_2src_2): Likewise.
1013         (OP_LWP_E): Likewise.
1014         (OP_EX_Vex): Don't check vex.register_specifier.
1015         (OP_XMM_Vex): Likewise.
1016
1017 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1018             Lili Cui  <lili.cui@intel.com>
1019
1020         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1021         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1022         instructions.
1023         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1024         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1025         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1026         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1027         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1028         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1029         * i386-init.h: Regenerated.
1030         * i386-tbl.h: Likewise.
1031
1032 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1033             Lili Cui  <lili.cui@intel.com>
1034
1035         * doc/c-i386.texi: Document enqcmd.
1036         * testsuite/gas/i386/enqcmd-intel.d: New file.
1037         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1038         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1039         * testsuite/gas/i386/enqcmd.d: Likewise.
1040         * testsuite/gas/i386/enqcmd.s: Likewise.
1041         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1042         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1043         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1044         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1045         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1046         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1047         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1048         and x86-64-enqcmd.
1049
1050 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1051
1052         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1053
1054 2019-06-03  Alan Modra  <amodra@gmail.com>
1055
1056         * ppc-dis.c (prefix_opcd_indices): Correct size.
1057
1058 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1059
1060         PR gas/24625
1061         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1062         Disp8ShiftVL.
1063         * i386-tbl.h: Regenerated.
1064
1065 2019-05-24  Alan Modra  <amodra@gmail.com>
1066
1067         * po/POTFILES.in: Regenerate.
1068
1069 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1070             Alan Modra  <amodra@gmail.com>
1071
1072         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1073         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1074         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1075         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1076         XTOP>): Define and add entries.
1077         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1078         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1079         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1080         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1081
1082 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1083             Alan Modra  <amodra@gmail.com>
1084
1085         * ppc-dis.c (ppc_opts): Add "future" entry.
1086         (PREFIX_OPCD_SEGS): Define.
1087         (prefix_opcd_indices): New array.
1088         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1089         (lookup_prefix): New function.
1090         (print_insn_powerpc): Handle 64-bit prefix instructions.
1091         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1092         (PMRR, POWERXX): Define.
1093         (prefix_opcodes): New instruction table.
1094         (prefix_num_opcodes): New constant.
1095
1096 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1097
1098         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1099         * configure: Regenerated.
1100         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1101         and cpu/bpf.opc.
1102         (HFILES): Add bpf-desc.h and bpf-opc.h.
1103         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1104         bpf-ibld.c and bpf-opc.c.
1105         (BPF_DEPS): Define.
1106         * Makefile.in: Regenerated.
1107         * disassemble.c (ARCH_bpf): Define.
1108         (disassembler): Add case for bfd_arch_bpf.
1109         (disassemble_init_for_target): Likewise.
1110         (enum epbf_isa_attr): Define.
1111         * disassemble.h: extern print_insn_bpf.
1112         * bpf-asm.c: Generated.
1113         * bpf-opc.h: Likewise.
1114         * bpf-opc.c: Likewise.
1115         * bpf-ibld.c: Likewise.
1116         * bpf-dis.c: Likewise.
1117         * bpf-desc.h: Likewise.
1118         * bpf-desc.c: Likewise.
1119
1120 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1121
1122         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1123         and VMSR with the new operands.
1124
1125 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1126
1127         * arm-dis.c (enum mve_instructions): New enum
1128         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1129         and cneg.
1130         (mve_opcodes): New instructions as above.
1131         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1132         csneg and csel.
1133         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1134
1135 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1136
1137         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1138         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1139         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1140         uqshl, urshrl and urshr.
1141         (is_mve_okay_in_it): Add new instructions to TRUE list.
1142         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1143         (print_insn_mve): Updated to accept new %j,
1144         %<bitfield>m and %<bitfield>n patterns.
1145
1146 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1147
1148         * mips-opc.c (mips_builtin_opcodes): Change source register
1149         constraint for DAUI.
1150
1151 2019-05-20  Nick Clifton  <nickc@redhat.com>
1152
1153         * po/fr.po: Updated French translation.
1154
1155 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1156             Michael Collison <michael.collison@arm.com>
1157
1158         * arm-dis.c (thumb32_opcodes): Add new instructions.
1159         (enum mve_instructions): Likewise.
1160         (enum mve_undefined): Add new reasons.
1161         (is_mve_encoding_conflict): Handle new instructions.
1162         (is_mve_undefined): Likewise.
1163         (is_mve_unpredictable): Likewise.
1164         (print_mve_undefined): Likewise.
1165         (print_mve_size): Likewise.
1166
1167 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1168             Michael Collison <michael.collison@arm.com>
1169
1170         * arm-dis.c (thumb32_opcodes): Add new instructions.
1171         (enum mve_instructions): Likewise.
1172         (is_mve_encoding_conflict): Handle new instructions.
1173         (is_mve_undefined): Likewise.
1174         (is_mve_unpredictable): Likewise.
1175         (print_mve_size): Likewise.
1176
1177 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1178             Michael Collison <michael.collison@arm.com>
1179
1180         * arm-dis.c (thumb32_opcodes): Add new instructions.
1181         (enum mve_instructions): Likewise.
1182         (is_mve_encoding_conflict): Likewise.
1183         (is_mve_unpredictable): Likewise.
1184         (print_mve_size): Likewise.
1185
1186 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1187             Michael Collison <michael.collison@arm.com>
1188
1189         * arm-dis.c (thumb32_opcodes): Add new instructions.
1190         (enum mve_instructions): Likewise.
1191         (is_mve_encoding_conflict): Handle new instructions.
1192         (is_mve_undefined): Likewise.
1193         (is_mve_unpredictable): Likewise.
1194         (print_mve_size): Likewise.
1195
1196 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1197             Michael Collison <michael.collison@arm.com>
1198
1199         * arm-dis.c (thumb32_opcodes): Add new instructions.
1200         (enum mve_instructions): Likewise.
1201         (is_mve_encoding_conflict): Handle new instructions.
1202         (is_mve_undefined): Likewise.
1203         (is_mve_unpredictable): Likewise.
1204         (print_mve_size): Likewise.
1205         (print_insn_mve): Likewise.
1206
1207 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1208             Michael Collison <michael.collison@arm.com>
1209
1210         * arm-dis.c (thumb32_opcodes): Add new instructions.
1211         (print_insn_thumb32): Handle new instructions.
1212
1213 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1214             Michael Collison <michael.collison@arm.com>
1215
1216         * arm-dis.c (enum mve_instructions): Add new instructions.
1217         (enum mve_undefined): Add new reasons.
1218         (is_mve_encoding_conflict): Handle new instructions.
1219         (is_mve_undefined): Likewise.
1220         (is_mve_unpredictable): Likewise.
1221         (print_mve_undefined): Likewise.
1222         (print_mve_size): Likewise.
1223         (print_mve_shift_n): Likewise.
1224         (print_insn_mve): Likewise.
1225
1226 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1227             Michael Collison <michael.collison@arm.com>
1228
1229         * arm-dis.c (enum mve_instructions): Add new instructions.
1230         (is_mve_encoding_conflict): Handle new instructions.
1231         (is_mve_unpredictable): Likewise.
1232         (print_mve_rotate): Likewise.
1233         (print_mve_size): Likewise.
1234         (print_insn_mve): Likewise.
1235
1236 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1237             Michael Collison <michael.collison@arm.com>
1238
1239         * arm-dis.c (enum mve_instructions): Add new instructions.
1240         (is_mve_encoding_conflict): Handle new instructions.
1241         (is_mve_unpredictable): Likewise.
1242         (print_mve_size): Likewise.
1243         (print_insn_mve): Likewise.
1244
1245 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1246             Michael Collison <michael.collison@arm.com>
1247
1248         * arm-dis.c (enum mve_instructions): Add new instructions.
1249         (enum mve_undefined): Add new reasons.
1250         (is_mve_encoding_conflict): Handle new instructions.
1251         (is_mve_undefined): Likewise.
1252         (is_mve_unpredictable): Likewise.
1253         (print_mve_undefined): Likewise.
1254         (print_mve_size): Likewise.
1255         (print_insn_mve): Likewise.
1256
1257 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1258             Michael Collison <michael.collison@arm.com>
1259
1260         * arm-dis.c (enum mve_instructions): Add new instructions.
1261         (is_mve_encoding_conflict): Handle new instructions.
1262         (is_mve_undefined): Likewise.
1263         (is_mve_unpredictable): Likewise.
1264         (print_mve_size): Likewise.
1265         (print_insn_mve): Likewise.
1266
1267 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1268             Michael Collison <michael.collison@arm.com>
1269
1270         * arm-dis.c (enum mve_instructions): Add new instructions.
1271         (enum mve_unpredictable): Add new reasons.
1272         (enum mve_undefined): Likewise.
1273         (is_mve_okay_in_it): Handle new isntructions.
1274         (is_mve_encoding_conflict): Likewise.
1275         (is_mve_undefined): Likewise.
1276         (is_mve_unpredictable): Likewise.
1277         (print_mve_vmov_index): Likewise.
1278         (print_simd_imm8): Likewise.
1279         (print_mve_undefined): Likewise.
1280         (print_mve_unpredictable): Likewise.
1281         (print_mve_size): Likewise.
1282         (print_insn_mve): Likewise.
1283
1284 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1285             Michael Collison <michael.collison@arm.com>
1286
1287         * arm-dis.c (enum mve_instructions): Add new instructions.
1288         (enum mve_unpredictable): Add new reasons.
1289         (enum mve_undefined): Likewise.
1290         (is_mve_encoding_conflict): Handle new instructions.
1291         (is_mve_undefined): Likewise.
1292         (is_mve_unpredictable): Likewise.
1293         (print_mve_undefined): Likewise.
1294         (print_mve_unpredictable): Likewise.
1295         (print_mve_rounding_mode): Likewise.
1296         (print_mve_vcvt_size): Likewise.
1297         (print_mve_size): Likewise.
1298         (print_insn_mve): Likewise.
1299
1300 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1301             Michael Collison <michael.collison@arm.com>
1302
1303         * arm-dis.c (enum mve_instructions): Add new instructions.
1304         (enum mve_unpredictable): Add new reasons.
1305         (enum mve_undefined): Likewise.
1306         (is_mve_undefined): Handle new instructions.
1307         (is_mve_unpredictable): Likewise.
1308         (print_mve_undefined): Likewise.
1309         (print_mve_unpredictable): Likewise.
1310         (print_mve_size): Likewise.
1311         (print_insn_mve): Likewise.
1312
1313 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1314             Michael Collison <michael.collison@arm.com>
1315
1316         * arm-dis.c (enum mve_instructions): Add new instructions.
1317         (enum mve_undefined): Add new reasons.
1318         (insns): Add new instructions.
1319         (is_mve_encoding_conflict):
1320         (print_mve_vld_str_addr): New print function.
1321         (is_mve_undefined): Handle new instructions.
1322         (is_mve_unpredictable): Likewise.
1323         (print_mve_undefined): Likewise.
1324         (print_mve_size): Likewise.
1325         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1326         (print_insn_mve):  Handle new operands.
1327
1328 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1329             Michael Collison <michael.collison@arm.com>
1330
1331         * arm-dis.c (enum mve_instructions): Add new instructions.
1332         (enum mve_unpredictable): Add new reasons.
1333         (is_mve_encoding_conflict): Handle new instructions.
1334         (is_mve_unpredictable): Likewise.
1335         (mve_opcodes): Add new instructions.
1336         (print_mve_unpredictable): Handle new reasons.
1337         (print_mve_register_blocks): New print function.
1338         (print_mve_size): Handle new instructions.
1339         (print_insn_mve): Likewise.
1340
1341 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1342             Michael Collison <michael.collison@arm.com>
1343
1344         * arm-dis.c (enum mve_instructions): Add new instructions.
1345         (enum mve_unpredictable): Add new reasons.
1346         (enum mve_undefined): Likewise.
1347         (is_mve_encoding_conflict): Handle new instructions.
1348         (is_mve_undefined): Likewise.
1349         (is_mve_unpredictable): Likewise.
1350         (coprocessor_opcodes): Move NEON VDUP from here...
1351         (neon_opcodes): ... to here.
1352         (mve_opcodes): Add new instructions.
1353         (print_mve_undefined):  Handle new reasons.
1354         (print_mve_unpredictable): Likewise.
1355         (print_mve_size): Handle new instructions.
1356         (print_insn_neon): Handle vdup.
1357         (print_insn_mve): Handle new operands.
1358
1359 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1360             Michael Collison <michael.collison@arm.com>
1361
1362         * arm-dis.c (enum mve_instructions): Add new instructions.
1363         (enum mve_unpredictable): Add new values.
1364         (mve_opcodes): Add new instructions.
1365         (vec_condnames): New array with vector conditions.
1366         (mve_predicatenames): New array with predicate suffixes.
1367         (mve_vec_sizename): New array with vector sizes.
1368         (enum vpt_pred_state): New enum with vector predication states.
1369         (struct vpt_block): New struct type for vpt blocks.
1370         (vpt_block_state): Global struct to keep track of state.
1371         (mve_extract_pred_mask): New helper function.
1372         (num_instructions_vpt_block): Likewise.
1373         (mark_outside_vpt_block): Likewise.
1374         (mark_inside_vpt_block): Likewise.
1375         (invert_next_predicate_state): Likewise.
1376         (update_next_predicate_state): Likewise.
1377         (update_vpt_block_state): Likewise.
1378         (is_vpt_instruction): Likewise.
1379         (is_mve_encoding_conflict): Add entries for new instructions.
1380         (is_mve_unpredictable): Likewise.
1381         (print_mve_unpredictable): Handle new cases.
1382         (print_instruction_predicate): Likewise.
1383         (print_mve_size): New function.
1384         (print_vec_condition): New function.
1385         (print_insn_mve): Handle vpt blocks and new print operands.
1386
1387 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1388
1389         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1390         8, 14 and 15 for Armv8.1-M Mainline.
1391
1392 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1393             Michael Collison <michael.collison@arm.com>
1394
1395         * arm-dis.c (enum mve_instructions): New enum.
1396         (enum mve_unpredictable): Likewise.
1397         (enum mve_undefined): Likewise.
1398         (struct mopcode32): New struct.
1399         (is_mve_okay_in_it): New function.
1400         (is_mve_architecture): Likewise.
1401         (arm_decode_field): Likewise.
1402         (arm_decode_field_multiple): Likewise.
1403         (is_mve_encoding_conflict): Likewise.
1404         (is_mve_undefined): Likewise.
1405         (is_mve_unpredictable): Likewise.
1406         (print_mve_undefined): Likewise.
1407         (print_mve_unpredictable): Likewise.
1408         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1409         (print_insn_mve): New function.
1410         (print_insn_thumb32): Handle MVE architecture.
1411         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1412
1413 2019-05-10  Nick Clifton  <nickc@redhat.com>
1414
1415         PR 24538
1416         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1417         end of the table prematurely.
1418
1419 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1420
1421         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1422         macros for R6.
1423
1424 2019-05-11  Alan Modra  <amodra@gmail.com>
1425
1426         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1427         when -Mraw is in effect.
1428
1429 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1430
1431         * aarch64-dis-2.c: Regenerate.
1432         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1433         (OP_SVE_BBB): New variant set.
1434         (OP_SVE_DDDD): New variant set.
1435         (OP_SVE_HHH): New variant set.
1436         (OP_SVE_HHHU): New variant set.
1437         (OP_SVE_SSS): New variant set.
1438         (OP_SVE_SSSU): New variant set.
1439         (OP_SVE_SHH): New variant set.
1440         (OP_SVE_SBBU): New variant set.
1441         (OP_SVE_DSS): New variant set.
1442         (OP_SVE_DHHU): New variant set.
1443         (OP_SVE_VMV_HSD_BHS): New variant set.
1444         (OP_SVE_VVU_HSD_BHS): New variant set.
1445         (OP_SVE_VVVU_SD_BH): New variant set.
1446         (OP_SVE_VVVU_BHSD): New variant set.
1447         (OP_SVE_VVV_QHD_DBS): New variant set.
1448         (OP_SVE_VVV_HSD_BHS): New variant set.
1449         (OP_SVE_VVV_HSD_BHS2): New variant set.
1450         (OP_SVE_VVV_BHS_HSD): New variant set.
1451         (OP_SVE_VV_BHS_HSD): New variant set.
1452         (OP_SVE_VVV_SD): New variant set.
1453         (OP_SVE_VVU_BHS_HSD): New variant set.
1454         (OP_SVE_VZVV_SD): New variant set.
1455         (OP_SVE_VZVV_BH): New variant set.
1456         (OP_SVE_VZV_SD): New variant set.
1457         (aarch64_opcode_table): Add sve2 instructions.
1458
1459 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1460
1461         * aarch64-asm-2.c: Regenerated.
1462         * aarch64-dis-2.c: Regenerated.
1463         * aarch64-opc-2.c: Regenerated.
1464         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1465         for SVE_SHLIMM_UNPRED_22.
1466         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1467         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1468         operand.
1469
1470 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1471
1472         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1473         sve_size_tsz_bhs iclass encode.
1474         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1475         sve_size_tsz_bhs iclass decode.
1476
1477 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1478
1479         * aarch64-asm-2.c: Regenerated.
1480         * aarch64-dis-2.c: Regenerated.
1481         * aarch64-opc-2.c: Regenerated.
1482         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1483         for SVE_Zm4_11_INDEX.
1484         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1485         (fields): Handle SVE_i2h field.
1486         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1487         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1488
1489 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1490
1491         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1492         sve_shift_tsz_bhsd iclass encode.
1493         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1494         sve_shift_tsz_bhsd iclass decode.
1495
1496 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1497
1498         * aarch64-asm-2.c: Regenerated.
1499         * aarch64-dis-2.c: Regenerated.
1500         * aarch64-opc-2.c: Regenerated.
1501         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1502         (aarch64_encode_variant_using_iclass): Handle
1503         sve_shift_tsz_hsd iclass encode.
1504         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1505         sve_shift_tsz_hsd iclass decode.
1506         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1507         for SVE_SHRIMM_UNPRED_22.
1508         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1509         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1510         operand.
1511
1512 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1513
1514         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1515         sve_size_013 iclass encode.
1516         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1517         sve_size_013 iclass decode.
1518
1519 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1520
1521         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1522         sve_size_bh iclass encode.
1523         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1524         sve_size_bh iclass decode.
1525
1526 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1527
1528         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1529         sve_size_sd2 iclass encode.
1530         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1531         sve_size_sd2 iclass decode.
1532         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1533         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1534
1535 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1536
1537         * aarch64-asm-2.c: Regenerated.
1538         * aarch64-dis-2.c: Regenerated.
1539         * aarch64-opc-2.c: Regenerated.
1540         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1541         for SVE_ADDR_ZX.
1542         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1543         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1544
1545 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1546
1547         * aarch64-asm-2.c: Regenerated.
1548         * aarch64-dis-2.c: Regenerated.
1549         * aarch64-opc-2.c: Regenerated.
1550         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1551         for SVE_Zm3_11_INDEX.
1552         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1553         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1554         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1555         fields.
1556         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1557
1558 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1559
1560         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1561         sve_size_hsd2 iclass encode.
1562         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1563         sve_size_hsd2 iclass decode.
1564         * aarch64-opc.c (fields): Handle SVE_size field.
1565         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1566
1567 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1568
1569         * aarch64-asm-2.c: Regenerated.
1570         * aarch64-dis-2.c: Regenerated.
1571         * aarch64-opc-2.c: Regenerated.
1572         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1573         for SVE_IMM_ROT3.
1574         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1575         (fields): Handle SVE_rot3 field.
1576         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1577         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1578
1579 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1580
1581         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1582         instructions.
1583
1584 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1585
1586         * aarch64-tbl.h
1587         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1588         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1589         aarch64_feature_sve2bitperm): New feature sets.
1590         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1591         for feature set addresses.
1592         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1593         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1594
1595 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1596             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1597
1598         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1599         argument and set ASE_EVA_R6 appropriately.
1600         (set_default_mips_dis_options): Pass ISA to above.
1601         (parse_mips_dis_option): Likewise.
1602         * mips-opc.c (EVAR6): New macro.
1603         (mips_builtin_opcodes): Add llwpe, scwpe.
1604
1605 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1606
1607         * aarch64-asm-2.c: Regenerated.
1608         * aarch64-dis-2.c: Regenerated.
1609         * aarch64-opc-2.c: Regenerated.
1610         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1611         AARCH64_OPND_TME_UIMM16.
1612         (aarch64_print_operand): Likewise.
1613         * aarch64-tbl.h (QL_IMM_NIL): New.
1614         (TME): New.
1615         (_TME_INSN): New.
1616         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1617
1618 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1619
1620         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1621
1622 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1623             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1624
1625         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1626
1627 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1628
1629         * s12z-opc.h: Add extern "C" bracketing to help
1630         users who wish to use this interface in c++ code.
1631
1632 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1633
1634         * s12z-opc.c (bm_decode): Handle bit map operations with the
1635         "reserved0" mode.
1636
1637 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1638
1639         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1640         specifier.  Add entries for VLDR and VSTR of system registers.
1641         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1642         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1643         of %J and %K format specifier.
1644
1645 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1646
1647         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1648         Add new entries for VSCCLRM instruction.
1649         (print_insn_coprocessor): Handle new %C format control code.
1650
1651 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1652
1653         * arm-dis.c (enum isa): New enum.
1654         (struct sopcode32): New structure.
1655         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1656         set isa field of all current entries to ANY.
1657         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1658         Only match an entry if its isa field allows the current mode.
1659
1660 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1661
1662         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1663         CLRM.
1664         (print_insn_thumb32): Add logic to print %n CLRM register list.
1665
1666 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1667
1668         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1669         and %Q patterns.
1670
1671 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1672
1673         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1674         (print_insn_thumb32): Edit the switch case for %Z.
1675
1676 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1677
1678         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1679
1680 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1681
1682         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1683
1684 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1685
1686         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1687
1688 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1689
1690         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1691         Arm register with r13 and r15 unpredictable.
1692         (thumb32_opcodes): New instructions for bfx and bflx.
1693
1694 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1695
1696         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1697
1698 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1699
1700         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1701
1702 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1703
1704         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1705
1706 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1707
1708         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1709
1710 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1711
1712         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1713         "optr". ("operator" is a reserved word in c++).
1714
1715 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1716
1717         * aarch64-opc.c (aarch64_print_operand): Add case for
1718         AARCH64_OPND_Rt_SP.
1719         (verify_constraints): Likewise.
1720         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1721         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1722         to accept Rt|SP as first operand.
1723         (AARCH64_OPERANDS): Add new Rt_SP.
1724         * aarch64-asm-2.c: Regenerated.
1725         * aarch64-dis-2.c: Regenerated.
1726         * aarch64-opc-2.c: Regenerated.
1727
1728 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1729
1730         * aarch64-asm-2.c: Regenerated.
1731         * aarch64-dis-2.c: Likewise.
1732         * aarch64-opc-2.c: Likewise.
1733         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1734
1735 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1736
1737         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1738
1739 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1740
1741         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1742         * i386-init.h: Regenerated.
1743
1744 2019-04-07  Alan Modra  <amodra@gmail.com>
1745
1746         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1747         op_separator to control printing of spaces, comma and parens
1748         rather than need_comma, need_paren and spaces vars.
1749
1750 2019-04-07  Alan Modra  <amodra@gmail.com>
1751
1752         PR 24421
1753         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1754         (print_insn_neon, print_insn_arm): Likewise.
1755
1756 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1757
1758         * i386-dis-evex.h (evex_table): Updated to support BF16
1759         instructions.
1760         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1761         and EVEX_W_0F3872_P_3.
1762         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1763         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1764         * i386-opc.h (enum): Add CpuAVX512_BF16.
1765         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1766         * i386-opc.tbl: Add AVX512 BF16 instructions.
1767         * i386-init.h: Regenerated.
1768         * i386-tbl.h: Likewise.
1769
1770 2019-04-05  Alan Modra  <amodra@gmail.com>
1771
1772         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1773         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1774         to favour printing of "-" branch hint when using the "y" bit.
1775         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1776
1777 2019-04-05  Alan Modra  <amodra@gmail.com>
1778
1779         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1780         opcode until first operand is output.
1781
1782 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1783
1784         PR gas/24349
1785         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1786         (valid_bo_post_v2): Add support for 'at' branch hints.
1787         (insert_bo): Only error on branch on ctr.
1788         (get_bo_hint_mask): New function.
1789         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1790         for inserting 'at' branch hints.
1791         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1792         for extracting 'at' branch hints.
1793         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1794         (BOE): Delete operand.
1795         (BOM, BOP): New operands.
1796         (RM): Update value.
1797         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1798         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1799         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1800         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1801         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1802         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1803         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1804         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1805         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1806         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1807         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1808         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1809         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1810         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1811         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1812         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1813         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1814         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1815         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1816         bttarl+>: New extended mnemonics.
1817
1818 2019-03-28  Alan Modra  <amodra@gmail.com>
1819
1820         PR 24390
1821         * ppc-opc.c (BTF): Define.
1822         (powerpc_opcodes): Use for mtfsb*.
1823         * ppc-dis.c (print_insn_powerpc): Print fields with both
1824         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1825
1826 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1827
1828         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1829         (mapping_symbol_for_insn): Implement new algorithm.
1830         (print_insn): Remove duplicate code.
1831
1832 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1833
1834         * aarch64-dis.c (print_insn_aarch64):
1835         Implement override.
1836
1837 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1838
1839         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1840         order.
1841
1842 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1843
1844         * aarch64-dis.c (last_stop_offset): New.
1845         (print_insn_aarch64): Use stop_offset.
1846
1847 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1848
1849         PR gas/24359
1850         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1851         CPU_ANY_AVX2_FLAGS.
1852         * i386-init.h: Regenerated.
1853
1854 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1855
1856         PR gas/24348
1857         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1858         vmovdqu16, vmovdqu32 and vmovdqu64.
1859         * i386-tbl.h: Regenerated.
1860
1861 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1862
1863         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1864         from vstrszb, vstrszh, and vstrszf.
1865
1866 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1867
1868         * s390-opc.txt: Add instruction descriptions.
1869
1870 2019-02-08  Jim Wilson  <jimw@sifive.com>
1871
1872         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1873         <bne>: Likewise.
1874
1875 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1876
1877         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1878
1879 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1880
1881         PR binutils/23212
1882         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1883         * aarch64-opc.c (verify_elem_sd): New.
1884         (fields): Add FLD_sz entr.
1885         * aarch64-tbl.h (_SIMD_INSN): New.
1886         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1887         fmulx scalar and vector by element isns.
1888
1889 2019-02-07  Nick Clifton  <nickc@redhat.com>
1890
1891         * po/sv.po: Updated Swedish translation.
1892
1893 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1894
1895         * s390-mkopc.c (main): Accept arch13 as cpu string.
1896         * s390-opc.c: Add new instruction formats and instruction opcode
1897         masks.
1898         * s390-opc.txt: Add new arch13 instructions.
1899
1900 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1901
1902         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1903         (aarch64_opcode): Change encoding for stg, stzg
1904         st2g and st2zg.
1905         * aarch64-asm-2.c: Regenerated.
1906         * aarch64-dis-2.c: Regenerated.
1907         * aarch64-opc-2.c: Regenerated.
1908
1909 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1910
1911         * aarch64-asm-2.c: Regenerated.
1912         * aarch64-dis-2.c: Likewise.
1913         * aarch64-opc-2.c: Likewise.
1914         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1915
1916 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1917             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1918
1919         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1920         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1921         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1922         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1923         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1924         case for ldstgv_indexed.
1925         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1926         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1927         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1928         * aarch64-asm-2.c: Regenerated.
1929         * aarch64-dis-2.c: Regenerated.
1930         * aarch64-opc-2.c: Regenerated.
1931
1932 2019-01-23  Nick Clifton  <nickc@redhat.com>
1933
1934         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1935
1936 2019-01-21  Nick Clifton  <nickc@redhat.com>
1937
1938         * po/de.po: Updated German translation.
1939         * po/uk.po: Updated Ukranian translation.
1940
1941 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1942         * mips-dis.c (mips_arch_choices): Fix typo in
1943         gs464, gs464e and gs264e descriptors.
1944
1945 2019-01-19  Nick Clifton  <nickc@redhat.com>
1946
1947         * configure: Regenerate.
1948         * po/opcodes.pot: Regenerate.
1949
1950 2018-06-24  Nick Clifton  <nickc@redhat.com>
1951
1952         2.32 branch created.
1953
1954 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1955
1956         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1957         if it is null.
1958         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1959         zero.
1960
1961 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1962
1963         * configure: Regenerate.
1964
1965 2019-01-07  Alan Modra  <amodra@gmail.com>
1966
1967         * configure: Regenerate.
1968         * po/POTFILES.in: Regenerate.
1969
1970 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1971
1972         * s12z-opc.c: New file.
1973         * s12z-opc.h: New file.
1974         * s12z-dis.c: Removed all code not directly related to display
1975         of instructions.  Used the interface provided by the new files
1976         instead.
1977         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1978         * Makefile.in: Regenerate.
1979         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1980         * configure: Regenerate.
1981
1982 2019-01-01  Alan Modra  <amodra@gmail.com>
1983
1984         Update year range in copyright notice of all files.
1985
1986 For older changes see ChangeLog-2018
1987 \f
1988 Copyright (C) 2019 Free Software Foundation, Inc.
1989
1990 Copying and distribution of this file, with or without modification,
1991 are permitted in any medium without royalty provided the copyright
1992 notice and this notice are preserved.
1993
1994 Local Variables:
1995 mode: change-log
1996 left-margin: 8
1997 fill-column: 74
1998 version-control: never
1999 End: