opcodes/ChangeLog

   1 2006-10-26  Ben Elliston  <bje@au.ibm.com>
   2             Anton Blanchard  <anton@samba.org>
   3             Peter Bergner  <bergner@vnet.ibm.com>
   4
   5         * ppc-opc.c (A_L, DCM, DGM, TE, RMC, R, SP, S, SH16, XRT_L, EH,
   6         AFRALFRC_MASK, Z, ZRC, Z_MASK, XLRT_MASK, XEH_MASK): Define.
   7         (POWER6): Define.
   8         (powerpc_opcodes): Extend "lwarx", "ldarx", "dcbf", "fres", "fres.",
   9         "frsqrtes", "frsqrtes." "fre", "fre.", "frsqrte" and "frsqrte.".
  10         Add "doze", "nap", "sleep", "rvwinkle", "dcbfl", "prtyw", "prtyd",
  11         "mfcfar", "cmpb", "lfdpx", "stfdpx", "mtcfar", "mffgpr", "mftgpr",
  12         "lwzcix", "lhzcix", "lbzcix", "ldcix", "lfiwax", "stwcix", "sthcix",
  13         "stbcix", "stdcix", "lfdp", "dadd", "dadd.", "dqua", "dqua.", "dmul",
  14         "dmul.", "drrnd", "drrnd.", "dscli", "dscli.", "dquai", "dquai.",
  15         "dscri", "dscri.", "drintx", "drintx.", "dcmpo", "dtstex", "dtstdc",
  16         "dtstdg", "dtstsf", "drintn", "drintn.", "dctdp", "dctdp.", "dctfix",
  17         "dctfix.", "ddedpd", "ddedpd.", "dxex", "dxex.", "dsub", "dsub.",
  18         "ddiv", "ddiv.", "dcmpu", "drsp", "drsp.", "dcffix", "dcffix.",
  19         "denbcd", "denbcd.", "diex", "diex.", "stfdp", "daddq", "daddq.",
  20         "dquaq", "dquaq.", "fcpsgn", "fcpsgn.", "dmulq", "dmulq.",
  21         "drrndq", "drrndq.", "dscliq", "dscliq.", "dquaiq", "dquaiq.",
  22         "dscriq", "dscriq.", "drintxq", "drintxq.", "dcmpoq", "dtstexq",
  23         "dtstdcq", "dtstdgq", "dtstsfq", "drintnq", "drintnq.",
  24         "dctqpq", "dctqpq.", "dctfixq", "dctfixq.", "ddedpdq", "ddedpdq.",
  25         "dxexq", "dxexq.", "dsubq", "dsubq.", "ddivq", "ddivq.", "dcmpuq",
  26         "drdpq", "drdpq.", "dcffixq", "dcffixq.", "denbcdq", "denbcdq.",
  27         "diexq" and "diexq." opcodes.
  28
  29 2006-10-26  Daniel Jacobowitz  <dan@codesourcery.com>
  30
  31         * h8300-dis.c (bfd_h8_disassemble): Add missing consts.
  32
  33 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
  34             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
  35             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
  36             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
  37             Alan Modra  <amodra@bigpond.net.au>
  38
  39         * spu-dis.c: New file.
  40         * spu-opc.c: New file.
  41         * configure.in: Add SPU support.
  42         * disassemble.c: Likewise.
  43         * Makefile.am: Likewise.  Run "make dep-am".
  44         * Makefile.in: Regenerate.
  45         * configure: Regenerate.
  46         * po/POTFILES.in: Regenerate.
  47
  48 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
  49
  50         * ppc-opc.c (CELL): New define.
  51         (powerpc_opcodes): Enable hrfid for Cell.  Add ldbrx and stdbrx,
  52         cell specific instructions.  Add {st,l}x{r,l}{,l} cell specific
  53         VMX instructions.
  54         * ppc-dis.c (powerpc_dialect): Handle cell.
  55
  56 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
  57
  58         * i386-dis.c (dis386): Add support for the change in POPCNT opcode in
  59         amdfam10 architecture.
  60         (PREGRP37): NEW.
  61         (print_insn): Disallow REP prefix for POPCNT.
  62
  63 2006-10-20  Andrew Stubbs  <andrew.stubbs@st.com>
  64
  65         * sh-dis.c (print_insn_sh): Remove 0x from output to prevent GDB
  66         duplicating it.
  67
  68 2006-10-18  Dave Brolley  <brolley@redhat.com>
  69
  70         * configure.in (BFD_MACHINES): Add cgen-bitset.lo for bfd_sh_arch.
  71         * configure: Regenerated.
  72
  73 2006-09-29  Alan Modra  <amodra@bigpond.net.au>
  74
  75         * po/POTFILES.in: Regenerate.
  76
  77 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
  78             Joseph Myers  <joseph@codesourcery.com>
  79             Ian Lance Taylor  <ian@wasabisystems.com>
  80             Ben Elliston  <bje@wasabisystems.com>
  81
  82         * arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
  83         only be used with the default multiply-add operation, so if N is
  84         set, don't bother printing X.  Add new iwmmxt instructions.
  85         (IWMMXT_INSN_COUNT): Update.
  86         (iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
  87         with a 'c' suffix.
  88         (print_insn_coprocessor): Check for iWMMXt2.  Handle format
  89         specifiers 'r', 'i'.
  90
  91 2006-09-24  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
  92
  93         PR binutils/3100
  94         * i386-dis.c (prefix_user_table): Fix the second operand of
  95         maskmovdqu instruction to allow only %xmm register instead of
  96         both %xmm register and memory.
  97
  98 2006-09-23  H.J. Lu  <hongjiu.lu@intel.com>
  99
 100         PR binutils/3235
 101         * i386-dis.c (OP_OFF64): Get 32bit offset if there is an
 102         address size prefix.
 103
 104 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 105
 106         * score-dis.c: New file.
 107         * score-opc.h: New file.
 108         * Makefile.am: Add Score files.
 109         * Makefile.in: Regenerate.
 110         * configure.in: Add support for Score target.
 111         * configure: Regenerate.
 112         * disassemble.c: Add support for Score target.
 113
 114 2006-09-16  Nick Clifton  <nickc@redhat.com>
 115             Pedro Alves  <pedro_alves@portugalmail.pt>
 116
 117         * arm-dis.c: Make use of new STRING_COMMA_LEN and CONST_STRNEQ
 118         macros defined in bfd.h.
 119         * cris-dis.c: Likewise.
 120         * h8300-dis.c: Likewise.
 121         * i386-dis.c: Likewise.
 122         * ia64-gen.c: Likewise.
 123         * mips-dis: Likewise.
 124
 125 2006-09-04  Paul Brook  <paul@codesourcery.com>
 126
 127         * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
 128
 129 2006-08-23  H.J. Lu  <hongjiu.lu@intel.com>
 130
 131         * i386-dis.c (three_byte_table): Expand to 256 elements.
 132
 133 2006-08-04  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 134
 135         PR binutils/3000
 136         * i386-dis.c (MXC,EMC): Define.
 137         (OP_MXC): New function to handle cvt* (convert instructions) between
 138         %xmm and %mm register correctly.
 139         (OP_EMC): ditto.
 140         (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
 141         instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
 142         with EMC/MXC.
 143
 144 2006-07-29  Richard Sandiford  <richard@codesourcery.com>
 145
 146         * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
 147         "fdaddl" entry.
 148
 149 2006-07-19  Paul Brook  <paul@codesourcery.com>
 150
 151         * armd-dis.c (arm_opcodes): Fix rbit opcode.
 152
 153 2006-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 154
 155         * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
 156         "sldt", "str" and "smsw".
 157
 158 2006-07-15  H.J. Lu  <hongjiu.lu@intel.com>
 159
 160         PR binutils/2829
 161         * i386-dis.c (GRP11_C6): NEW.
 162         (GRP11_C7): Likewise.
 163         (GRP12): Updated.
 164         (GRP13): Likewise.
 165         (GRP14): Likewise.
 166         (GRP15): Likewise.
 167         (GRP16): Likewise.
 168         (GRPAMD): Likewise.
 169         (GRPPADLCK1): Likewise.
 170         (GRPPADLCK2): Likewise.
 171         (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
 172         respectively.
 173         (grps): Add entries for GRP11_C6 and GRP11_C7.
 174
 175 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 176            Michael Meissner             <michael.meissner@amd.com>
 177
 178         * i386-dis.c (dis386): Add support for 4 operand instructions. Add
 179         support for amdfam10 SSE4a/ABM instructions. Modify all
 180         initializer macros to have additional arguments. Disallow REP
 181         prefix for non-string instructions.
 182         (print_insn): Ditto.
 183
 184 2006-07-05  Julian Brown  <julian@codesourcery.com>
 185
 186         * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
 187
 188 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 189
 190         * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
 191         (twobyte_has_modrm): Set 1 for 0x1f.
 192
 193 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 194
 195         * i386-dis.c (NOP_Fixup): Removed.
 196         (NOP_Fixup1): New.
 197         (NOP_Fixup2): Likewise.
 198         (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
 199
 200 2006-06-12  Julian Brown  <julian@codesourcery.com>
 201
 202         * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
 203         on 64-bit hosts.
 204
 205 2006-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 206
 207         * i386.c (GRP10): Renamed to ...
 208         (GRP12): This.
 209         (GRP11): Renamed to ...
 210         (GRP13): This.
 211         (GRP12): Renamed to ...
 212         (GRP14): This.
 213         (GRP13): Renamed to ...
 214         (GRP15): This.
 215         (GRP14): Renamed to ...
 216         (GRP16): This.
 217         (dis386_twobyte): Updated.
 218         (grps): Likewise.
 219
 220 2006-06-09  Nick Clifton  <nickc@redhat.com>
 221
 222         * po/fi.po: Updated Finnish translation.
 223
 224 2006-06-07  Joseph S. Myers  <joseph@codesourcery.com>
 225
 226         * po/Make-in (pdf, ps): New dummy targets.
 227
 228 2006-06-06  Paul Brook  <paul@codesourcery.com>
 229
 230         * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
 231         instructions.
 232         (neon_opcodes): Add conditional execution specifiers.
 233         (thumb_opcodes): Ditto.
 234         (thumb32_opcodes): Ditto.
 235         (arm_conditional): Change 0xe to "al" and add "" to end.
 236         (ifthen_state, ifthen_next_state, ifthen_address): New.
 237         (IFTHEN_COND): Define.
 238         (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
 239         (print_insn_arm): Change %c to use new values of arm_conditional.
 240         (print_insn_thumb16): Print thumb conditions.  Add %I.
 241         (print_insn_thumb32): Print thumb conditions.
 242         (find_ifthen_state): New function.
 243         (print_insn): Track IT block state.
 244
 245 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 246             Anton Blanchard  <anton@samba.org>
 247             Peter Bergner  <bergner@vnet.ibm.com>
 248
 249         * ppc-dis.c (powerpc_dialect): Handle power6 option.
 250         (print_ppc_disassembler_options): Mention power6.
 251
 252 2006-06-06  Thiemo Seufer  <ths@mips.com>
 253             Chao-ying Fu  <fu@mips.com>
 254
 255         * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
 256         * mips-opc.c: Add DSP64 instructions.
 257
 258 2006-06-06  Alan Modra  <amodra@bigpond.net.au>
 259
 260         * m68hc11-dis.c (print_insn): Warning fix.
 261
 262 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
 263
 264         * po/Make-in (top_builddir): Define.
 265
 266 2006-06-05  Alan Modra  <amodra@bigpond.net.au>
 267
 268         * Makefile.am: Run "make dep-am".
 269         * Makefile.in: Regenerate.
 270         * config.in: Regenerate.
 271
 272 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
 273
 274         * Makefile.am (INCLUDES): Use @INCINTL@.
 275         * acinclude.m4: Include new gettext macros.
 276         * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
 277         Remove local code for po/Makefile.
 278         * Makefile.in, aclocal.m4, configure: Regenerated.
 279
 280 2006-05-30  Nick Clifton  <nickc@redhat.com>
 281
 282         * po/es.po: Updated Spanish translation.
 283
 284 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 285
 286         * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
 287         and fmovem entries.  Put register list entries before immediate
 288         mask entries.  Use "l" rather than "L" in the fmovem entries.
 289         * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
 290         out from INFO.
 291         (m68k_scan_mask): New function, split out from...
 292         (print_insn_m68k): ...here.  If no architecture has been set,
 293         first try printing an m680x0 instruction, then try a Coldfire one.
 294
 295 2006-05-24  Nick Clifton  <nickc@redhat.com>
 296
 297         * po/ga.po: Updated Irish translation.
 298
 299 2006-05-22  Nick Clifton  <nickc@redhat.com>
 300
 301         * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
 302
 303 2006-05-22  Nick Clifton  <nickc@redhat.com>
 304
 305         * po/nl.po: Updated translation.
 306
 307 2006-05-18  Alan Modra  <amodra@bigpond.net.au>
 308
 309         * avr-dis.c: Formatting fix.
 310
 311 2006-05-14  Thiemo Seufer  <ths@mips.com>
 312
 313         * mips16-opc.c (I1, I32, I64): New shortcut defines.
 314         (mips16_opcodes): Change membership of instructions to their
 315         lowest baseline ISA.
 316
 317 2006-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 318
 319         * i386-dis.c (grps): Update sgdt/sidt for 64bit.
 320
 321 2006-05-05  Julian Brown  <julian@codesourcery.com>
 322
 323         * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
 324         vldm/vstm.
 325
 326 2006-05-05  Thiemo Seufer  <ths@mips.com>
 327             David Ung  <davidu@mips.com>
 328
 329         * mips-opc.c: Add macro for cache instruction.
 330
 331 2006-05-04  Thiemo Seufer  <ths@mips.com>
 332             Nigel Stephens  <nigel@mips.com>
 333             David Ung  <davidu@mips.com>
 334
 335         * mips-dis.c (mips_arch_choices): Add smartmips instruction
 336         decoding to MIPS32 and MIPS32R2.  Limit DSP decoding to release
 337         2 ISAs.  Add MIPS3D decoding to MIPS32R2.  Add MT decoding to
 338         MIPS64R2.
 339         * mips-opc.c: fix random typos in comments.
 340         (INSN_SMARTMIPS): New defines.
 341         (mips_builtin_opcodes): Add paired single support for MIPS32R2.
 342         Move bc3f, bc3fl, bc3t, bc3tl downwards.  Move flushi, flushd,
 343         flushid, wb upwards.  Move cfc3, ctc3 downwards.  Rework the
 344         FP_S and FP_D flags to denote single and double register
 345         accesses separately.  Move dmfc3, dmtc3, mfc3, mtc3 downwards.
 346         Allow jr.hb and jalr.hb for release 1 ISAs.  Allow luxc1, suxc1
 347         for MIPS32R2.  Add SmartMIPS instructions.  Add two-argument
 348         variants of bc2f, bc2fl, bc2t, bc2tl.  Add mfhc2, mthc2 to
 349         release 2 ISAs.
 350         * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
 351
 352 2006-05-03  Thiemo Seufer  <ths@mips.com>
 353
 354         * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
 355
 356 2006-05-02  Thiemo Seufer  <ths@mips.com>
 357             Nigel Stephens  <nigel@mips.com>
 358             David Ung  <davidu@mips.com>
 359
 360         * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
 361         (print_mips16_insn_arg): Force mips16 to odd addresses.
 362
 363 2006-04-30  Thiemo Seufer  <ths@mips.com>
 364             David Ung  <davidu@mips.com>
 365
 366         * mips-opc.c (mips_builtin_opcodes): Add udi instructions
 367         "udi0" to "udi15".
 368         * mips-dis.c (print_insn_args): Adds udi argument handling.
 369
 370 2006-04-28  James E Wilson  <wilson@specifix.com>
 371
 372         * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
 373         error message.
 374
 375 2006-04-28  Thiemo Seufer  <ths@mips.com>
 376             David Ung  <davidu@mips.com>
 377             Nigel Stephens  <nigel@mips.com>
 378
 379         * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
 380         names.
 381
 382 2006-04-28  Thiemo Seufer  <ths@mips.com>
 383             Nigel Stephens  <nigel@mips.com>
 384             David Ung  <davidu@mips.com>
 385
 386         * mips-dis.c (print_insn_args): Add mips_opcode argument.
 387         (print_insn_mips):  Adjust print_insn_args call.
 388
 389 2006-04-28  Thiemo Seufer  <ths@mips.com>
 390             Nigel Stephens  <nigel@mips.com>
 391
 392         * mips-dis.c (print_insn_args): Print $fcc only for FP
 393         instructions, use $cc elsewise.
 394
 395 2006-04-28  Thiemo Seufer  <ths@mips.com>
 396             Nigel Stephens  <nigel@mips.com>
 397
 398         * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
 399         Map MIPS16 registers to O32 names.
 400         (print_mips16_insn_arg): Use mips16_reg_names.
 401
 402 2006-04-26  Julian Brown  <julian@codesourcery.com>
 403
 404         * arm-dis.c (print_insn_neon): Disassemble floating-point constant
 405         VMOV.
 406
 407 2006-04-26  Nathan Sidwell  <nathan@codesourcery.com>
 408             Julian Brown  <julian@codesourcery.com>
 409
 410         * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
 411         %<code>[zy] into %[zy]<code>.  Expand meaning of %<bitfield>['`?].
 412         Add unified load/store instruction names.
 413         (neon_opcode_table): New.
 414         (arm_opcodes): Expand meaning of %<bitfield>['`?].
 415         (arm_decode_bitfield): New.
 416         (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
 417         Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
 418         (print_insn_neon): New.
 419         (print_insn_arm): Adjust print_insn_coprocessor call. Call
 420         print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
 421         (print_insn_thumb32): Likewise.
 422
 423 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 424
 425         * Makefile.am: Run "make dep-am".
 426         * Makefile.in: Regenerate.
 427
 428 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 429
 430         * avr-dis.c (avr_operand): Warning fix.
 431
 432         * configure: Regenerate.
 433
 434 2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>
 435
 436         * po/POTFILES.in: Regenerated.
 437
 438 2006-04-12   Hochstein  <hochstein@algo.informatik.tu-darmstadt.de>
 439
 440         PR binutils/2454
 441         * avr-dis.c (avr_operand): Arrange for a comment to appear before
 442         the symolic form of an address, so that the output of objdump -d
 443         can be reassembled.
 444
 445 2006-04-10  DJ Delorie  <dj@redhat.com>
 446
 447         * m32c-asm.c: Regenerate.
 448
 449 2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>
 450
 451         * Makefile.am: Add install-html target.
 452         * Makefile.in: Regenerate.
 453
 454 2006-04-06  Nick Clifton  <nickc@redhat.com>
 455
 456         * po/vi/po: Updated Vietnamese translation.
 457
 458 2006-03-31  Paul Koning  <ni1d@arrl.net>
 459
 460         * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
 461
 462 2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>
 463
 464         * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
 465         logic to identify halfword shifts.
 466
 467 2006-03-16  Paul Brook  <paul@codesourcery.com>
 468
 469         * arm-dis.c (arm_opcodes): Rename swi to svc.
 470         (thumb_opcodes): Ditto.
 471
 472 2006-03-13  DJ Delorie  <dj@redhat.com>
 473
 474         * m32c-asm.c: Regenerate.
 475         * m32c-desc.c: Likewise.
 476         * m32c-desc.h: Likewise.
 477         * m32c-dis.c: Likewise.
 478         * m32c-ibld.c: Likewise.
 479         * m32c-opc.c: Likewise.
 480         * m32c-opc.h: Likewise.
 481
 482 2006-03-10  DJ Delorie  <dj@redhat.com>
 483
 484         * m32c-desc.c: Regenerate with mul.l, mulu.l.
 485         * m32c-opc.c: Likewise.
 486         * m32c-opc.h: Likewise.
 487
 488
 489 2006-03-09  Nick Clifton  <nickc@redhat.com>
 490
 491         * po/sv.po: Updated Swedish translation.
 492
 493 2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>
 494
 495         PR binutils/2428
 496         * i386-dis.c (REP_Fixup): New function.
 497         (AL): Remove duplicate.
 498         (Xbr): New.
 499         (Xvr): Likewise.
 500         (Ybr): Likewise.
 501         (Yvr): Likewise.
 502         (indirDXr): Likewise.
 503         (ALr): Likewise.
 504         (eAXr): Likewise.
 505         (dis386): Updated entries of ins, outs, movs, lods and stos.
 506
 507 2006-03-05  Nick Clifton  <nickc@redhat.com>
 508
 509         * cgen-ibld.in (insert_normal): Cope with attempts to insert a
 510         signed 32-bit value into an unsigned 32-bit field when the host is
 511         a 64-bit machine.
 512         * fr30-ibld.c: Regenerate.
 513         * frv-ibld.c: Regenerate.
 514         * ip2k-ibld.c: Regenerate.
 515         * iq2000-asm.c: Regenerate.
 516         * iq2000-ibld.c: Regenerate.
 517         * m32c-ibld.c: Regenerate.
 518         * m32r-ibld.c: Regenerate.
 519         * openrisc-ibld.c: Regenerate.
 520         * xc16x-ibld.c: Regenerate.
 521         * xstormy16-ibld.c: Regenerate.
 522
 523 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
 524
 525         * xc16x-asm.c: Regenerate.
 526         * xc16x-dis.c: Regenerate.
 527
 528 2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>
 529
 530         * po/Make-in: Add html target.
 531
 532 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 533
 534         * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
 535         Intel Merom New Instructions.
 536         (THREE_BYTE_0): Likewise.
 537         (THREE_BYTE_1): Likewise.
 538         (three_byte_table): Likewise.
 539         (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
 540         THREE_BYTE_1 for entry 0x3a.
 541         (twobyte_has_modrm): Updated.
 542         (twobyte_uses_SSE_prefix): Likewise.
 543         (print_insn): Handle 3-byte opcodes used by Intel Merom New
 544         Instructions.
 545
 546 2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
 547
 548         * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
 549         (v9_hpriv_reg_names): New table.
 550         (print_insn_sparc): Allow values up to 16 for '?' and '!'.
 551         New cases '$' and '%' for read/write hyperprivileged register.
 552         * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
 553         window handling and rdhpr/wrhpr instructions.
 554
 555 2006-02-24  DJ Delorie  <dj@redhat.com>
 556
 557         * m32c-desc.c: Regenerate with linker relaxation attributes.
 558         * m32c-desc.h: Likewise.
 559         * m32c-dis.c: Likewise.
 560         * m32c-opc.c: Likewise.
 561
 562 2006-02-24  Paul Brook  <paul@codesourcery.com>
 563
 564         * arm-dis.c (arm_opcodes): Add V7 instructions.
 565         (thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
 566         (print_arm_address): New function.
 567         (print_insn_arm): Use it.  Add 'P' and 'U' cases.
 568         (psr_name): New function.
 569         (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
 570
 571 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 572
 573         * ia64-opc-i.c (bXc): New.
 574         (mXc): Likewise.
 575         (OpX2TaTbYaXcC): Likewise.
 576         (TF). Likewise.
 577         (TFCM). Likewise.
 578         (ia64_opcodes_i): Add instructions for tf.
 579
 580         * ia64-opc.h (IMMU5b): New.
 581
 582         * ia64-asmtab.c: Regenerated.
 583
 584 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 585
 586         * ia64-gen.c: Update copyright years.
 587         * ia64-opc-b.c: Likewise.
 588
 589 2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 590
 591         * ia64-gen.c (lookup_regindex): Handle ".vm".
 592         (print_dependency_table): Handle '\"'.
 593
 594         * ia64-ic.tbl: Updated from SDM 2.2.
 595         * ia64-raw.tbl: Likewise.
 596         * ia64-waw.tbl: Likewise.
 597         * ia64-asmtab.c: Regenerated.
 598
 599         * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
 600
 601 2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
 602             Anil Paranjape   <anilp1@kpitcummins.com>
 603             Shilin Shakti    <shilins@kpitcummins.com>
 604
 605         * xc16x-desc.h: New file
 606         * xc16x-desc.c: New file
 607         * xc16x-opc.h: New file
 608         * xc16x-opc.c: New file
 609         * xc16x-ibld.c: New file
 610         * xc16x-asm.c: New file
 611         * xc16x-dis.c: New file
 612         * Makefile.am: Entries for xc16x
 613         * Makefile.in: Regenerate
 614         * cofigure.in: Add xc16x target information.
 615         * configure: Regenerate.
 616         * disassemble.c: Add xc16x target information.
 617
 618 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 619
 620         * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
 621         moves.
 622
 623 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 624
 625         * i386-dis.c ('Z'): Add a new macro.
 626         (dis386_twobyte): Use "movZ" for control register moves.
 627
 628 2006-02-10  Nick Clifton  <nickc@redhat.com>
 629
 630         * iq2000-asm.c: Regenerate.
 631
 632 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 633
 634         * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
 635
 636 2006-01-26  David Ung  <davidu@mips.com>
 637
 638         * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
 639         ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
 640         floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
 641         nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
 642         rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
 643
 644 2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>
 645
 646         * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
 647         ld_d_r, pref_xd_cb): Use signed char to hold data to be
 648         disassembled.
 649         * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
 650         buffer overflows when disassembling instructions like
 651         ld (ix+123),0x23
 652         * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
 653         operand, if the offset is negative.
 654
 655 2006-01-17  Arnold Metselaar  <arnoldm@sourceware.org>
 656
 657         * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
 658         unsigned char to hold data to be disassembled.
 659
 660 2006-01-17  Andreas Schwab  <schwab@suse.de>
 661
 662         PR binutils/1486
 663         * disassemble.c (disassemble_init_for_target): Set
 664         disassembler_needs_relocs for bfd_arch_arm.
 665
 666 2006-01-16  Paul Brook  <paul@codesourcery.com>
 667
 668         * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
 669         f?add?, and f?sub? instructions.
 670
 671 2006-01-16  Nick Clifton  <nickc@redhat.com>
 672
 673         * po/zh_CN.po: New Chinese (simplified) translation.
 674         * configure.in (ALL_LINGUAS): Add "zh_CH".
 675         * configure: Regenerate.
 676
 677 2006-01-05  Paul Brook  <paul@codesourcery.com>
 678
 679         * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
 680
 681 2006-01-06  DJ Delorie  <dj@redhat.com>
 682
 683         * m32c-desc.c: Regenerate.
 684         * m32c-opc.c: Regenerate.
 685         * m32c-opc.h: Regenerate.
 686
 687 2006-01-03  DJ Delorie  <dj@redhat.com>
 688
 689         * cgen-ibld.in (extract_normal): Avoid memory range errors.
 690         * m32c-ibld.c: Regenerated.
 691
 692 For older changes see ChangeLog-2005
 693 \f
 694 Local Variables:
 695 mode: change-log
 696 left-margin: 8
 697 fill-column: 74
 698 version-control: never
 699 End: