opcodes/ChangeLog

   1 2019-07-01  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
   4         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
   5         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
   6         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
   7         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
   8         monitorx, mwaitx): Drop ImmExt from operand-less forms.
   9         * i386-tbl.h: Re-generate.
  10
  11 2019-07-01  Jan Beulich  <jbeulich@suse.com>
  12
  13         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
  14         register operands.
  15         * i386-tbl.h: Re-generate.
  16
  17 2019-07-01  Jan Beulich  <jbeulich@suse.com>
  18
  19         * i386-opc.tbl (C): New.
  20         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
  21         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
  22         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
  23         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
  24         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
  25         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
  26         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
  27         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
  28         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
  29         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
  30         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
  31         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
  32         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
  33         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
  34         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
  35         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
  36         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
  37         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
  38         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
  39         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
  40         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
  41         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
  42         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
  43         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
  44         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
  45         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
  46         flavors.
  47         * i386-tbl.h: Re-generate.
  48
  49 2019-07-01  Jan Beulich  <jbeulich@suse.com>
  50
  51         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
  52         register operands.
  53         * i386-tbl.h: Re-generate.
  54
  55 2019-07-01  Jan Beulich  <jbeulich@suse.com>
  56
  57         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
  58         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
  59         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
  60         * i386-tbl.h: Re-generate.
  61
  62 2019-07-01  Jan Beulich  <jbeulich@suse.com>
  63
  64         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
  65         Disp8MemShift from register only templates.
  66         * i386-tbl.h: Re-generate.
  67
  68 2019-07-01  Jan Beulich  <jbeulich@suse.com>
  69
  70         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
  71         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
  72         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
  73         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
  74         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
  75         EVEX_W_0F11_P_3_M_1): Delete.
  76         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
  77         EVEX_W_0F11_P_3): New.
  78         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
  79         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
  80         MOD_EVEX_0F11_PREFIX_3 table entries.
  81         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
  82         PREFIX_EVEX_0F11 table entries.
  83         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
  84         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
  85         EVEX_W_0F11_P_3_M_{0,1} table entries.
  86
  87 2019-07-01  Jan Beulich  <jbeulich@suse.com>
  88
  89         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
  90         Delete.
  91
  92 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
  93
  94         PR binutils/24719
  95         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
  96         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
  97         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
  98         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
  99         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 100         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 101         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 102         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 103         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 104         PREFIX_EVEX_0F38C6_REG_6 entries.
 105         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 106         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 107         EVEX_W_0F38C7_R_6_P_2 entries.
 108         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 109         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 110         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 111         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 112         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 113         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 114         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 115
 116 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 117
 118         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 119         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 120         VEX_LEN_0F2D_P_3): Delete.
 121         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 122         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 123         (prefix_table): ... here.
 124
 125 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 126
 127         * i386-dis.c (Iq): Delete.
 128         (Id): New.
 129         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 130         TBM insns.
 131         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 132         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 133         (OP_E_memory): Also honor needindex when deciding whether an
 134         address size prefix needs printing.
 135         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 136
 137 2019-06-26  Jim Wilson  <jimw@sifive.com>
 138
 139         PR binutils/24739
 140         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 141         Set info->display_endian to info->endian_code.
 142
 143 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 144
 145         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 146         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 147         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 148         OPERAND_TYPE_ACC64 entries.
 149         * i386-init.h: Re-generate.
 150
 151 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 152
 153         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 154         Delete.
 155         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 156         of dqa_mode.
 157         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 158         entries here.
 159         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 160         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 161
 162 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 163
 164         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 165         variables.
 166
 167 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 168
 169         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 170         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 171         movnti.
 172         * i386-opc.tbl (movnti): Add IgnoreSize.
 173         * i386-tbl.h: Re-generate.
 174
 175 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 176
 177         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 178         * i386-tbl.h: Re-generate.
 179
 180 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 181
 182         * i386-dis-evex.h: Break into ...
 183         * i386-dis-evex-len.h: New file.
 184         * i386-dis-evex-mod.h: Likewise.
 185         * i386-dis-evex-prefix.h: Likewise.
 186         * i386-dis-evex-reg.h: Likewise.
 187         * i386-dis-evex-w.h: Likewise.
 188         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 189         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 190         i386-dis-evex-mod.h.
 191
 192 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 193
 194         PR binutils/24700
 195         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 196         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 197         EVEX_W_0F385B_P_2.
 198         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 199         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 200         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 201         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 202         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 203         EVEX_LEN_0F385B_P_2_W_1.
 204         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 205         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 206         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 207         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 208         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 209         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 210         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 211         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 212         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 213         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 214
 215 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 216
 217         PR binutils/24691
 218         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 219         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 220         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 221         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 222         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 223         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 224         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 225         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 226         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 227         EVEX_LEN_0F3A43_P_2_W_1.
 228         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 229         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 230         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 231         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 232         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 233         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 234         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 235         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 236         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 237         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 238         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 239         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 240
 241 2019-06-14  Nick Clifton  <nickc@redhat.com>
 242
 243         * po/fr.po; Updated French translation.
 244
 245 2019-06-13  Stafford Horne  <shorne@gmail.com>
 246
 247         * or1k-asm.c: Regenerated.
 248         * or1k-desc.c: Regenerated.
 249         * or1k-desc.h: Regenerated.
 250         * or1k-dis.c: Regenerated.
 251         * or1k-ibld.c: Regenerated.
 252         * or1k-opc.c: Regenerated.
 253         * or1k-opc.h: Regenerated.
 254         * or1k-opinst.c: Regenerated.
 255
 256 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 257
 258         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 259
 260 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 261
 262         PR binutils/24633
 263         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 264         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 265         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 266         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 267         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 268         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 269         EVEX_LEN_0F3A1B_P_2_W_1.
 270         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 271         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 272         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 273         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 274         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 275         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 276         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 277         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 278
 279 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 280
 281         PR binutils/24626
 282         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 283         EVEX.vvvv when disassembling VEX and EVEX instructions.
 284         (OP_VEX): Set vex.register_specifier to 0 after readding
 285         vex.register_specifier.
 286         (OP_Vex_2src_1): Likewise.
 287         (OP_Vex_2src_2): Likewise.
 288         (OP_LWP_E): Likewise.
 289         (OP_EX_Vex): Don't check vex.register_specifier.
 290         (OP_XMM_Vex): Likewise.
 291
 292 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 293             Lili Cui  <lili.cui@intel.com>
 294
 295         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 296         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 297         instructions.
 298         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 299         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 300         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 301         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 302         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 303         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 304         * i386-init.h: Regenerated.
 305         * i386-tbl.h: Likewise.
 306
 307 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 308             Lili Cui  <lili.cui@intel.com>
 309
 310         * doc/c-i386.texi: Document enqcmd.
 311         * testsuite/gas/i386/enqcmd-intel.d: New file.
 312         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 313         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 314         * testsuite/gas/i386/enqcmd.d: Likewise.
 315         * testsuite/gas/i386/enqcmd.s: Likewise.
 316         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 317         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 318         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 319         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 320         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 321         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 322         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 323         and x86-64-enqcmd.
 324
 325 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 326
 327         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 328
 329 2019-06-03  Alan Modra  <amodra@gmail.com>
 330
 331         * ppc-dis.c (prefix_opcd_indices): Correct size.
 332
 333 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 334
 335         PR gas/24625
 336         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 337         Disp8ShiftVL.
 338         * i386-tbl.h: Regenerated.
 339
 340 2019-05-24  Alan Modra  <amodra@gmail.com>
 341
 342         * po/POTFILES.in: Regenerate.
 343
 344 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 345             Alan Modra  <amodra@gmail.com>
 346
 347         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 348         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 349         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 350         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 351         XTOP>): Define and add entries.
 352         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 353         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 354         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 355         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 356
 357 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 358             Alan Modra  <amodra@gmail.com>
 359
 360         * ppc-dis.c (ppc_opts): Add "future" entry.
 361         (PREFIX_OPCD_SEGS): Define.
 362         (prefix_opcd_indices): New array.
 363         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 364         (lookup_prefix): New function.
 365         (print_insn_powerpc): Handle 64-bit prefix instructions.
 366         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 367         (PMRR, POWERXX): Define.
 368         (prefix_opcodes): New instruction table.
 369         (prefix_num_opcodes): New constant.
 370
 371 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 372
 373         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 374         * configure: Regenerated.
 375         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 376         and cpu/bpf.opc.
 377         (HFILES): Add bpf-desc.h and bpf-opc.h.
 378         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 379         bpf-ibld.c and bpf-opc.c.
 380         (BPF_DEPS): Define.
 381         * Makefile.in: Regenerated.
 382         * disassemble.c (ARCH_bpf): Define.
 383         (disassembler): Add case for bfd_arch_bpf.
 384         (disassemble_init_for_target): Likewise.
 385         (enum epbf_isa_attr): Define.
 386         * disassemble.h: extern print_insn_bpf.
 387         * bpf-asm.c: Generated.
 388         * bpf-opc.h: Likewise.
 389         * bpf-opc.c: Likewise.
 390         * bpf-ibld.c: Likewise.
 391         * bpf-dis.c: Likewise.
 392         * bpf-desc.h: Likewise.
 393         * bpf-desc.c: Likewise.
 394
 395 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 396
 397         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 398         and VMSR with the new operands.
 399
 400 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 401
 402         * arm-dis.c (enum mve_instructions): New enum
 403         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 404         and cneg.
 405         (mve_opcodes): New instructions as above.
 406         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 407         csneg and csel.
 408         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 409
 410 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 411
 412         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 413         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 414         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 415         uqshl, urshrl and urshr.
 416         (is_mve_okay_in_it): Add new instructions to TRUE list.
 417         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 418         (print_insn_mve): Updated to accept new %j,
 419         %<bitfield>m and %<bitfield>n patterns.
 420
 421 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 422
 423         * mips-opc.c (mips_builtin_opcodes): Change source register
 424         constraint for DAUI.
 425
 426 2019-05-20  Nick Clifton  <nickc@redhat.com>
 427
 428         * po/fr.po: Updated French translation.
 429
 430 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 431             Michael Collison <michael.collison@arm.com>
 432
 433         * arm-dis.c (thumb32_opcodes): Add new instructions.
 434         (enum mve_instructions): Likewise.
 435         (enum mve_undefined): Add new reasons.
 436         (is_mve_encoding_conflict): Handle new instructions.
 437         (is_mve_undefined): Likewise.
 438         (is_mve_unpredictable): Likewise.
 439         (print_mve_undefined): Likewise.
 440         (print_mve_size): Likewise.
 441
 442 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 443             Michael Collison <michael.collison@arm.com>
 444
 445         * arm-dis.c (thumb32_opcodes): Add new instructions.
 446         (enum mve_instructions): Likewise.
 447         (is_mve_encoding_conflict): Handle new instructions.
 448         (is_mve_undefined): Likewise.
 449         (is_mve_unpredictable): Likewise.
 450         (print_mve_size): Likewise.
 451
 452 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 453             Michael Collison <michael.collison@arm.com>
 454
 455         * arm-dis.c (thumb32_opcodes): Add new instructions.
 456         (enum mve_instructions): Likewise.
 457         (is_mve_encoding_conflict): Likewise.
 458         (is_mve_unpredictable): Likewise.
 459         (print_mve_size): Likewise.
 460
 461 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 462             Michael Collison <michael.collison@arm.com>
 463
 464         * arm-dis.c (thumb32_opcodes): Add new instructions.
 465         (enum mve_instructions): Likewise.
 466         (is_mve_encoding_conflict): Handle new instructions.
 467         (is_mve_undefined): Likewise.
 468         (is_mve_unpredictable): Likewise.
 469         (print_mve_size): Likewise.
 470
 471 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 472             Michael Collison <michael.collison@arm.com>
 473
 474         * arm-dis.c (thumb32_opcodes): Add new instructions.
 475         (enum mve_instructions): Likewise.
 476         (is_mve_encoding_conflict): Handle new instructions.
 477         (is_mve_undefined): Likewise.
 478         (is_mve_unpredictable): Likewise.
 479         (print_mve_size): Likewise.
 480         (print_insn_mve): Likewise.
 481
 482 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 483             Michael Collison <michael.collison@arm.com>
 484
 485         * arm-dis.c (thumb32_opcodes): Add new instructions.
 486         (print_insn_thumb32): Handle new instructions.
 487
 488 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 489             Michael Collison <michael.collison@arm.com>
 490
 491         * arm-dis.c (enum mve_instructions): Add new instructions.
 492         (enum mve_undefined): Add new reasons.
 493         (is_mve_encoding_conflict): Handle new instructions.
 494         (is_mve_undefined): Likewise.
 495         (is_mve_unpredictable): Likewise.
 496         (print_mve_undefined): Likewise.
 497         (print_mve_size): Likewise.
 498         (print_mve_shift_n): Likewise.
 499         (print_insn_mve): Likewise.
 500
 501 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 502             Michael Collison <michael.collison@arm.com>
 503
 504         * arm-dis.c (enum mve_instructions): Add new instructions.
 505         (is_mve_encoding_conflict): Handle new instructions.
 506         (is_mve_unpredictable): Likewise.
 507         (print_mve_rotate): Likewise.
 508         (print_mve_size): Likewise.
 509         (print_insn_mve): Likewise.
 510
 511 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 512             Michael Collison <michael.collison@arm.com>
 513
 514         * arm-dis.c (enum mve_instructions): Add new instructions.
 515         (is_mve_encoding_conflict): Handle new instructions.
 516         (is_mve_unpredictable): Likewise.
 517         (print_mve_size): Likewise.
 518         (print_insn_mve): Likewise.
 519
 520 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 521             Michael Collison <michael.collison@arm.com>
 522
 523         * arm-dis.c (enum mve_instructions): Add new instructions.
 524         (enum mve_undefined): Add new reasons.
 525         (is_mve_encoding_conflict): Handle new instructions.
 526         (is_mve_undefined): Likewise.
 527         (is_mve_unpredictable): Likewise.
 528         (print_mve_undefined): Likewise.
 529         (print_mve_size): Likewise.
 530         (print_insn_mve): Likewise.
 531
 532 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 533             Michael Collison <michael.collison@arm.com>
 534
 535         * arm-dis.c (enum mve_instructions): Add new instructions.
 536         (is_mve_encoding_conflict): Handle new instructions.
 537         (is_mve_undefined): Likewise.
 538         (is_mve_unpredictable): Likewise.
 539         (print_mve_size): Likewise.
 540         (print_insn_mve): Likewise.
 541
 542 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 543             Michael Collison <michael.collison@arm.com>
 544
 545         * arm-dis.c (enum mve_instructions): Add new instructions.
 546         (enum mve_unpredictable): Add new reasons.
 547         (enum mve_undefined): Likewise.
 548         (is_mve_okay_in_it): Handle new isntructions.
 549         (is_mve_encoding_conflict): Likewise.
 550         (is_mve_undefined): Likewise.
 551         (is_mve_unpredictable): Likewise.
 552         (print_mve_vmov_index): Likewise.
 553         (print_simd_imm8): Likewise.
 554         (print_mve_undefined): Likewise.
 555         (print_mve_unpredictable): Likewise.
 556         (print_mve_size): Likewise.
 557         (print_insn_mve): Likewise.
 558
 559 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 560             Michael Collison <michael.collison@arm.com>
 561
 562         * arm-dis.c (enum mve_instructions): Add new instructions.
 563         (enum mve_unpredictable): Add new reasons.
 564         (enum mve_undefined): Likewise.
 565         (is_mve_encoding_conflict): Handle new instructions.
 566         (is_mve_undefined): Likewise.
 567         (is_mve_unpredictable): Likewise.
 568         (print_mve_undefined): Likewise.
 569         (print_mve_unpredictable): Likewise.
 570         (print_mve_rounding_mode): Likewise.
 571         (print_mve_vcvt_size): Likewise.
 572         (print_mve_size): Likewise.
 573         (print_insn_mve): Likewise.
 574
 575 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 576             Michael Collison <michael.collison@arm.com>
 577
 578         * arm-dis.c (enum mve_instructions): Add new instructions.
 579         (enum mve_unpredictable): Add new reasons.
 580         (enum mve_undefined): Likewise.
 581         (is_mve_undefined): Handle new instructions.
 582         (is_mve_unpredictable): Likewise.
 583         (print_mve_undefined): Likewise.
 584         (print_mve_unpredictable): Likewise.
 585         (print_mve_size): Likewise.
 586         (print_insn_mve): Likewise.
 587
 588 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 589             Michael Collison <michael.collison@arm.com>
 590
 591         * arm-dis.c (enum mve_instructions): Add new instructions.
 592         (enum mve_undefined): Add new reasons.
 593         (insns): Add new instructions.
 594         (is_mve_encoding_conflict):
 595         (print_mve_vld_str_addr): New print function.
 596         (is_mve_undefined): Handle new instructions.
 597         (is_mve_unpredictable): Likewise.
 598         (print_mve_undefined): Likewise.
 599         (print_mve_size): Likewise.
 600         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 601         (print_insn_mve):  Handle new operands.
 602
 603 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 604             Michael Collison <michael.collison@arm.com>
 605
 606         * arm-dis.c (enum mve_instructions): Add new instructions.
 607         (enum mve_unpredictable): Add new reasons.
 608         (is_mve_encoding_conflict): Handle new instructions.
 609         (is_mve_unpredictable): Likewise.
 610         (mve_opcodes): Add new instructions.
 611         (print_mve_unpredictable): Handle new reasons.
 612         (print_mve_register_blocks): New print function.
 613         (print_mve_size): Handle new instructions.
 614         (print_insn_mve): Likewise.
 615
 616 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 617             Michael Collison <michael.collison@arm.com>
 618
 619         * arm-dis.c (enum mve_instructions): Add new instructions.
 620         (enum mve_unpredictable): Add new reasons.
 621         (enum mve_undefined): Likewise.
 622         (is_mve_encoding_conflict): Handle new instructions.
 623         (is_mve_undefined): Likewise.
 624         (is_mve_unpredictable): Likewise.
 625         (coprocessor_opcodes): Move NEON VDUP from here...
 626         (neon_opcodes): ... to here.
 627         (mve_opcodes): Add new instructions.
 628         (print_mve_undefined):  Handle new reasons.
 629         (print_mve_unpredictable): Likewise.
 630         (print_mve_size): Handle new instructions.
 631         (print_insn_neon): Handle vdup.
 632         (print_insn_mve): Handle new operands.
 633
 634 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 635             Michael Collison <michael.collison@arm.com>
 636
 637         * arm-dis.c (enum mve_instructions): Add new instructions.
 638         (enum mve_unpredictable): Add new values.
 639         (mve_opcodes): Add new instructions.
 640         (vec_condnames): New array with vector conditions.
 641         (mve_predicatenames): New array with predicate suffixes.
 642         (mve_vec_sizename): New array with vector sizes.
 643         (enum vpt_pred_state): New enum with vector predication states.
 644         (struct vpt_block): New struct type for vpt blocks.
 645         (vpt_block_state): Global struct to keep track of state.
 646         (mve_extract_pred_mask): New helper function.
 647         (num_instructions_vpt_block): Likewise.
 648         (mark_outside_vpt_block): Likewise.
 649         (mark_inside_vpt_block): Likewise.
 650         (invert_next_predicate_state): Likewise.
 651         (update_next_predicate_state): Likewise.
 652         (update_vpt_block_state): Likewise.
 653         (is_vpt_instruction): Likewise.
 654         (is_mve_encoding_conflict): Add entries for new instructions.
 655         (is_mve_unpredictable): Likewise.
 656         (print_mve_unpredictable): Handle new cases.
 657         (print_instruction_predicate): Likewise.
 658         (print_mve_size): New function.
 659         (print_vec_condition): New function.
 660         (print_insn_mve): Handle vpt blocks and new print operands.
 661
 662 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 663
 664         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 665         8, 14 and 15 for Armv8.1-M Mainline.
 666
 667 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 668             Michael Collison <michael.collison@arm.com>
 669
 670         * arm-dis.c (enum mve_instructions): New enum.
 671         (enum mve_unpredictable): Likewise.
 672         (enum mve_undefined): Likewise.
 673         (struct mopcode32): New struct.
 674         (is_mve_okay_in_it): New function.
 675         (is_mve_architecture): Likewise.
 676         (arm_decode_field): Likewise.
 677         (arm_decode_field_multiple): Likewise.
 678         (is_mve_encoding_conflict): Likewise.
 679         (is_mve_undefined): Likewise.
 680         (is_mve_unpredictable): Likewise.
 681         (print_mve_undefined): Likewise.
 682         (print_mve_unpredictable): Likewise.
 683         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 684         (print_insn_mve): New function.
 685         (print_insn_thumb32): Handle MVE architecture.
 686         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 687
 688 2019-05-10  Nick Clifton  <nickc@redhat.com>
 689
 690         PR 24538
 691         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 692         end of the table prematurely.
 693
 694 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 695
 696         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 697         macros for R6.
 698
 699 2019-05-11  Alan Modra  <amodra@gmail.com>
 700
 701         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 702         when -Mraw is in effect.
 703
 704 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 705
 706         * aarch64-dis-2.c: Regenerate.
 707         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 708         (OP_SVE_BBB): New variant set.
 709         (OP_SVE_DDDD): New variant set.
 710         (OP_SVE_HHH): New variant set.
 711         (OP_SVE_HHHU): New variant set.
 712         (OP_SVE_SSS): New variant set.
 713         (OP_SVE_SSSU): New variant set.
 714         (OP_SVE_SHH): New variant set.
 715         (OP_SVE_SBBU): New variant set.
 716         (OP_SVE_DSS): New variant set.
 717         (OP_SVE_DHHU): New variant set.
 718         (OP_SVE_VMV_HSD_BHS): New variant set.
 719         (OP_SVE_VVU_HSD_BHS): New variant set.
 720         (OP_SVE_VVVU_SD_BH): New variant set.
 721         (OP_SVE_VVVU_BHSD): New variant set.
 722         (OP_SVE_VVV_QHD_DBS): New variant set.
 723         (OP_SVE_VVV_HSD_BHS): New variant set.
 724         (OP_SVE_VVV_HSD_BHS2): New variant set.
 725         (OP_SVE_VVV_BHS_HSD): New variant set.
 726         (OP_SVE_VV_BHS_HSD): New variant set.
 727         (OP_SVE_VVV_SD): New variant set.
 728         (OP_SVE_VVU_BHS_HSD): New variant set.
 729         (OP_SVE_VZVV_SD): New variant set.
 730         (OP_SVE_VZVV_BH): New variant set.
 731         (OP_SVE_VZV_SD): New variant set.
 732         (aarch64_opcode_table): Add sve2 instructions.
 733
 734 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 735
 736         * aarch64-asm-2.c: Regenerated.
 737         * aarch64-dis-2.c: Regenerated.
 738         * aarch64-opc-2.c: Regenerated.
 739         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 740         for SVE_SHLIMM_UNPRED_22.
 741         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 742         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 743         operand.
 744
 745 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 746
 747         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 748         sve_size_tsz_bhs iclass encode.
 749         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 750         sve_size_tsz_bhs iclass decode.
 751
 752 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 753
 754         * aarch64-asm-2.c: Regenerated.
 755         * aarch64-dis-2.c: Regenerated.
 756         * aarch64-opc-2.c: Regenerated.
 757         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 758         for SVE_Zm4_11_INDEX.
 759         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 760         (fields): Handle SVE_i2h field.
 761         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 762         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 763
 764 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 765
 766         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 767         sve_shift_tsz_bhsd iclass encode.
 768         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 769         sve_shift_tsz_bhsd iclass decode.
 770
 771 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 772
 773         * aarch64-asm-2.c: Regenerated.
 774         * aarch64-dis-2.c: Regenerated.
 775         * aarch64-opc-2.c: Regenerated.
 776         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 777         (aarch64_encode_variant_using_iclass): Handle
 778         sve_shift_tsz_hsd iclass encode.
 779         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 780         sve_shift_tsz_hsd iclass decode.
 781         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 782         for SVE_SHRIMM_UNPRED_22.
 783         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 784         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 785         operand.
 786
 787 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 788
 789         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 790         sve_size_013 iclass encode.
 791         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 792         sve_size_013 iclass decode.
 793
 794 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 795
 796         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 797         sve_size_bh iclass encode.
 798         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 799         sve_size_bh iclass decode.
 800
 801 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 802
 803         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 804         sve_size_sd2 iclass encode.
 805         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 806         sve_size_sd2 iclass decode.
 807         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 808         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 809
 810 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 811
 812         * aarch64-asm-2.c: Regenerated.
 813         * aarch64-dis-2.c: Regenerated.
 814         * aarch64-opc-2.c: Regenerated.
 815         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 816         for SVE_ADDR_ZX.
 817         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 818         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 819
 820 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 821
 822         * aarch64-asm-2.c: Regenerated.
 823         * aarch64-dis-2.c: Regenerated.
 824         * aarch64-opc-2.c: Regenerated.
 825         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 826         for SVE_Zm3_11_INDEX.
 827         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 828         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 829         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 830         fields.
 831         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 832
 833 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 834
 835         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 836         sve_size_hsd2 iclass encode.
 837         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 838         sve_size_hsd2 iclass decode.
 839         * aarch64-opc.c (fields): Handle SVE_size field.
 840         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 841
 842 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 843
 844         * aarch64-asm-2.c: Regenerated.
 845         * aarch64-dis-2.c: Regenerated.
 846         * aarch64-opc-2.c: Regenerated.
 847         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 848         for SVE_IMM_ROT3.
 849         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 850         (fields): Handle SVE_rot3 field.
 851         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 852         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 853
 854 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 855
 856         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 857         instructions.
 858
 859 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 860
 861         * aarch64-tbl.h
 862         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 863         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 864         aarch64_feature_sve2bitperm): New feature sets.
 865         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 866         for feature set addresses.
 867         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 868         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 869
 870 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 871             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 872
 873         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 874         argument and set ASE_EVA_R6 appropriately.
 875         (set_default_mips_dis_options): Pass ISA to above.
 876         (parse_mips_dis_option): Likewise.
 877         * mips-opc.c (EVAR6): New macro.
 878         (mips_builtin_opcodes): Add llwpe, scwpe.
 879
 880 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 881
 882         * aarch64-asm-2.c: Regenerated.
 883         * aarch64-dis-2.c: Regenerated.
 884         * aarch64-opc-2.c: Regenerated.
 885         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 886         AARCH64_OPND_TME_UIMM16.
 887         (aarch64_print_operand): Likewise.
 888         * aarch64-tbl.h (QL_IMM_NIL): New.
 889         (TME): New.
 890         (_TME_INSN): New.
 891         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 892
 893 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 894
 895         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 896
 897 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 898             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 899
 900         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 901
 902 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 903
 904         * s12z-opc.h: Add extern "C" bracketing to help
 905         users who wish to use this interface in c++ code.
 906
 907 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 908
 909         * s12z-opc.c (bm_decode): Handle bit map operations with the
 910         "reserved0" mode.
 911
 912 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 913
 914         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 915         specifier.  Add entries for VLDR and VSTR of system registers.
 916         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 917         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 918         of %J and %K format specifier.
 919
 920 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 921
 922         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 923         Add new entries for VSCCLRM instruction.
 924         (print_insn_coprocessor): Handle new %C format control code.
 925
 926 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 927
 928         * arm-dis.c (enum isa): New enum.
 929         (struct sopcode32): New structure.
 930         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 931         set isa field of all current entries to ANY.
 932         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 933         Only match an entry if its isa field allows the current mode.
 934
 935 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 936
 937         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 938         CLRM.
 939         (print_insn_thumb32): Add logic to print %n CLRM register list.
 940
 941 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 942
 943         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 944         and %Q patterns.
 945
 946 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 947
 948         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 949         (print_insn_thumb32): Edit the switch case for %Z.
 950
 951 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 952
 953         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 954
 955 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 956
 957         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 958
 959 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 960
 961         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 962
 963 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 964
 965         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 966         Arm register with r13 and r15 unpredictable.
 967         (thumb32_opcodes): New instructions for bfx and bflx.
 968
 969 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 970
 971         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 972
 973 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 974
 975         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 976
 977 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 978
 979         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 980
 981 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 982
 983         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 984
 985 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 986
 987         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 988         "optr". ("operator" is a reserved word in c++).
 989
 990 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 991
 992         * aarch64-opc.c (aarch64_print_operand): Add case for
 993         AARCH64_OPND_Rt_SP.
 994         (verify_constraints): Likewise.
 995         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 996         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 997         to accept Rt|SP as first operand.
 998         (AARCH64_OPERANDS): Add new Rt_SP.
 999         * aarch64-asm-2.c: Regenerated.
1000         * aarch64-dis-2.c: Regenerated.
1001         * aarch64-opc-2.c: Regenerated.
1002
1003 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1004
1005         * aarch64-asm-2.c: Regenerated.
1006         * aarch64-dis-2.c: Likewise.
1007         * aarch64-opc-2.c: Likewise.
1008         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1009
1010 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1011
1012         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1013
1014 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1015
1016         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1017         * i386-init.h: Regenerated.
1018
1019 2019-04-07  Alan Modra  <amodra@gmail.com>
1020
1021         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1022         op_separator to control printing of spaces, comma and parens
1023         rather than need_comma, need_paren and spaces vars.
1024
1025 2019-04-07  Alan Modra  <amodra@gmail.com>
1026
1027         PR 24421
1028         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1029         (print_insn_neon, print_insn_arm): Likewise.
1030
1031 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1032
1033         * i386-dis-evex.h (evex_table): Updated to support BF16
1034         instructions.
1035         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1036         and EVEX_W_0F3872_P_3.
1037         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1038         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1039         * i386-opc.h (enum): Add CpuAVX512_BF16.
1040         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1041         * i386-opc.tbl: Add AVX512 BF16 instructions.
1042         * i386-init.h: Regenerated.
1043         * i386-tbl.h: Likewise.
1044
1045 2019-04-05  Alan Modra  <amodra@gmail.com>
1046
1047         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1048         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1049         to favour printing of "-" branch hint when using the "y" bit.
1050         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1051
1052 2019-04-05  Alan Modra  <amodra@gmail.com>
1053
1054         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1055         opcode until first operand is output.
1056
1057 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1058
1059         PR gas/24349
1060         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1061         (valid_bo_post_v2): Add support for 'at' branch hints.
1062         (insert_bo): Only error on branch on ctr.
1063         (get_bo_hint_mask): New function.
1064         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1065         for inserting 'at' branch hints.
1066         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1067         for extracting 'at' branch hints.
1068         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1069         (BOE): Delete operand.
1070         (BOM, BOP): New operands.
1071         (RM): Update value.
1072         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1073         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1074         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1075         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1076         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1077         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1078         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1079         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1080         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1081         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1082         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1083         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1084         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1085         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1086         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1087         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1088         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1089         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1090         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1091         bttarl+>: New extended mnemonics.
1092
1093 2019-03-28  Alan Modra  <amodra@gmail.com>
1094
1095         PR 24390
1096         * ppc-opc.c (BTF): Define.
1097         (powerpc_opcodes): Use for mtfsb*.
1098         * ppc-dis.c (print_insn_powerpc): Print fields with both
1099         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1100
1101 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1102
1103         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1104         (mapping_symbol_for_insn): Implement new algorithm.
1105         (print_insn): Remove duplicate code.
1106
1107 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1108
1109         * aarch64-dis.c (print_insn_aarch64):
1110         Implement override.
1111
1112 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1113
1114         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1115         order.
1116
1117 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1118
1119         * aarch64-dis.c (last_stop_offset): New.
1120         (print_insn_aarch64): Use stop_offset.
1121
1122 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1123
1124         PR gas/24359
1125         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1126         CPU_ANY_AVX2_FLAGS.
1127         * i386-init.h: Regenerated.
1128
1129 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1130
1131         PR gas/24348
1132         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1133         vmovdqu16, vmovdqu32 and vmovdqu64.
1134         * i386-tbl.h: Regenerated.
1135
1136 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1137
1138         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1139         from vstrszb, vstrszh, and vstrszf.
1140
1141 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1142
1143         * s390-opc.txt: Add instruction descriptions.
1144
1145 2019-02-08  Jim Wilson  <jimw@sifive.com>
1146
1147         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1148         <bne>: Likewise.
1149
1150 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1151
1152         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1153
1154 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1155
1156         PR binutils/23212
1157         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1158         * aarch64-opc.c (verify_elem_sd): New.
1159         (fields): Add FLD_sz entr.
1160         * aarch64-tbl.h (_SIMD_INSN): New.
1161         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1162         fmulx scalar and vector by element isns.
1163
1164 2019-02-07  Nick Clifton  <nickc@redhat.com>
1165
1166         * po/sv.po: Updated Swedish translation.
1167
1168 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1169
1170         * s390-mkopc.c (main): Accept arch13 as cpu string.
1171         * s390-opc.c: Add new instruction formats and instruction opcode
1172         masks.
1173         * s390-opc.txt: Add new arch13 instructions.
1174
1175 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1176
1177         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1178         (aarch64_opcode): Change encoding for stg, stzg
1179         st2g and st2zg.
1180         * aarch64-asm-2.c: Regenerated.
1181         * aarch64-dis-2.c: Regenerated.
1182         * aarch64-opc-2.c: Regenerated.
1183
1184 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1185
1186         * aarch64-asm-2.c: Regenerated.
1187         * aarch64-dis-2.c: Likewise.
1188         * aarch64-opc-2.c: Likewise.
1189         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1190
1191 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1192             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1193
1194         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1195         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1196         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1197         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1198         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1199         case for ldstgv_indexed.
1200         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1201         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1202         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1203         * aarch64-asm-2.c: Regenerated.
1204         * aarch64-dis-2.c: Regenerated.
1205         * aarch64-opc-2.c: Regenerated.
1206
1207 2019-01-23  Nick Clifton  <nickc@redhat.com>
1208
1209         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1210
1211 2019-01-21  Nick Clifton  <nickc@redhat.com>
1212
1213         * po/de.po: Updated German translation.
1214         * po/uk.po: Updated Ukranian translation.
1215
1216 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1217         * mips-dis.c (mips_arch_choices): Fix typo in
1218         gs464, gs464e and gs264e descriptors.
1219
1220 2019-01-19  Nick Clifton  <nickc@redhat.com>
1221
1222         * configure: Regenerate.
1223         * po/opcodes.pot: Regenerate.
1224
1225 2018-06-24  Nick Clifton  <nickc@redhat.com>
1226
1227         2.32 branch created.
1228
1229 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1230
1231         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1232         if it is null.
1233         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1234         zero.
1235
1236 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1237
1238         * configure: Regenerate.
1239
1240 2019-01-07  Alan Modra  <amodra@gmail.com>
1241
1242         * configure: Regenerate.
1243         * po/POTFILES.in: Regenerate.
1244
1245 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1246
1247         * s12z-opc.c: New file.
1248         * s12z-opc.h: New file.
1249         * s12z-dis.c: Removed all code not directly related to display
1250         of instructions.  Used the interface provided by the new files
1251         instead.
1252         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1253         * Makefile.in: Regenerate.
1254         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1255         * configure: Regenerate.
1256
1257 2019-01-01  Alan Modra  <amodra@gmail.com>
1258
1259         Update year range in copyright notice of all files.
1260
1261 For older changes see ChangeLog-2018
1262 \f
1263 Copyright (C) 2019 Free Software Foundation, Inc.
1264
1265 Copying and distribution of this file, with or without modification,
1266 are permitted in any medium without royalty provided the copyright
1267 notice and this notice are preserved.
1268
1269 Local Variables:
1270 mode: change-log
1271 left-margin: 8
1272 fill-column: 74
1273 version-control: never
1274 End: