opcodes/ChangeLog

   1 2019-11-14  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-gen.c (opcode_modifiers): Add AnySize entry.
   4         (operand_types): Remove AnySize entry.
   5         * i386-opc.h (AnySize): Move between enums.
   6         (struct i386_opcode_modifier): Add anysize field.
   7         (OTUnused): Un-comment.
   8         (union i386_operand_type): Remove anysize field.
   9         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
  10         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
  11         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
  12         AnySize.
  13         * i386-tbl.h: Re-generate.
  14
  15 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
  16
  17         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
  18         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
  19         use the floating point register (FPR).
  20
  21 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
  22
  23         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
  24         cmode 1101.
  25         (is_mve_encoding_conflict): Update cmode conflict checks for
  26         MVE_VMVN_IMM.
  27
  28 2019-11-12  Jan Beulich  <jbeulich@suse.com>
  29
  30         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
  31         entry.
  32         (operand_types): Remove EsSeg entry.
  33         (main): Replace stale use of OTMax.
  34         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
  35         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
  36         (EsSeg): Delete.
  37         (OTUnused): Comment out.
  38         (union i386_operand_type): Remove esseg field.
  39         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
  40         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
  41         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
  42         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
  43         * i386-init.h, i386-tbl.h: Re-generate.
  44
  45 2019-11-12  Jan Beulich  <jbeulich@suse.com>
  46
  47         * i386-gen.c (operand_instances): Add RegB entry.
  48         * i386-opc.h (enum operand_instance): Add RegB.
  49         * i386-opc.tbl (RegC, RegD, RegB): Define.
  50         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
  51         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
  52         monitorx, mwaitx): Drop ImmExt and convert encodings
  53         accordingly.
  54         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
  55         (edx, rdx): Add Instance=RegD.
  56         (ebx, rbx): Add Instance=RegB.
  57         * i386-tbl.h: Re-generate.
  58
  59 2019-11-12  Jan Beulich  <jbeulich@suse.com>
  60
  61         * i386-gen.c (operand_type_init): Adjust
  62         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
  63         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
  64         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
  65         (operand_instances): New.
  66         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
  67         (output_operand_type): New parameter "instance". Process it.
  68         (process_i386_operand_type): New local variable "instance".
  69         (main): Adjust static assertions.
  70         * i386-opc.h (INSTANCE_WIDTH): Define.
  71         (enum operand_instance): New.
  72         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
  73         (union i386_operand_type): Replace acc, inoutportreg, and
  74         shiftcount by instance.
  75         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
  76         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
  77         Add Instance=.
  78         * i386-init.h, i386-tbl.h: Re-generate.
  79
  80 2019-11-11  Jan Beulich  <jbeulich@suse.com>
  81
  82         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
  83         smaxp/sminp entries' "tied_operand" field to 2.
  84
  85 2019-11-11  Jan Beulich  <jbeulich@suse.com>
  86
  87         * aarch64-opc.c (operand_general_constraint_met_p): Replace
  88         "index" local variable by that of the already existing "num".
  89
  90 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
  91
  92         PR gas/25167
  93         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
  94         * i386-tbl.h: Regenerated.
  95
  96 2019-11-08  Jan Beulich  <jbeulich@suse.com>
  97
  98         * i386-gen.c (operand_type_init): Add Class= to
  99         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 100         OPERAND_TYPE_REGBND entry.
 101         (operand_classes): Add RegMask and RegBND entries.
 102         (operand_types): Drop RegMask and RegBND entry.
 103         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 104         (RegMask, RegBND): Delete.
 105         (union i386_operand_type): Remove regmask and regbnd fields.
 106         * i386-opc.tbl (RegMask, RegBND): Define.
 107         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 108         Class=RegBND.
 109         * i386-init.h, i386-tbl.h: Re-generate.
 110
 111 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 112
 113         * i386-gen.c (operand_type_init): Add Class= to
 114         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 115         OPERAND_TYPE_REGZMM entries.
 116         (operand_classes): Add RegMMX and RegSIMD entries.
 117         (operand_types): Drop RegMMX and RegSIMD entries.
 118         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 119         (RegMMX, RegSIMD): Delete.
 120         (union i386_operand_type): Remove regmmx and regsimd fields.
 121         * i386-opc.tbl (RegMMX): Define.
 122         (RegXMM, RegYMM, RegZMM): Add Class=.
 123         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 124         Class=RegSIMD.
 125         * i386-init.h, i386-tbl.h: Re-generate.
 126
 127 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 128
 129         * i386-gen.c (operand_type_init): Add Class= to
 130         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 131         entries.
 132         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 133         (operand_types): Drop Control, Debug, and Test entries.
 134         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 135         (Control, Debug, Test): Delete.
 136         (union i386_operand_type): Remove control, debug, and test
 137         fields.
 138         * i386-opc.tbl (Control, Debug, Test): Define.
 139         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 140         Class=RegDR, and Test by Class=RegTR.
 141         * i386-init.h, i386-tbl.h: Re-generate.
 142
 143 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 144
 145         * i386-gen.c (operand_type_init): Add Class= to
 146         OPERAND_TYPE_SREG entry.
 147         (operand_classes): Add SReg entry.
 148         (operand_types): Drop SReg entry.
 149         * i386-opc.h (enum operand_class): Add SReg.
 150         (SReg): Delete.
 151         (union i386_operand_type): Remove sreg field.
 152         * i386-opc.tbl (SReg): Define.
 153         * i386-reg.tbl: Replace SReg by Class=SReg.
 154         * i386-init.h, i386-tbl.h: Re-generate.
 155
 156 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 157
 158         * i386-gen.c (operand_type_init): Add Class=. New
 159         OPERAND_TYPE_ANYIMM entry.
 160         (operand_classes): New.
 161         (operand_types): Drop Reg entry.
 162         (output_operand_type): New parameter "class". Process it.
 163         (process_i386_operand_type): New local variable "class".
 164         (main): Adjust static assertions.
 165         * i386-opc.h (CLASS_WIDTH): Define.
 166         (enum operand_class): New.
 167         (Reg): Replace by Class. Adjust comment.
 168         (union i386_operand_type): Replace reg by class.
 169         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 170         Class=.
 171         * i386-reg.tbl: Replace Reg by Class=Reg.
 172         * i386-init.h: Re-generate.
 173
 174 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 175
 176         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 177         (aarch64_opcode_table): Add data gathering hint mnemonic.
 178         * opcodes/aarch64-dis-2.c: Account for new instruction.
 179
 180 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 181
 182         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 183
 184
 185 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 186
 187         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 188         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 189         aarch64_feature_f64mm): New feature sets.
 190         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 191         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 192         instructions.
 193         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 194         macros.
 195         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 196         (OP_SVE_QQQ): New qualifier.
 197         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 198         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 199         the movprfx constraint.
 200         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 201         (aarch64_opcode_table): Define new instructions smmla,
 202         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 203         uzip{1/2}, trn{1/2}.
 204         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 205         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 206         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 207         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 208         Account for new instructions.
 209         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 210         S4x32 operand.
 211         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 212
 213 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 214 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 215
 216         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 217         Armv8.6-A.
 218         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 219         (neon_opcodes): Add bfloat SIMD instructions.
 220         (print_insn_coprocessor): Add new control character %b to print
 221         condition code without checking cp_num.
 222         (print_insn_neon): Account for BFloat16 instructions that have no
 223         special top-byte handling.
 224
 225 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 226 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 227
 228         * arm-dis.c (print_insn_coprocessor,
 229         print_insn_generic_coprocessor): Create wrapper functions around
 230         the implementation of the print_insn_coprocessor control codes.
 231         (print_insn_coprocessor_1): Original print_insn_coprocessor
 232         function that now takes which array to look at as an argument.
 233         (print_insn_arm): Use both print_insn_coprocessor and
 234         print_insn_generic_coprocessor.
 235         (print_insn_thumb32): As above.
 236
 237 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 238 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 239
 240         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 241         in reglane special case.
 242         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 243         aarch64_find_next_opcode): Account for new instructions.
 244         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 245         in reglane special case.
 246         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 247         new AARCH64_OPND_QLF_S_2H qualifier.
 248         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 249         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 250         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 251         sets.
 252         (BFLOAT_SVE, BFLOAT): New feature set macros.
 253         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 254         instructions.
 255         (aarch64_opcode_table): Define new instructions bfdot,
 256         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 257         bfcvtn2, bfcvt.
 258
 259 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 260 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 261
 262         * aarch64-tbl.h (ARMV8_6): New macro.
 263
 264 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 265
 266         * i386-dis.c (prefix_table): Add mcommit.
 267         (rm_table): Add rdpru.
 268         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 269         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 270         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 271         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 272         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 273         * i386-opc.tbl (mcommit, rdpru): New.
 274         * i386-init.h, i386-tbl.h: Re-generate.
 275
 276 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 277
 278         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 279         "names32" instead.
 280         (OP_Monitor): Drop local variable "op1_names", re-purpose
 281         "names" for it instead, and replace former "names" uses by
 282         "names32" ones.
 283
 284 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 285
 286         PR/gas 25167
 287         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 288         operand-less forms.
 289         * opcodes/i386-tbl.h: Re-generate.
 290
 291 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 292
 293         * i386-dis.c (OP_Mwaitx): Delete.
 294         (prefix_table): Use OP_Mwait for mwaitx entry.
 295         (OP_Mwait): Also handle mwaitx.
 296
 297 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 298
 299         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 300         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 301         (prefix_table): Add respective entries.
 302         (rm_table): Link to those entries.
 303
 304 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 305
 306         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 307         (REG_0F1C_P_0_MOD_0): ... this.
 308         (REG_0F1E_MOD_3): Rename to ...
 309         (REG_0F1E_P_1_MOD_3): ... this.
 310         (RM_0F01_REG_5): Rename to ...
 311         (RM_0F01_REG_5_MOD_3): ... this.
 312         (RM_0F01_REG_7): Rename to ...
 313         (RM_0F01_REG_7_MOD_3): ... this.
 314         (RM_0F1E_MOD_3_REG_7): Rename to ...
 315         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 316         (RM_0FAE_REG_6): Rename to ...
 317         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 318         (RM_0FAE_REG_7): Rename to ...
 319         (RM_0FAE_REG_7_MOD_3): ... this.
 320         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 321         (PREFIX_0F01_REG_5_MOD_0): ... this.
 322         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 323         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 324         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 325         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 326         (PREFIX_0FAE_REG_0): Rename to ...
 327         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 328         (PREFIX_0FAE_REG_1): Rename to ...
 329         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 330         (PREFIX_0FAE_REG_2): Rename to ...
 331         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 332         (PREFIX_0FAE_REG_3): Rename to ...
 333         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 334         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 335         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 336         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 337         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 338         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 339         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 340         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 341         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 342         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 343         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 344         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 345         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 346         (PREFIX_0FAE_REG_7): Rename to ...
 347         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 348         (PREFIX_MOD_0_0FC3): Rename to ...
 349         (PREFIX_0FC3_MOD_0): ... this.
 350         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 351         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 352         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 353         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 354         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 355         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 356         (reg_table, prefix_table, mod_table, rm_table): Adjust
 357         accordingly.
 358
 359 2019-11-04  Nick Clifton  <nickc@redhat.com>
 360
 361         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 362         of a v850 system register.  Move the v850_sreg_names array into
 363         this function.
 364         (get_v850_reg_name): Likewise for ordinary register names.
 365         (get_v850_vreg_name): Likewise for vector register names.
 366         (get_v850_cc_name): Likewise for condition codes.
 367         * get_v850_float_cc_name): Likewise for floating point condition
 368         codes.
 369         (get_v850_cacheop_name): Likewise for cache-ops.
 370         (get_v850_prefop_name): Likewise for pref-ops.
 371         (disassemble): Use the new accessor functions.
 372
 373 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 374
 375         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 376         immediate for the writeback form of ldraa/ldrab if it is 0.
 377         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 378         * aarch64-opc-2.c: Regenerated.
 379
 380 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 381
 382         * i386-gen.c (operand_type_shorthands): Delete.
 383         (operand_type_init): Expand previous shorthands.
 384         (set_bitfield_from_shorthand): Rename back to ...
 385         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 386         of operand_type_init[].
 387         (set_bitfield): Adjust call to the above function.
 388         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 389         RegXMM, RegYMM, RegZMM): Define.
 390         * i386-reg.tbl: Expand prior shorthands.
 391
 392 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 393
 394         * i386-gen.c (output_i386_opcode): Change order of fields
 395         emitted to output.
 396         * i386-opc.h (struct insn_template): Move operands field.
 397         Convert extension_opcode field to unsigned short.
 398         * i386-tbl.h: Re-generate.
 399
 400 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 401
 402         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 403         of W.
 404         * i386-opc.h (W): Extend comment.
 405         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 406         general purpose variants not allowing for byte operands.
 407         * i386-tbl.h: Re-generate.
 408
 409 2019-10-29  Nick Clifton  <nickc@redhat.com>
 410
 411         * tic30-dis.c (print_branch): Correct size of operand array.
 412
 413 2019-10-29  Nick Clifton  <nickc@redhat.com>
 414
 415         * d30v-dis.c (print_insn): Check that operand index is valid
 416         before attempting to access the operands array.
 417
 418 2019-10-29  Nick Clifton  <nickc@redhat.com>
 419
 420         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 421         locating the bit to be tested.
 422
 423 2019-10-29  Nick Clifton  <nickc@redhat.com>
 424
 425         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 426         values.
 427         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 428         (print_insn_s12z):  Check for illegal size values.
 429
 430 2019-10-28  Nick Clifton  <nickc@redhat.com>
 431
 432         * csky-dis.c (csky_chars_to_number): Check for a negative
 433         count. Use an unsigned integer to construct the return value.
 434
 435 2019-10-28  Nick Clifton  <nickc@redhat.com>
 436
 437         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 438         operand buffer.  Set value to 15 not 13.
 439         (get_register_operand): Use OPERAND_BUFFER_LEN.
 440         (get_indirect_operand): Likewise.
 441         (print_two_operand): Likewise.
 442         (print_three_operand): Likewise.
 443         (print_oar_insn): Likewise.
 444
 445 2019-10-28  Nick Clifton  <nickc@redhat.com>
 446
 447         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 448         (bit_extract_simple): Likewise.
 449         (bit_copy): Likewise.
 450         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 451         index_offset array are not accessed.
 452
 453 2019-10-28  Nick Clifton  <nickc@redhat.com>
 454
 455         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 456         operand.
 457
 458 2019-10-25  Nick Clifton  <nickc@redhat.com>
 459
 460         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 461         access to opcodes.op array element.
 462
 463 2019-10-23  Nick Clifton  <nickc@redhat.com>
 464
 465         * rx-dis.c (get_register_name): Fix spelling typo in error
 466         message.
 467         (get_condition_name, get_flag_name, get_double_register_name)
 468         (get_double_register_high_name, get_double_register_low_name)
 469         (get_double_control_register_name, get_double_condition_name)
 470         (get_opsize_name, get_size_name): Likewise.
 471
 472 2019-10-22  Nick Clifton  <nickc@redhat.com>
 473
 474         * rx-dis.c (get_size_name): New function.  Provides safe
 475         access to name array.
 476         (get_opsize_name): Likewise.
 477         (print_insn_rx): Use the accessor functions.
 478
 479 2019-10-16  Nick Clifton  <nickc@redhat.com>
 480
 481         * rx-dis.c (get_register_name): New function.  Provides safe
 482         access to name array.
 483         (get_condition_name, get_flag_name, get_double_register_name)
 484         (get_double_register_high_name, get_double_register_low_name)
 485         (get_double_control_register_name, get_double_condition_name):
 486         Likewise.
 487         (print_insn_rx): Use the accessor functions.
 488
 489 2019-10-09  Nick Clifton  <nickc@redhat.com>
 490
 491         PR 25041
 492         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 493         instructions.
 494
 495 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 496
 497         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 498         (cmpsd): Likewise. Move EsSeg to other operand.
 499         * opcodes/i386-tbl.h: Re-generate.
 500
 501 2019-09-23  Alan Modra  <amodra@gmail.com>
 502
 503         * m68k-dis.c: Include cpu-m68k.h
 504
 505 2019-09-23  Alan Modra  <amodra@gmail.com>
 506
 507         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 508         "elf/mips.h" earlier.
 509
 510 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 511
 512         PR gas/25012
 513         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 514         with SReg operand.
 515         * i386-tbl.h: Re-generate.
 516
 517 2019-09-18  Alan Modra  <amodra@gmail.com>
 518
 519         * arc-ext.c: Update throughout for bfd section macro changes.
 520
 521 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 522
 523         * Makefile.in: Re-generate.
 524         * configure: Re-generate.
 525
 526 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 527
 528         * riscv-opc.c (riscv_opcodes): Change subset field
 529         to insn_class field for all instructions.
 530         (riscv_insn_types): Likewise.
 531
 532 2019-09-16  Phil Blundell  <pb@pbcl.net>
 533
 534         * configure: Regenerated.
 535
 536 2019-09-10  Miod Vallat  <miod@online.fr>
 537
 538         PR 24982
 539         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 540
 541 2019-09-09  Phil Blundell  <pb@pbcl.net>
 542
 543         binutils 2.33 branch created.
 544
 545 2019-09-03  Nick Clifton  <nickc@redhat.com>
 546
 547         PR 24961
 548         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 549         greater than zero before indexing via (bufcnt -1).
 550
 551 2019-09-03  Nick Clifton  <nickc@redhat.com>
 552
 553         PR 24958
 554         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 555         (MAX_SPEC_REG_NAME_LEN): Define.
 556         (struct mmix_dis_info): Use defined constants for array lengths.
 557         (get_reg_name): New function.
 558         (get_sprec_reg_name): New function.
 559         (print_insn_mmix): Use new functions.
 560
 561 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 562
 563         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 564         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 565         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 566
 567 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 568
 569         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 570         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 571         (aarch64_sys_reg_supported_p): Update checks for the above.
 572
 573 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 574
 575         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 576         cases MVE_SQRSHRL and MVE_UQRSHLL.
 577         (print_insn_mve): Add case for specifier 'k' to check
 578         specific bit of the instruction.
 579
 580 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 581
 582         PR 24854
 583         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 584         encountering an unknown machine type.
 585         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 586         cases return -1 rather than calling abort.
 587
 588 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 589
 590         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 591         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 592         IgnoreSize.
 593         * i386-tbl.h: Re-generate.
 594
 595 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 596
 597         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 598         instructions.
 599
 600 2019-07-30  Mel Chen <mel.chen@sifive.com>
 601
 602         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 603         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 604
 605         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 606         fscsr.
 607
 608 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 609
 610         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 611         and MPY class instructions.
 612         (parse_option): Add nps400 option.
 613         (print_arc_disassembler_options): Add nps400 info.
 614
 615 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 616
 617         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 618         (bspop): Likewise.
 619         (modapp): Likewise.
 620         * arc-opc.c (RAD_CHK): Add.
 621         * arc-tbl.h: Regenerate.
 622
 623 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 624
 625         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 626         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 627
 628 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 629
 630         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 631         instructions as UNPREDICTABLE.
 632
 633 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 634
 635         * bpf-desc.c: Regenerated.
 636
 637 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 638
 639         * i386-gen.c (static_assert): Define.
 640         (main): Use it.
 641         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 642         (Opcode_Modifier_Num): ... this.
 643         (Mem): Delete.
 644
 645 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 646
 647         * i386-gen.c (operand_types): Move RegMem ...
 648         (opcode_modifiers): ... here.
 649         * i386-opc.h (RegMem): Move to opcode modifer enum.
 650         (union i386_operand_type): Move regmem field ...
 651         (struct i386_opcode_modifier): ... here.
 652         * i386-opc.tbl (RegMem): Define.
 653         (mov, movq): Move RegMem on segment, control, debug, and test
 654         register flavors.
 655         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 656         to non-SSE2AVX flavor.
 657         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 658         Move RegMem on register only flavors. Drop IgnoreSize from
 659         legacy encoding flavors.
 660         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 661         flavors.
 662         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 663         register only flavors.
 664         (vmovd): Move RegMem and drop IgnoreSize on register only
 665         flavor. Change opcode and operand order to store form.
 666         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 667
 668 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 669
 670         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 671         entries.
 672         * i386-opc.h (SReg2, SReg3): Replace by ...
 673         (SReg): ... this.
 674         (union i386_operand_type): Replace sreg fields.
 675         * i386-opc.tbl (mov, ): Use SReg.
 676         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 677         register flavors.
 678         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 679         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 680
 681 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 682
 683         * bpf-desc.c: Regenerate.
 684         * bpf-opc.c: Likewise.
 685         * bpf-opc.h: Likewise.
 686
 687 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 688
 689         * bpf-desc.c: Regenerate.
 690         * bpf-opc.c: Likewise.
 691
 692 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 693
 694         * arm-dis.c (print_insn_coprocessor): Rename index to
 695         index_operand.
 696
 697 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 698
 699         * riscv-opc.c (riscv_insn_types): Add r4 type.
 700
 701         * riscv-opc.c (riscv_insn_types): Add b and j type.
 702
 703         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 704         format for sb type and correct s type.
 705
 706 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 707
 708         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 709         SVE FMOV alias of FCPY.
 710
 711 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 712
 713         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 714         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 715
 716 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 717
 718         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 719         registers in an instruction prefixed by MOVPRFX.
 720
 721 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 722
 723         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 724         sve_size_13 icode to account for variant behaviour of
 725         pmull{t,b}.
 726         * aarch64-dis-2.c: Regenerate.
 727         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 728         sve_size_13 icode to account for variant behaviour of
 729         pmull{t,b}.
 730         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 731         (OP_SVE_VVV_Q_D): Add new qualifier.
 732         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 733         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 734         AES and those not.
 735
 736 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 737
 738         * opcodes/i386-gen.c (operand_type_init): Remove
 739         OPERAND_TYPE_VEC_IMM4 entry.
 740         (operand_types): Remove Vec_Imm4.
 741         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 742         (union i386_operand_type): Remove vec_imm4.
 743         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 744         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 745
 746 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 747
 748         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 749         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 750         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 751         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 752         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 753         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 754         * i386-tbl.h: Re-generate.
 755
 756 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 757
 758         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 759         register operands.
 760         * i386-tbl.h: Re-generate.
 761
 762 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 763
 764         * i386-opc.tbl (C): New.
 765         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 766         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 767         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 768         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 769         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 770         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 771         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 772         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 773         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 774         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 775         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 776         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 777         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 778         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 779         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 780         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 781         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 782         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 783         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 784         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 785         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 786         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 787         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 788         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 789         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 790         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 791         flavors.
 792         * i386-tbl.h: Re-generate.
 793
 794 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 795
 796         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 797         register operands.
 798         * i386-tbl.h: Re-generate.
 799
 800 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 801
 802         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 803         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 804         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 805         * i386-tbl.h: Re-generate.
 806
 807 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 808
 809         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 810         Disp8MemShift from register only templates.
 811         * i386-tbl.h: Re-generate.
 812
 813 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 814
 815         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 816         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 817         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 818         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 819         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 820         EVEX_W_0F11_P_3_M_1): Delete.
 821         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 822         EVEX_W_0F11_P_3): New.
 823         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 824         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 825         MOD_EVEX_0F11_PREFIX_3 table entries.
 826         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 827         PREFIX_EVEX_0F11 table entries.
 828         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 829         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 830         EVEX_W_0F11_P_3_M_{0,1} table entries.
 831
 832 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 833
 834         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 835         Delete.
 836
 837 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 838
 839         PR binutils/24719
 840         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 841         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 842         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 843         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 844         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 845         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 846         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 847         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 848         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 849         PREFIX_EVEX_0F38C6_REG_6 entries.
 850         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 851         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 852         EVEX_W_0F38C7_R_6_P_2 entries.
 853         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 854         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 855         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 856         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 857         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 858         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 859         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 860
 861 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 862
 863         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 864         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 865         VEX_LEN_0F2D_P_3): Delete.
 866         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 867         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 868         (prefix_table): ... here.
 869
 870 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 871
 872         * i386-dis.c (Iq): Delete.
 873         (Id): New.
 874         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 875         TBM insns.
 876         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 877         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 878         (OP_E_memory): Also honor needindex when deciding whether an
 879         address size prefix needs printing.
 880         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 881
 882 2019-06-26  Jim Wilson  <jimw@sifive.com>
 883
 884         PR binutils/24739
 885         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 886         Set info->display_endian to info->endian_code.
 887
 888 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 889
 890         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 891         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 892         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 893         OPERAND_TYPE_ACC64 entries.
 894         * i386-init.h: Re-generate.
 895
 896 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 897
 898         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 899         Delete.
 900         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 901         of dqa_mode.
 902         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 903         entries here.
 904         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 905         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 906
 907 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 908
 909         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 910         variables.
 911
 912 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 913
 914         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 915         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 916         movnti.
 917         * i386-opc.tbl (movnti): Add IgnoreSize.
 918         * i386-tbl.h: Re-generate.
 919
 920 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 921
 922         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 923         * i386-tbl.h: Re-generate.
 924
 925 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 926
 927         * i386-dis-evex.h: Break into ...
 928         * i386-dis-evex-len.h: New file.
 929         * i386-dis-evex-mod.h: Likewise.
 930         * i386-dis-evex-prefix.h: Likewise.
 931         * i386-dis-evex-reg.h: Likewise.
 932         * i386-dis-evex-w.h: Likewise.
 933         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 934         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 935         i386-dis-evex-mod.h.
 936
 937 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 938
 939         PR binutils/24700
 940         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 941         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 942         EVEX_W_0F385B_P_2.
 943         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 944         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 945         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 946         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 947         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 948         EVEX_LEN_0F385B_P_2_W_1.
 949         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 950         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 951         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 952         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 953         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 954         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 955         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 956         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 957         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 958         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 959
 960 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 961
 962         PR binutils/24691
 963         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 964         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 965         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 966         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 967         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 968         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 969         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 970         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 971         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 972         EVEX_LEN_0F3A43_P_2_W_1.
 973         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 974         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 975         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 976         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 977         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 978         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 979         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 980         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 981         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 982         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 983         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 984         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 985
 986 2019-06-14  Nick Clifton  <nickc@redhat.com>
 987
 988         * po/fr.po; Updated French translation.
 989
 990 2019-06-13  Stafford Horne  <shorne@gmail.com>
 991
 992         * or1k-asm.c: Regenerated.
 993         * or1k-desc.c: Regenerated.
 994         * or1k-desc.h: Regenerated.
 995         * or1k-dis.c: Regenerated.
 996         * or1k-ibld.c: Regenerated.
 997         * or1k-opc.c: Regenerated.
 998         * or1k-opc.h: Regenerated.
 999         * or1k-opinst.c: Regenerated.
1000
1001 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1002
1003         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1004
1005 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1006
1007         PR binutils/24633
1008         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1009         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1010         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1011         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1012         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1013         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1014         EVEX_LEN_0F3A1B_P_2_W_1.
1015         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1016         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1017         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1018         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1019         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1020         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1021         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1022         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1023
1024 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1025
1026         PR binutils/24626
1027         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1028         EVEX.vvvv when disassembling VEX and EVEX instructions.
1029         (OP_VEX): Set vex.register_specifier to 0 after readding
1030         vex.register_specifier.
1031         (OP_Vex_2src_1): Likewise.
1032         (OP_Vex_2src_2): Likewise.
1033         (OP_LWP_E): Likewise.
1034         (OP_EX_Vex): Don't check vex.register_specifier.
1035         (OP_XMM_Vex): Likewise.
1036
1037 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1038             Lili Cui  <lili.cui@intel.com>
1039
1040         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1041         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1042         instructions.
1043         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1044         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1045         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1046         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1047         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1048         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1049         * i386-init.h: Regenerated.
1050         * i386-tbl.h: Likewise.
1051
1052 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1053             Lili Cui  <lili.cui@intel.com>
1054
1055         * doc/c-i386.texi: Document enqcmd.
1056         * testsuite/gas/i386/enqcmd-intel.d: New file.
1057         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1058         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1059         * testsuite/gas/i386/enqcmd.d: Likewise.
1060         * testsuite/gas/i386/enqcmd.s: Likewise.
1061         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1062         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1063         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1064         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1065         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1066         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1067         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1068         and x86-64-enqcmd.
1069
1070 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1071
1072         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1073
1074 2019-06-03  Alan Modra  <amodra@gmail.com>
1075
1076         * ppc-dis.c (prefix_opcd_indices): Correct size.
1077
1078 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1079
1080         PR gas/24625
1081         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1082         Disp8ShiftVL.
1083         * i386-tbl.h: Regenerated.
1084
1085 2019-05-24  Alan Modra  <amodra@gmail.com>
1086
1087         * po/POTFILES.in: Regenerate.
1088
1089 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1090             Alan Modra  <amodra@gmail.com>
1091
1092         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1093         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1094         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1095         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1096         XTOP>): Define and add entries.
1097         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1098         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1099         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1100         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1101
1102 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1103             Alan Modra  <amodra@gmail.com>
1104
1105         * ppc-dis.c (ppc_opts): Add "future" entry.
1106         (PREFIX_OPCD_SEGS): Define.
1107         (prefix_opcd_indices): New array.
1108         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1109         (lookup_prefix): New function.
1110         (print_insn_powerpc): Handle 64-bit prefix instructions.
1111         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1112         (PMRR, POWERXX): Define.
1113         (prefix_opcodes): New instruction table.
1114         (prefix_num_opcodes): New constant.
1115
1116 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1117
1118         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1119         * configure: Regenerated.
1120         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1121         and cpu/bpf.opc.
1122         (HFILES): Add bpf-desc.h and bpf-opc.h.
1123         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1124         bpf-ibld.c and bpf-opc.c.
1125         (BPF_DEPS): Define.
1126         * Makefile.in: Regenerated.
1127         * disassemble.c (ARCH_bpf): Define.
1128         (disassembler): Add case for bfd_arch_bpf.
1129         (disassemble_init_for_target): Likewise.
1130         (enum epbf_isa_attr): Define.
1131         * disassemble.h: extern print_insn_bpf.
1132         * bpf-asm.c: Generated.
1133         * bpf-opc.h: Likewise.
1134         * bpf-opc.c: Likewise.
1135         * bpf-ibld.c: Likewise.
1136         * bpf-dis.c: Likewise.
1137         * bpf-desc.h: Likewise.
1138         * bpf-desc.c: Likewise.
1139
1140 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1141
1142         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1143         and VMSR with the new operands.
1144
1145 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1146
1147         * arm-dis.c (enum mve_instructions): New enum
1148         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1149         and cneg.
1150         (mve_opcodes): New instructions as above.
1151         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1152         csneg and csel.
1153         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1154
1155 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1156
1157         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1158         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1159         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1160         uqshl, urshrl and urshr.
1161         (is_mve_okay_in_it): Add new instructions to TRUE list.
1162         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1163         (print_insn_mve): Updated to accept new %j,
1164         %<bitfield>m and %<bitfield>n patterns.
1165
1166 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1167
1168         * mips-opc.c (mips_builtin_opcodes): Change source register
1169         constraint for DAUI.
1170
1171 2019-05-20  Nick Clifton  <nickc@redhat.com>
1172
1173         * po/fr.po: Updated French translation.
1174
1175 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1176             Michael Collison <michael.collison@arm.com>
1177
1178         * arm-dis.c (thumb32_opcodes): Add new instructions.
1179         (enum mve_instructions): Likewise.
1180         (enum mve_undefined): Add new reasons.
1181         (is_mve_encoding_conflict): Handle new instructions.
1182         (is_mve_undefined): Likewise.
1183         (is_mve_unpredictable): Likewise.
1184         (print_mve_undefined): Likewise.
1185         (print_mve_size): Likewise.
1186
1187 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1188             Michael Collison <michael.collison@arm.com>
1189
1190         * arm-dis.c (thumb32_opcodes): Add new instructions.
1191         (enum mve_instructions): Likewise.
1192         (is_mve_encoding_conflict): Handle new instructions.
1193         (is_mve_undefined): Likewise.
1194         (is_mve_unpredictable): Likewise.
1195         (print_mve_size): Likewise.
1196
1197 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1198             Michael Collison <michael.collison@arm.com>
1199
1200         * arm-dis.c (thumb32_opcodes): Add new instructions.
1201         (enum mve_instructions): Likewise.
1202         (is_mve_encoding_conflict): Likewise.
1203         (is_mve_unpredictable): Likewise.
1204         (print_mve_size): Likewise.
1205
1206 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1207             Michael Collison <michael.collison@arm.com>
1208
1209         * arm-dis.c (thumb32_opcodes): Add new instructions.
1210         (enum mve_instructions): Likewise.
1211         (is_mve_encoding_conflict): Handle new instructions.
1212         (is_mve_undefined): Likewise.
1213         (is_mve_unpredictable): Likewise.
1214         (print_mve_size): Likewise.
1215
1216 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1217             Michael Collison <michael.collison@arm.com>
1218
1219         * arm-dis.c (thumb32_opcodes): Add new instructions.
1220         (enum mve_instructions): Likewise.
1221         (is_mve_encoding_conflict): Handle new instructions.
1222         (is_mve_undefined): Likewise.
1223         (is_mve_unpredictable): Likewise.
1224         (print_mve_size): Likewise.
1225         (print_insn_mve): Likewise.
1226
1227 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1228             Michael Collison <michael.collison@arm.com>
1229
1230         * arm-dis.c (thumb32_opcodes): Add new instructions.
1231         (print_insn_thumb32): Handle new instructions.
1232
1233 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1234             Michael Collison <michael.collison@arm.com>
1235
1236         * arm-dis.c (enum mve_instructions): Add new instructions.
1237         (enum mve_undefined): Add new reasons.
1238         (is_mve_encoding_conflict): Handle new instructions.
1239         (is_mve_undefined): Likewise.
1240         (is_mve_unpredictable): Likewise.
1241         (print_mve_undefined): Likewise.
1242         (print_mve_size): Likewise.
1243         (print_mve_shift_n): Likewise.
1244         (print_insn_mve): Likewise.
1245
1246 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1247             Michael Collison <michael.collison@arm.com>
1248
1249         * arm-dis.c (enum mve_instructions): Add new instructions.
1250         (is_mve_encoding_conflict): Handle new instructions.
1251         (is_mve_unpredictable): Likewise.
1252         (print_mve_rotate): Likewise.
1253         (print_mve_size): Likewise.
1254         (print_insn_mve): Likewise.
1255
1256 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1257             Michael Collison <michael.collison@arm.com>
1258
1259         * arm-dis.c (enum mve_instructions): Add new instructions.
1260         (is_mve_encoding_conflict): Handle new instructions.
1261         (is_mve_unpredictable): Likewise.
1262         (print_mve_size): Likewise.
1263         (print_insn_mve): Likewise.
1264
1265 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1266             Michael Collison <michael.collison@arm.com>
1267
1268         * arm-dis.c (enum mve_instructions): Add new instructions.
1269         (enum mve_undefined): Add new reasons.
1270         (is_mve_encoding_conflict): Handle new instructions.
1271         (is_mve_undefined): Likewise.
1272         (is_mve_unpredictable): Likewise.
1273         (print_mve_undefined): Likewise.
1274         (print_mve_size): Likewise.
1275         (print_insn_mve): Likewise.
1276
1277 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1278             Michael Collison <michael.collison@arm.com>
1279
1280         * arm-dis.c (enum mve_instructions): Add new instructions.
1281         (is_mve_encoding_conflict): Handle new instructions.
1282         (is_mve_undefined): Likewise.
1283         (is_mve_unpredictable): Likewise.
1284         (print_mve_size): Likewise.
1285         (print_insn_mve): Likewise.
1286
1287 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1288             Michael Collison <michael.collison@arm.com>
1289
1290         * arm-dis.c (enum mve_instructions): Add new instructions.
1291         (enum mve_unpredictable): Add new reasons.
1292         (enum mve_undefined): Likewise.
1293         (is_mve_okay_in_it): Handle new isntructions.
1294         (is_mve_encoding_conflict): Likewise.
1295         (is_mve_undefined): Likewise.
1296         (is_mve_unpredictable): Likewise.
1297         (print_mve_vmov_index): Likewise.
1298         (print_simd_imm8): Likewise.
1299         (print_mve_undefined): Likewise.
1300         (print_mve_unpredictable): Likewise.
1301         (print_mve_size): Likewise.
1302         (print_insn_mve): Likewise.
1303
1304 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1305             Michael Collison <michael.collison@arm.com>
1306
1307         * arm-dis.c (enum mve_instructions): Add new instructions.
1308         (enum mve_unpredictable): Add new reasons.
1309         (enum mve_undefined): Likewise.
1310         (is_mve_encoding_conflict): Handle new instructions.
1311         (is_mve_undefined): Likewise.
1312         (is_mve_unpredictable): Likewise.
1313         (print_mve_undefined): Likewise.
1314         (print_mve_unpredictable): Likewise.
1315         (print_mve_rounding_mode): Likewise.
1316         (print_mve_vcvt_size): Likewise.
1317         (print_mve_size): Likewise.
1318         (print_insn_mve): Likewise.
1319
1320 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1321             Michael Collison <michael.collison@arm.com>
1322
1323         * arm-dis.c (enum mve_instructions): Add new instructions.
1324         (enum mve_unpredictable): Add new reasons.
1325         (enum mve_undefined): Likewise.
1326         (is_mve_undefined): Handle new instructions.
1327         (is_mve_unpredictable): Likewise.
1328         (print_mve_undefined): Likewise.
1329         (print_mve_unpredictable): Likewise.
1330         (print_mve_size): Likewise.
1331         (print_insn_mve): Likewise.
1332
1333 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1334             Michael Collison <michael.collison@arm.com>
1335
1336         * arm-dis.c (enum mve_instructions): Add new instructions.
1337         (enum mve_undefined): Add new reasons.
1338         (insns): Add new instructions.
1339         (is_mve_encoding_conflict):
1340         (print_mve_vld_str_addr): New print function.
1341         (is_mve_undefined): Handle new instructions.
1342         (is_mve_unpredictable): Likewise.
1343         (print_mve_undefined): Likewise.
1344         (print_mve_size): Likewise.
1345         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1346         (print_insn_mve):  Handle new operands.
1347
1348 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1349             Michael Collison <michael.collison@arm.com>
1350
1351         * arm-dis.c (enum mve_instructions): Add new instructions.
1352         (enum mve_unpredictable): Add new reasons.
1353         (is_mve_encoding_conflict): Handle new instructions.
1354         (is_mve_unpredictable): Likewise.
1355         (mve_opcodes): Add new instructions.
1356         (print_mve_unpredictable): Handle new reasons.
1357         (print_mve_register_blocks): New print function.
1358         (print_mve_size): Handle new instructions.
1359         (print_insn_mve): Likewise.
1360
1361 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1362             Michael Collison <michael.collison@arm.com>
1363
1364         * arm-dis.c (enum mve_instructions): Add new instructions.
1365         (enum mve_unpredictable): Add new reasons.
1366         (enum mve_undefined): Likewise.
1367         (is_mve_encoding_conflict): Handle new instructions.
1368         (is_mve_undefined): Likewise.
1369         (is_mve_unpredictable): Likewise.
1370         (coprocessor_opcodes): Move NEON VDUP from here...
1371         (neon_opcodes): ... to here.
1372         (mve_opcodes): Add new instructions.
1373         (print_mve_undefined):  Handle new reasons.
1374         (print_mve_unpredictable): Likewise.
1375         (print_mve_size): Handle new instructions.
1376         (print_insn_neon): Handle vdup.
1377         (print_insn_mve): Handle new operands.
1378
1379 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1380             Michael Collison <michael.collison@arm.com>
1381
1382         * arm-dis.c (enum mve_instructions): Add new instructions.
1383         (enum mve_unpredictable): Add new values.
1384         (mve_opcodes): Add new instructions.
1385         (vec_condnames): New array with vector conditions.
1386         (mve_predicatenames): New array with predicate suffixes.
1387         (mve_vec_sizename): New array with vector sizes.
1388         (enum vpt_pred_state): New enum with vector predication states.
1389         (struct vpt_block): New struct type for vpt blocks.
1390         (vpt_block_state): Global struct to keep track of state.
1391         (mve_extract_pred_mask): New helper function.
1392         (num_instructions_vpt_block): Likewise.
1393         (mark_outside_vpt_block): Likewise.
1394         (mark_inside_vpt_block): Likewise.
1395         (invert_next_predicate_state): Likewise.
1396         (update_next_predicate_state): Likewise.
1397         (update_vpt_block_state): Likewise.
1398         (is_vpt_instruction): Likewise.
1399         (is_mve_encoding_conflict): Add entries for new instructions.
1400         (is_mve_unpredictable): Likewise.
1401         (print_mve_unpredictable): Handle new cases.
1402         (print_instruction_predicate): Likewise.
1403         (print_mve_size): New function.
1404         (print_vec_condition): New function.
1405         (print_insn_mve): Handle vpt blocks and new print operands.
1406
1407 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1408
1409         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1410         8, 14 and 15 for Armv8.1-M Mainline.
1411
1412 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1413             Michael Collison <michael.collison@arm.com>
1414
1415         * arm-dis.c (enum mve_instructions): New enum.
1416         (enum mve_unpredictable): Likewise.
1417         (enum mve_undefined): Likewise.
1418         (struct mopcode32): New struct.
1419         (is_mve_okay_in_it): New function.
1420         (is_mve_architecture): Likewise.
1421         (arm_decode_field): Likewise.
1422         (arm_decode_field_multiple): Likewise.
1423         (is_mve_encoding_conflict): Likewise.
1424         (is_mve_undefined): Likewise.
1425         (is_mve_unpredictable): Likewise.
1426         (print_mve_undefined): Likewise.
1427         (print_mve_unpredictable): Likewise.
1428         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1429         (print_insn_mve): New function.
1430         (print_insn_thumb32): Handle MVE architecture.
1431         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1432
1433 2019-05-10  Nick Clifton  <nickc@redhat.com>
1434
1435         PR 24538
1436         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1437         end of the table prematurely.
1438
1439 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1440
1441         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1442         macros for R6.
1443
1444 2019-05-11  Alan Modra  <amodra@gmail.com>
1445
1446         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1447         when -Mraw is in effect.
1448
1449 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1450
1451         * aarch64-dis-2.c: Regenerate.
1452         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1453         (OP_SVE_BBB): New variant set.
1454         (OP_SVE_DDDD): New variant set.
1455         (OP_SVE_HHH): New variant set.
1456         (OP_SVE_HHHU): New variant set.
1457         (OP_SVE_SSS): New variant set.
1458         (OP_SVE_SSSU): New variant set.
1459         (OP_SVE_SHH): New variant set.
1460         (OP_SVE_SBBU): New variant set.
1461         (OP_SVE_DSS): New variant set.
1462         (OP_SVE_DHHU): New variant set.
1463         (OP_SVE_VMV_HSD_BHS): New variant set.
1464         (OP_SVE_VVU_HSD_BHS): New variant set.
1465         (OP_SVE_VVVU_SD_BH): New variant set.
1466         (OP_SVE_VVVU_BHSD): New variant set.
1467         (OP_SVE_VVV_QHD_DBS): New variant set.
1468         (OP_SVE_VVV_HSD_BHS): New variant set.
1469         (OP_SVE_VVV_HSD_BHS2): New variant set.
1470         (OP_SVE_VVV_BHS_HSD): New variant set.
1471         (OP_SVE_VV_BHS_HSD): New variant set.
1472         (OP_SVE_VVV_SD): New variant set.
1473         (OP_SVE_VVU_BHS_HSD): New variant set.
1474         (OP_SVE_VZVV_SD): New variant set.
1475         (OP_SVE_VZVV_BH): New variant set.
1476         (OP_SVE_VZV_SD): New variant set.
1477         (aarch64_opcode_table): Add sve2 instructions.
1478
1479 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1480
1481         * aarch64-asm-2.c: Regenerated.
1482         * aarch64-dis-2.c: Regenerated.
1483         * aarch64-opc-2.c: Regenerated.
1484         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1485         for SVE_SHLIMM_UNPRED_22.
1486         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1487         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1488         operand.
1489
1490 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1491
1492         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1493         sve_size_tsz_bhs iclass encode.
1494         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1495         sve_size_tsz_bhs iclass decode.
1496
1497 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1498
1499         * aarch64-asm-2.c: Regenerated.
1500         * aarch64-dis-2.c: Regenerated.
1501         * aarch64-opc-2.c: Regenerated.
1502         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1503         for SVE_Zm4_11_INDEX.
1504         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1505         (fields): Handle SVE_i2h field.
1506         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1507         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1508
1509 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1510
1511         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1512         sve_shift_tsz_bhsd iclass encode.
1513         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1514         sve_shift_tsz_bhsd iclass decode.
1515
1516 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1517
1518         * aarch64-asm-2.c: Regenerated.
1519         * aarch64-dis-2.c: Regenerated.
1520         * aarch64-opc-2.c: Regenerated.
1521         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1522         (aarch64_encode_variant_using_iclass): Handle
1523         sve_shift_tsz_hsd iclass encode.
1524         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1525         sve_shift_tsz_hsd iclass decode.
1526         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1527         for SVE_SHRIMM_UNPRED_22.
1528         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1529         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1530         operand.
1531
1532 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1533
1534         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1535         sve_size_013 iclass encode.
1536         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1537         sve_size_013 iclass decode.
1538
1539 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1540
1541         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1542         sve_size_bh iclass encode.
1543         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1544         sve_size_bh iclass decode.
1545
1546 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1547
1548         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1549         sve_size_sd2 iclass encode.
1550         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1551         sve_size_sd2 iclass decode.
1552         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1553         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1554
1555 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1556
1557         * aarch64-asm-2.c: Regenerated.
1558         * aarch64-dis-2.c: Regenerated.
1559         * aarch64-opc-2.c: Regenerated.
1560         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1561         for SVE_ADDR_ZX.
1562         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1563         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1564
1565 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1566
1567         * aarch64-asm-2.c: Regenerated.
1568         * aarch64-dis-2.c: Regenerated.
1569         * aarch64-opc-2.c: Regenerated.
1570         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1571         for SVE_Zm3_11_INDEX.
1572         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1573         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1574         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1575         fields.
1576         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1577
1578 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1579
1580         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1581         sve_size_hsd2 iclass encode.
1582         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1583         sve_size_hsd2 iclass decode.
1584         * aarch64-opc.c (fields): Handle SVE_size field.
1585         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1586
1587 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1588
1589         * aarch64-asm-2.c: Regenerated.
1590         * aarch64-dis-2.c: Regenerated.
1591         * aarch64-opc-2.c: Regenerated.
1592         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1593         for SVE_IMM_ROT3.
1594         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1595         (fields): Handle SVE_rot3 field.
1596         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1597         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1598
1599 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1600
1601         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1602         instructions.
1603
1604 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1605
1606         * aarch64-tbl.h
1607         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1608         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1609         aarch64_feature_sve2bitperm): New feature sets.
1610         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1611         for feature set addresses.
1612         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1613         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1614
1615 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1616             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1617
1618         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1619         argument and set ASE_EVA_R6 appropriately.
1620         (set_default_mips_dis_options): Pass ISA to above.
1621         (parse_mips_dis_option): Likewise.
1622         * mips-opc.c (EVAR6): New macro.
1623         (mips_builtin_opcodes): Add llwpe, scwpe.
1624
1625 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1626
1627         * aarch64-asm-2.c: Regenerated.
1628         * aarch64-dis-2.c: Regenerated.
1629         * aarch64-opc-2.c: Regenerated.
1630         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1631         AARCH64_OPND_TME_UIMM16.
1632         (aarch64_print_operand): Likewise.
1633         * aarch64-tbl.h (QL_IMM_NIL): New.
1634         (TME): New.
1635         (_TME_INSN): New.
1636         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1637
1638 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1639
1640         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1641
1642 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1643             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1644
1645         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1646
1647 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1648
1649         * s12z-opc.h: Add extern "C" bracketing to help
1650         users who wish to use this interface in c++ code.
1651
1652 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1653
1654         * s12z-opc.c (bm_decode): Handle bit map operations with the
1655         "reserved0" mode.
1656
1657 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1658
1659         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1660         specifier.  Add entries for VLDR and VSTR of system registers.
1661         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1662         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1663         of %J and %K format specifier.
1664
1665 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1666
1667         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1668         Add new entries for VSCCLRM instruction.
1669         (print_insn_coprocessor): Handle new %C format control code.
1670
1671 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1672
1673         * arm-dis.c (enum isa): New enum.
1674         (struct sopcode32): New structure.
1675         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1676         set isa field of all current entries to ANY.
1677         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1678         Only match an entry if its isa field allows the current mode.
1679
1680 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1681
1682         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1683         CLRM.
1684         (print_insn_thumb32): Add logic to print %n CLRM register list.
1685
1686 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1687
1688         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1689         and %Q patterns.
1690
1691 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1692
1693         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1694         (print_insn_thumb32): Edit the switch case for %Z.
1695
1696 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1697
1698         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1699
1700 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1701
1702         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1703
1704 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1705
1706         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1707
1708 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1709
1710         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1711         Arm register with r13 and r15 unpredictable.
1712         (thumb32_opcodes): New instructions for bfx and bflx.
1713
1714 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1715
1716         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1717
1718 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1719
1720         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1721
1722 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1723
1724         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1725
1726 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1727
1728         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1729
1730 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1731
1732         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1733         "optr". ("operator" is a reserved word in c++).
1734
1735 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1736
1737         * aarch64-opc.c (aarch64_print_operand): Add case for
1738         AARCH64_OPND_Rt_SP.
1739         (verify_constraints): Likewise.
1740         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1741         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1742         to accept Rt|SP as first operand.
1743         (AARCH64_OPERANDS): Add new Rt_SP.
1744         * aarch64-asm-2.c: Regenerated.
1745         * aarch64-dis-2.c: Regenerated.
1746         * aarch64-opc-2.c: Regenerated.
1747
1748 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1749
1750         * aarch64-asm-2.c: Regenerated.
1751         * aarch64-dis-2.c: Likewise.
1752         * aarch64-opc-2.c: Likewise.
1753         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1754
1755 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1756
1757         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1758
1759 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1760
1761         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1762         * i386-init.h: Regenerated.
1763
1764 2019-04-07  Alan Modra  <amodra@gmail.com>
1765
1766         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1767         op_separator to control printing of spaces, comma and parens
1768         rather than need_comma, need_paren and spaces vars.
1769
1770 2019-04-07  Alan Modra  <amodra@gmail.com>
1771
1772         PR 24421
1773         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1774         (print_insn_neon, print_insn_arm): Likewise.
1775
1776 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1777
1778         * i386-dis-evex.h (evex_table): Updated to support BF16
1779         instructions.
1780         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1781         and EVEX_W_0F3872_P_3.
1782         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1783         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1784         * i386-opc.h (enum): Add CpuAVX512_BF16.
1785         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1786         * i386-opc.tbl: Add AVX512 BF16 instructions.
1787         * i386-init.h: Regenerated.
1788         * i386-tbl.h: Likewise.
1789
1790 2019-04-05  Alan Modra  <amodra@gmail.com>
1791
1792         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1793         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1794         to favour printing of "-" branch hint when using the "y" bit.
1795         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1796
1797 2019-04-05  Alan Modra  <amodra@gmail.com>
1798
1799         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1800         opcode until first operand is output.
1801
1802 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1803
1804         PR gas/24349
1805         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1806         (valid_bo_post_v2): Add support for 'at' branch hints.
1807         (insert_bo): Only error on branch on ctr.
1808         (get_bo_hint_mask): New function.
1809         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1810         for inserting 'at' branch hints.
1811         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1812         for extracting 'at' branch hints.
1813         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1814         (BOE): Delete operand.
1815         (BOM, BOP): New operands.
1816         (RM): Update value.
1817         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1818         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1819         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1820         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1821         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1822         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1823         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1824         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1825         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1826         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1827         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1828         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1829         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1830         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1831         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1832         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1833         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1834         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1835         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1836         bttarl+>: New extended mnemonics.
1837
1838 2019-03-28  Alan Modra  <amodra@gmail.com>
1839
1840         PR 24390
1841         * ppc-opc.c (BTF): Define.
1842         (powerpc_opcodes): Use for mtfsb*.
1843         * ppc-dis.c (print_insn_powerpc): Print fields with both
1844         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1845
1846 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1847
1848         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1849         (mapping_symbol_for_insn): Implement new algorithm.
1850         (print_insn): Remove duplicate code.
1851
1852 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1853
1854         * aarch64-dis.c (print_insn_aarch64):
1855         Implement override.
1856
1857 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1858
1859         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1860         order.
1861
1862 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1863
1864         * aarch64-dis.c (last_stop_offset): New.
1865         (print_insn_aarch64): Use stop_offset.
1866
1867 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1868
1869         PR gas/24359
1870         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1871         CPU_ANY_AVX2_FLAGS.
1872         * i386-init.h: Regenerated.
1873
1874 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1875
1876         PR gas/24348
1877         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1878         vmovdqu16, vmovdqu32 and vmovdqu64.
1879         * i386-tbl.h: Regenerated.
1880
1881 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1882
1883         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1884         from vstrszb, vstrszh, and vstrszf.
1885
1886 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1887
1888         * s390-opc.txt: Add instruction descriptions.
1889
1890 2019-02-08  Jim Wilson  <jimw@sifive.com>
1891
1892         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1893         <bne>: Likewise.
1894
1895 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1896
1897         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1898
1899 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1900
1901         PR binutils/23212
1902         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1903         * aarch64-opc.c (verify_elem_sd): New.
1904         (fields): Add FLD_sz entr.
1905         * aarch64-tbl.h (_SIMD_INSN): New.
1906         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1907         fmulx scalar and vector by element isns.
1908
1909 2019-02-07  Nick Clifton  <nickc@redhat.com>
1910
1911         * po/sv.po: Updated Swedish translation.
1912
1913 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1914
1915         * s390-mkopc.c (main): Accept arch13 as cpu string.
1916         * s390-opc.c: Add new instruction formats and instruction opcode
1917         masks.
1918         * s390-opc.txt: Add new arch13 instructions.
1919
1920 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1921
1922         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1923         (aarch64_opcode): Change encoding for stg, stzg
1924         st2g and st2zg.
1925         * aarch64-asm-2.c: Regenerated.
1926         * aarch64-dis-2.c: Regenerated.
1927         * aarch64-opc-2.c: Regenerated.
1928
1929 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1930
1931         * aarch64-asm-2.c: Regenerated.
1932         * aarch64-dis-2.c: Likewise.
1933         * aarch64-opc-2.c: Likewise.
1934         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1935
1936 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1937             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1938
1939         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1940         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1941         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1942         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1943         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1944         case for ldstgv_indexed.
1945         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1946         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1947         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1948         * aarch64-asm-2.c: Regenerated.
1949         * aarch64-dis-2.c: Regenerated.
1950         * aarch64-opc-2.c: Regenerated.
1951
1952 2019-01-23  Nick Clifton  <nickc@redhat.com>
1953
1954         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1955
1956 2019-01-21  Nick Clifton  <nickc@redhat.com>
1957
1958         * po/de.po: Updated German translation.
1959         * po/uk.po: Updated Ukranian translation.
1960
1961 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1962         * mips-dis.c (mips_arch_choices): Fix typo in
1963         gs464, gs464e and gs264e descriptors.
1964
1965 2019-01-19  Nick Clifton  <nickc@redhat.com>
1966
1967         * configure: Regenerate.
1968         * po/opcodes.pot: Regenerate.
1969
1970 2018-06-24  Nick Clifton  <nickc@redhat.com>
1971
1972         2.32 branch created.
1973
1974 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1975
1976         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1977         if it is null.
1978         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1979         zero.
1980
1981 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1982
1983         * configure: Regenerate.
1984
1985 2019-01-07  Alan Modra  <amodra@gmail.com>
1986
1987         * configure: Regenerate.
1988         * po/POTFILES.in: Regenerate.
1989
1990 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1991
1992         * s12z-opc.c: New file.
1993         * s12z-opc.h: New file.
1994         * s12z-dis.c: Removed all code not directly related to display
1995         of instructions.  Used the interface provided by the new files
1996         instead.
1997         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1998         * Makefile.in: Regenerate.
1999         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2000         * configure: Regenerate.
2001
2002 2019-01-01  Alan Modra  <amodra@gmail.com>
2003
2004         Update year range in copyright notice of all files.
2005
2006 For older changes see ChangeLog-2018
2007 \f
2008 Copyright (C) 2019 Free Software Foundation, Inc.
2009
2010 Copying and distribution of this file, with or without modification,
2011 are permitted in any medium without royalty provided the copyright
2012 notice and this notice are preserved.
2013
2014 Local Variables:
2015 mode: change-log
2016 left-margin: 8
2017 fill-column: 74
2018 version-control: never
2019 End: