1 2019-11-08 Jan Beulich <jbeulich@suse.com>
3 * i386-gen.c (operand_type_init): Add Class= to
4 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
6 (operand_classes): Add RegCR, RegDR, and RegTR entries.
7 (operand_types): Drop Control, Debug, and Test entries.
8 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
9 (Control, Debug, Test): Delete.
10 (union i386_operand_type): Remove control, debug, and test
12 * i386-opc.tbl (Control, Debug, Test): Define.
13 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
14 Class=RegDR, and Test by Class=RegTR.
15 * i386-init.h, i386-tbl.h: Re-generate.
17 2019-11-08 Jan Beulich <jbeulich@suse.com>
19 * i386-gen.c (operand_type_init): Add Class= to
20 OPERAND_TYPE_SREG entry.
21 (operand_classes): Add SReg entry.
22 (operand_types): Drop SReg entry.
23 * i386-opc.h (enum operand_class): Add SReg.
25 (union i386_operand_type): Remove sreg field.
26 * i386-opc.tbl (SReg): Define.
27 * i386-reg.tbl: Replace SReg by Class=SReg.
28 * i386-init.h, i386-tbl.h: Re-generate.
30 2019-11-08 Jan Beulich <jbeulich@suse.com>
32 * i386-gen.c (operand_type_init): Add Class=. New
33 OPERAND_TYPE_ANYIMM entry.
34 (operand_classes): New.
35 (operand_types): Drop Reg entry.
36 (output_operand_type): New parameter "class". Process it.
37 (process_i386_operand_type): New local variable "class".
38 (main): Adjust static assertions.
39 * i386-opc.h (CLASS_WIDTH): Define.
40 (enum operand_class): New.
41 (Reg): Replace by Class. Adjust comment.
42 (union i386_operand_type): Replace reg by class.
43 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
45 * i386-reg.tbl: Replace Reg by Class=Reg.
46 * i386-init.h: Re-generate.
48 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
50 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
51 (aarch64_opcode_table): Add data gathering hint mnemonic.
52 * opcodes/aarch64-dis-2.c: Account for new instruction.
54 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
56 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
59 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
61 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
62 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
63 aarch64_feature_f64mm): New feature sets.
64 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
65 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
67 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
69 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
70 (OP_SVE_QQQ): New qualifier.
71 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
72 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
73 the movprfx constraint.
74 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
75 (aarch64_opcode_table): Define new instructions smmla,
76 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
78 * aarch64-opc.c (operand_general_constraint_met_p): Handle
79 AARCH64_OPND_SVE_ADDR_RI_S4x32.
80 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
81 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
82 Account for new instructions.
83 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
85 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
87 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
88 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
90 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
92 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
93 (neon_opcodes): Add bfloat SIMD instructions.
94 (print_insn_coprocessor): Add new control character %b to print
95 condition code without checking cp_num.
96 (print_insn_neon): Account for BFloat16 instructions that have no
97 special top-byte handling.
99 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
100 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
102 * arm-dis.c (print_insn_coprocessor,
103 print_insn_generic_coprocessor): Create wrapper functions around
104 the implementation of the print_insn_coprocessor control codes.
105 (print_insn_coprocessor_1): Original print_insn_coprocessor
106 function that now takes which array to look at as an argument.
107 (print_insn_arm): Use both print_insn_coprocessor and
108 print_insn_generic_coprocessor.
109 (print_insn_thumb32): As above.
111 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
112 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
114 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
115 in reglane special case.
116 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
117 aarch64_find_next_opcode): Account for new instructions.
118 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
119 in reglane special case.
120 * aarch64-opc.c (struct operand_qualifier_data): Add data for
121 new AARCH64_OPND_QLF_S_2H qualifier.
122 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
123 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
124 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
126 (BFLOAT_SVE, BFLOAT): New feature set macros.
127 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
129 (aarch64_opcode_table): Define new instructions bfdot,
130 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
133 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
134 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
136 * aarch64-tbl.h (ARMV8_6): New macro.
138 2019-11-07 Jan Beulich <jbeulich@suse.com>
140 * i386-dis.c (prefix_table): Add mcommit.
141 (rm_table): Add rdpru.
142 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
143 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
144 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
145 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
146 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
147 * i386-opc.tbl (mcommit, rdpru): New.
148 * i386-init.h, i386-tbl.h: Re-generate.
150 2019-11-07 Jan Beulich <jbeulich@suse.com>
152 * i386-dis.c (OP_Mwait): Drop local variable "names", use
154 (OP_Monitor): Drop local variable "op1_names", re-purpose
155 "names" for it instead, and replace former "names" uses by
158 2019-11-07 Jan Beulich <jbeulich@suse.com>
161 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
163 * opcodes/i386-tbl.h: Re-generate.
165 2019-11-05 Jan Beulich <jbeulich@suse.com>
167 * i386-dis.c (OP_Mwaitx): Delete.
168 (prefix_table): Use OP_Mwait for mwaitx entry.
169 (OP_Mwait): Also handle mwaitx.
171 2019-11-05 Jan Beulich <jbeulich@suse.com>
173 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
174 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
175 (prefix_table): Add respective entries.
176 (rm_table): Link to those entries.
178 2019-11-05 Jan Beulich <jbeulich@suse.com>
180 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
181 (REG_0F1C_P_0_MOD_0): ... this.
182 (REG_0F1E_MOD_3): Rename to ...
183 (REG_0F1E_P_1_MOD_3): ... this.
184 (RM_0F01_REG_5): Rename to ...
185 (RM_0F01_REG_5_MOD_3): ... this.
186 (RM_0F01_REG_7): Rename to ...
187 (RM_0F01_REG_7_MOD_3): ... this.
188 (RM_0F1E_MOD_3_REG_7): Rename to ...
189 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
190 (RM_0FAE_REG_6): Rename to ...
191 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
192 (RM_0FAE_REG_7): Rename to ...
193 (RM_0FAE_REG_7_MOD_3): ... this.
194 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
195 (PREFIX_0F01_REG_5_MOD_0): ... this.
196 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
197 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
198 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
199 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
200 (PREFIX_0FAE_REG_0): Rename to ...
201 (PREFIX_0FAE_REG_0_MOD_3): ... this.
202 (PREFIX_0FAE_REG_1): Rename to ...
203 (PREFIX_0FAE_REG_1_MOD_3): ... this.
204 (PREFIX_0FAE_REG_2): Rename to ...
205 (PREFIX_0FAE_REG_2_MOD_3): ... this.
206 (PREFIX_0FAE_REG_3): Rename to ...
207 (PREFIX_0FAE_REG_3_MOD_3): ... this.
208 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
209 (PREFIX_0FAE_REG_4_MOD_0): ... this.
210 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
211 (PREFIX_0FAE_REG_4_MOD_3): ... this.
212 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
213 (PREFIX_0FAE_REG_5_MOD_0): ... this.
214 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
215 (PREFIX_0FAE_REG_5_MOD_3): ... this.
216 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
217 (PREFIX_0FAE_REG_6_MOD_0): ... this.
218 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
219 (PREFIX_0FAE_REG_6_MOD_3): ... this.
220 (PREFIX_0FAE_REG_7): Rename to ...
221 (PREFIX_0FAE_REG_7_MOD_0): ... this.
222 (PREFIX_MOD_0_0FC3): Rename to ...
223 (PREFIX_0FC3_MOD_0): ... this.
224 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
225 (PREFIX_0FC7_REG_6_MOD_0): ... this.
226 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
227 (PREFIX_0FC7_REG_6_MOD_3): ... this.
228 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
229 (PREFIX_0FC7_REG_7_MOD_3): ... this.
230 (reg_table, prefix_table, mod_table, rm_table): Adjust
233 2019-11-04 Nick Clifton <nickc@redhat.com>
235 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
236 of a v850 system register. Move the v850_sreg_names array into
238 (get_v850_reg_name): Likewise for ordinary register names.
239 (get_v850_vreg_name): Likewise for vector register names.
240 (get_v850_cc_name): Likewise for condition codes.
241 * get_v850_float_cc_name): Likewise for floating point condition
243 (get_v850_cacheop_name): Likewise for cache-ops.
244 (get_v850_prefop_name): Likewise for pref-ops.
245 (disassemble): Use the new accessor functions.
247 2019-10-30 Delia Burduv <delia.burduv@arm.com>
249 * aarch64-opc.c (print_immediate_offset_address): Don't print the
250 immediate for the writeback form of ldraa/ldrab if it is 0.
251 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
252 * aarch64-opc-2.c: Regenerated.
254 2019-10-30 Jan Beulich <jbeulich@suse.com>
256 * i386-gen.c (operand_type_shorthands): Delete.
257 (operand_type_init): Expand previous shorthands.
258 (set_bitfield_from_shorthand): Rename back to ...
259 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
260 of operand_type_init[].
261 (set_bitfield): Adjust call to the above function.
262 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
263 RegXMM, RegYMM, RegZMM): Define.
264 * i386-reg.tbl: Expand prior shorthands.
266 2019-10-30 Jan Beulich <jbeulich@suse.com>
268 * i386-gen.c (output_i386_opcode): Change order of fields
270 * i386-opc.h (struct insn_template): Move operands field.
271 Convert extension_opcode field to unsigned short.
272 * i386-tbl.h: Re-generate.
274 2019-10-30 Jan Beulich <jbeulich@suse.com>
276 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
278 * i386-opc.h (W): Extend comment.
279 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
280 general purpose variants not allowing for byte operands.
281 * i386-tbl.h: Re-generate.
283 2019-10-29 Nick Clifton <nickc@redhat.com>
285 * tic30-dis.c (print_branch): Correct size of operand array.
287 2019-10-29 Nick Clifton <nickc@redhat.com>
289 * d30v-dis.c (print_insn): Check that operand index is valid
290 before attempting to access the operands array.
292 2019-10-29 Nick Clifton <nickc@redhat.com>
294 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
295 locating the bit to be tested.
297 2019-10-29 Nick Clifton <nickc@redhat.com>
299 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
301 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
302 (print_insn_s12z): Check for illegal size values.
304 2019-10-28 Nick Clifton <nickc@redhat.com>
306 * csky-dis.c (csky_chars_to_number): Check for a negative
307 count. Use an unsigned integer to construct the return value.
309 2019-10-28 Nick Clifton <nickc@redhat.com>
311 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
312 operand buffer. Set value to 15 not 13.
313 (get_register_operand): Use OPERAND_BUFFER_LEN.
314 (get_indirect_operand): Likewise.
315 (print_two_operand): Likewise.
316 (print_three_operand): Likewise.
317 (print_oar_insn): Likewise.
319 2019-10-28 Nick Clifton <nickc@redhat.com>
321 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
322 (bit_extract_simple): Likewise.
323 (bit_copy): Likewise.
324 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
325 index_offset array are not accessed.
327 2019-10-28 Nick Clifton <nickc@redhat.com>
329 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
332 2019-10-25 Nick Clifton <nickc@redhat.com>
334 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
335 access to opcodes.op array element.
337 2019-10-23 Nick Clifton <nickc@redhat.com>
339 * rx-dis.c (get_register_name): Fix spelling typo in error
341 (get_condition_name, get_flag_name, get_double_register_name)
342 (get_double_register_high_name, get_double_register_low_name)
343 (get_double_control_register_name, get_double_condition_name)
344 (get_opsize_name, get_size_name): Likewise.
346 2019-10-22 Nick Clifton <nickc@redhat.com>
348 * rx-dis.c (get_size_name): New function. Provides safe
349 access to name array.
350 (get_opsize_name): Likewise.
351 (print_insn_rx): Use the accessor functions.
353 2019-10-16 Nick Clifton <nickc@redhat.com>
355 * rx-dis.c (get_register_name): New function. Provides safe
356 access to name array.
357 (get_condition_name, get_flag_name, get_double_register_name)
358 (get_double_register_high_name, get_double_register_low_name)
359 (get_double_control_register_name, get_double_condition_name):
361 (print_insn_rx): Use the accessor functions.
363 2019-10-09 Nick Clifton <nickc@redhat.com>
366 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
369 2019-10-07 Jan Beulich <jbeulich@suse.com>
371 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
372 (cmpsd): Likewise. Move EsSeg to other operand.
373 * opcodes/i386-tbl.h: Re-generate.
375 2019-09-23 Alan Modra <amodra@gmail.com>
377 * m68k-dis.c: Include cpu-m68k.h
379 2019-09-23 Alan Modra <amodra@gmail.com>
381 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
382 "elf/mips.h" earlier.
384 2018-09-20 Jan Beulich <jbeulich@suse.com>
387 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
389 * i386-tbl.h: Re-generate.
391 2019-09-18 Alan Modra <amodra@gmail.com>
393 * arc-ext.c: Update throughout for bfd section macro changes.
395 2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
397 * Makefile.in: Re-generate.
398 * configure: Re-generate.
400 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
402 * riscv-opc.c (riscv_opcodes): Change subset field
403 to insn_class field for all instructions.
404 (riscv_insn_types): Likewise.
406 2019-09-16 Phil Blundell <pb@pbcl.net>
408 * configure: Regenerated.
410 2019-09-10 Miod Vallat <miod@online.fr>
413 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
415 2019-09-09 Phil Blundell <pb@pbcl.net>
417 binutils 2.33 branch created.
419 2019-09-03 Nick Clifton <nickc@redhat.com>
422 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
423 greater than zero before indexing via (bufcnt -1).
425 2019-09-03 Nick Clifton <nickc@redhat.com>
428 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
429 (MAX_SPEC_REG_NAME_LEN): Define.
430 (struct mmix_dis_info): Use defined constants for array lengths.
431 (get_reg_name): New function.
432 (get_sprec_reg_name): New function.
433 (print_insn_mmix): Use new functions.
435 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
437 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
438 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
439 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
441 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
443 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
444 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
445 (aarch64_sys_reg_supported_p): Update checks for the above.
447 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
449 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
450 cases MVE_SQRSHRL and MVE_UQRSHLL.
451 (print_insn_mve): Add case for specifier 'k' to check
452 specific bit of the instruction.
454 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
457 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
458 encountering an unknown machine type.
459 (print_insn_arc): Handle arc_insn_length returning 0. In error
460 cases return -1 rather than calling abort.
462 2019-08-07 Jan Beulich <jbeulich@suse.com>
464 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
465 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
467 * i386-tbl.h: Re-generate.
469 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
471 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
474 2019-07-30 Mel Chen <mel.chen@sifive.com>
476 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
477 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
479 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
482 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
484 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
485 and MPY class instructions.
486 (parse_option): Add nps400 option.
487 (print_arc_disassembler_options): Add nps400 info.
489 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
491 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
494 * arc-opc.c (RAD_CHK): Add.
495 * arc-tbl.h: Regenerate.
497 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
499 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
500 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
502 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
504 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
505 instructions as UNPREDICTABLE.
507 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
509 * bpf-desc.c: Regenerated.
511 2019-07-17 Jan Beulich <jbeulich@suse.com>
513 * i386-gen.c (static_assert): Define.
515 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
516 (Opcode_Modifier_Num): ... this.
519 2019-07-16 Jan Beulich <jbeulich@suse.com>
521 * i386-gen.c (operand_types): Move RegMem ...
522 (opcode_modifiers): ... here.
523 * i386-opc.h (RegMem): Move to opcode modifer enum.
524 (union i386_operand_type): Move regmem field ...
525 (struct i386_opcode_modifier): ... here.
526 * i386-opc.tbl (RegMem): Define.
527 (mov, movq): Move RegMem on segment, control, debug, and test
529 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
530 to non-SSE2AVX flavor.
531 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
532 Move RegMem on register only flavors. Drop IgnoreSize from
533 legacy encoding flavors.
534 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
536 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
537 register only flavors.
538 (vmovd): Move RegMem and drop IgnoreSize on register only
539 flavor. Change opcode and operand order to store form.
540 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
542 2019-07-16 Jan Beulich <jbeulich@suse.com>
544 * i386-gen.c (operand_type_init, operand_types): Replace SReg
546 * i386-opc.h (SReg2, SReg3): Replace by ...
548 (union i386_operand_type): Replace sreg fields.
549 * i386-opc.tbl (mov, ): Use SReg.
550 (push, pop): Likewies. Drop i386 and x86-64 specific segment
552 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
553 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
555 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
557 * bpf-desc.c: Regenerate.
558 * bpf-opc.c: Likewise.
559 * bpf-opc.h: Likewise.
561 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
563 * bpf-desc.c: Regenerate.
564 * bpf-opc.c: Likewise.
566 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
568 * arm-dis.c (print_insn_coprocessor): Rename index to
571 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
573 * riscv-opc.c (riscv_insn_types): Add r4 type.
575 * riscv-opc.c (riscv_insn_types): Add b and j type.
577 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
578 format for sb type and correct s type.
580 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
582 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
583 SVE FMOV alias of FCPY.
585 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
587 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
588 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
590 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
592 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
593 registers in an instruction prefixed by MOVPRFX.
595 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
597 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
598 sve_size_13 icode to account for variant behaviour of
600 * aarch64-dis-2.c: Regenerate.
601 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
602 sve_size_13 icode to account for variant behaviour of
604 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
605 (OP_SVE_VVV_Q_D): Add new qualifier.
606 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
607 (struct aarch64_opcode): Split pmull{t,b} into those requiring
610 2019-07-01 Jan Beulich <jbeulich@suse.com>
612 * opcodes/i386-gen.c (operand_type_init): Remove
613 OPERAND_TYPE_VEC_IMM4 entry.
614 (operand_types): Remove Vec_Imm4.
615 * opcodes/i386-opc.h (Vec_Imm4): Delete.
616 (union i386_operand_type): Remove vec_imm4.
617 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
618 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
620 2019-07-01 Jan Beulich <jbeulich@suse.com>
622 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
623 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
624 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
625 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
626 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
627 monitorx, mwaitx): Drop ImmExt from operand-less forms.
628 * i386-tbl.h: Re-generate.
630 2019-07-01 Jan Beulich <jbeulich@suse.com>
632 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
634 * i386-tbl.h: Re-generate.
636 2019-07-01 Jan Beulich <jbeulich@suse.com>
638 * i386-opc.tbl (C): New.
639 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
640 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
641 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
642 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
643 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
644 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
645 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
646 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
647 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
648 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
649 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
650 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
651 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
652 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
653 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
654 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
655 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
656 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
657 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
658 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
659 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
660 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
661 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
662 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
663 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
664 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
666 * i386-tbl.h: Re-generate.
668 2019-07-01 Jan Beulich <jbeulich@suse.com>
670 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
672 * i386-tbl.h: Re-generate.
674 2019-07-01 Jan Beulich <jbeulich@suse.com>
676 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
677 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
678 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
679 * i386-tbl.h: Re-generate.
681 2019-07-01 Jan Beulich <jbeulich@suse.com>
683 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
684 Disp8MemShift from register only templates.
685 * i386-tbl.h: Re-generate.
687 2019-07-01 Jan Beulich <jbeulich@suse.com>
689 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
690 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
691 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
692 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
693 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
694 EVEX_W_0F11_P_3_M_1): Delete.
695 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
696 EVEX_W_0F11_P_3): New.
697 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
698 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
699 MOD_EVEX_0F11_PREFIX_3 table entries.
700 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
701 PREFIX_EVEX_0F11 table entries.
702 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
703 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
704 EVEX_W_0F11_P_3_M_{0,1} table entries.
706 2019-07-01 Jan Beulich <jbeulich@suse.com>
708 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
711 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
714 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
715 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
716 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
717 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
718 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
719 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
720 EVEX_LEN_0F38C7_R_6_P_2_W_1.
721 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
722 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
723 PREFIX_EVEX_0F38C6_REG_6 entries.
724 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
725 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
726 EVEX_W_0F38C7_R_6_P_2 entries.
727 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
728 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
729 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
730 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
731 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
732 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
733 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
735 2019-06-27 Jan Beulich <jbeulich@suse.com>
737 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
738 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
739 VEX_LEN_0F2D_P_3): Delete.
740 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
741 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
742 (prefix_table): ... here.
744 2019-06-27 Jan Beulich <jbeulich@suse.com>
746 * i386-dis.c (Iq): Delete.
748 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
750 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
751 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
752 (OP_E_memory): Also honor needindex when deciding whether an
753 address size prefix needs printing.
754 (OP_I): Remove handling of q_mode. Add handling of d_mode.
756 2019-06-26 Jim Wilson <jimw@sifive.com>
759 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
760 Set info->display_endian to info->endian_code.
762 2019-06-25 Jan Beulich <jbeulich@suse.com>
764 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
765 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
766 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
767 OPERAND_TYPE_ACC64 entries.
768 * i386-init.h: Re-generate.
770 2019-06-25 Jan Beulich <jbeulich@suse.com>
772 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
774 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
776 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
778 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
779 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
781 2019-06-25 Jan Beulich <jbeulich@suse.com>
783 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
786 2019-06-25 Jan Beulich <jbeulich@suse.com>
788 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
789 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
791 * i386-opc.tbl (movnti): Add IgnoreSize.
792 * i386-tbl.h: Re-generate.
794 2019-06-25 Jan Beulich <jbeulich@suse.com>
796 * i386-opc.tbl (and): Mark Imm8S form for optimization.
797 * i386-tbl.h: Re-generate.
799 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
801 * i386-dis-evex.h: Break into ...
802 * i386-dis-evex-len.h: New file.
803 * i386-dis-evex-mod.h: Likewise.
804 * i386-dis-evex-prefix.h: Likewise.
805 * i386-dis-evex-reg.h: Likewise.
806 * i386-dis-evex-w.h: Likewise.
807 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
808 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
811 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
814 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
815 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
817 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
818 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
819 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
820 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
821 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
822 EVEX_LEN_0F385B_P_2_W_1.
823 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
824 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
825 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
826 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
827 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
828 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
829 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
830 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
831 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
832 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
834 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
837 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
838 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
839 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
840 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
841 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
842 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
843 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
844 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
845 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
846 EVEX_LEN_0F3A43_P_2_W_1.
847 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
848 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
849 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
850 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
851 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
852 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
853 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
854 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
855 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
856 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
857 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
858 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
860 2019-06-14 Nick Clifton <nickc@redhat.com>
862 * po/fr.po; Updated French translation.
864 2019-06-13 Stafford Horne <shorne@gmail.com>
866 * or1k-asm.c: Regenerated.
867 * or1k-desc.c: Regenerated.
868 * or1k-desc.h: Regenerated.
869 * or1k-dis.c: Regenerated.
870 * or1k-ibld.c: Regenerated.
871 * or1k-opc.c: Regenerated.
872 * or1k-opc.h: Regenerated.
873 * or1k-opinst.c: Regenerated.
875 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
877 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
879 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
882 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
883 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
884 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
885 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
886 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
887 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
888 EVEX_LEN_0F3A1B_P_2_W_1.
889 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
890 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
891 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
892 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
893 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
894 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
895 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
896 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
898 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
901 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
902 EVEX.vvvv when disassembling VEX and EVEX instructions.
903 (OP_VEX): Set vex.register_specifier to 0 after readding
904 vex.register_specifier.
905 (OP_Vex_2src_1): Likewise.
906 (OP_Vex_2src_2): Likewise.
907 (OP_LWP_E): Likewise.
908 (OP_EX_Vex): Don't check vex.register_specifier.
909 (OP_XMM_Vex): Likewise.
911 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
912 Lili Cui <lili.cui@intel.com>
914 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
915 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
917 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
918 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
919 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
920 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
921 (i386_cpu_flags): Add cpuavx512_vp2intersect.
922 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
923 * i386-init.h: Regenerated.
924 * i386-tbl.h: Likewise.
926 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
927 Lili Cui <lili.cui@intel.com>
929 * doc/c-i386.texi: Document enqcmd.
930 * testsuite/gas/i386/enqcmd-intel.d: New file.
931 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
932 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
933 * testsuite/gas/i386/enqcmd.d: Likewise.
934 * testsuite/gas/i386/enqcmd.s: Likewise.
935 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
936 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
937 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
938 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
939 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
940 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
941 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
944 2019-06-04 Alan Hayward <alan.hayward@arm.com>
946 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
948 2019-06-03 Alan Modra <amodra@gmail.com>
950 * ppc-dis.c (prefix_opcd_indices): Correct size.
952 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
955 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
957 * i386-tbl.h: Regenerated.
959 2019-05-24 Alan Modra <amodra@gmail.com>
961 * po/POTFILES.in: Regenerate.
963 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
964 Alan Modra <amodra@gmail.com>
966 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
967 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
968 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
969 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
970 XTOP>): Define and add entries.
971 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
972 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
973 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
974 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
976 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
977 Alan Modra <amodra@gmail.com>
979 * ppc-dis.c (ppc_opts): Add "future" entry.
980 (PREFIX_OPCD_SEGS): Define.
981 (prefix_opcd_indices): New array.
982 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
983 (lookup_prefix): New function.
984 (print_insn_powerpc): Handle 64-bit prefix instructions.
985 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
986 (PMRR, POWERXX): Define.
987 (prefix_opcodes): New instruction table.
988 (prefix_num_opcodes): New constant.
990 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
992 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
993 * configure: Regenerated.
994 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
996 (HFILES): Add bpf-desc.h and bpf-opc.h.
997 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
998 bpf-ibld.c and bpf-opc.c.
1000 * Makefile.in: Regenerated.
1001 * disassemble.c (ARCH_bpf): Define.
1002 (disassembler): Add case for bfd_arch_bpf.
1003 (disassemble_init_for_target): Likewise.
1004 (enum epbf_isa_attr): Define.
1005 * disassemble.h: extern print_insn_bpf.
1006 * bpf-asm.c: Generated.
1007 * bpf-opc.h: Likewise.
1008 * bpf-opc.c: Likewise.
1009 * bpf-ibld.c: Likewise.
1010 * bpf-dis.c: Likewise.
1011 * bpf-desc.h: Likewise.
1012 * bpf-desc.c: Likewise.
1014 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1016 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1017 and VMSR with the new operands.
1019 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1021 * arm-dis.c (enum mve_instructions): New enum
1022 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1024 (mve_opcodes): New instructions as above.
1025 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1027 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1029 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1031 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1032 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1033 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1034 uqshl, urshrl and urshr.
1035 (is_mve_okay_in_it): Add new instructions to TRUE list.
1036 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1037 (print_insn_mve): Updated to accept new %j,
1038 %<bitfield>m and %<bitfield>n patterns.
1040 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1042 * mips-opc.c (mips_builtin_opcodes): Change source register
1043 constraint for DAUI.
1045 2019-05-20 Nick Clifton <nickc@redhat.com>
1047 * po/fr.po: Updated French translation.
1049 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1050 Michael Collison <michael.collison@arm.com>
1052 * arm-dis.c (thumb32_opcodes): Add new instructions.
1053 (enum mve_instructions): Likewise.
1054 (enum mve_undefined): Add new reasons.
1055 (is_mve_encoding_conflict): Handle new instructions.
1056 (is_mve_undefined): Likewise.
1057 (is_mve_unpredictable): Likewise.
1058 (print_mve_undefined): Likewise.
1059 (print_mve_size): Likewise.
1061 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1062 Michael Collison <michael.collison@arm.com>
1064 * arm-dis.c (thumb32_opcodes): Add new instructions.
1065 (enum mve_instructions): Likewise.
1066 (is_mve_encoding_conflict): Handle new instructions.
1067 (is_mve_undefined): Likewise.
1068 (is_mve_unpredictable): Likewise.
1069 (print_mve_size): Likewise.
1071 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1072 Michael Collison <michael.collison@arm.com>
1074 * arm-dis.c (thumb32_opcodes): Add new instructions.
1075 (enum mve_instructions): Likewise.
1076 (is_mve_encoding_conflict): Likewise.
1077 (is_mve_unpredictable): Likewise.
1078 (print_mve_size): Likewise.
1080 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1081 Michael Collison <michael.collison@arm.com>
1083 * arm-dis.c (thumb32_opcodes): Add new instructions.
1084 (enum mve_instructions): Likewise.
1085 (is_mve_encoding_conflict): Handle new instructions.
1086 (is_mve_undefined): Likewise.
1087 (is_mve_unpredictable): Likewise.
1088 (print_mve_size): Likewise.
1090 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1091 Michael Collison <michael.collison@arm.com>
1093 * arm-dis.c (thumb32_opcodes): Add new instructions.
1094 (enum mve_instructions): Likewise.
1095 (is_mve_encoding_conflict): Handle new instructions.
1096 (is_mve_undefined): Likewise.
1097 (is_mve_unpredictable): Likewise.
1098 (print_mve_size): Likewise.
1099 (print_insn_mve): Likewise.
1101 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1102 Michael Collison <michael.collison@arm.com>
1104 * arm-dis.c (thumb32_opcodes): Add new instructions.
1105 (print_insn_thumb32): Handle new instructions.
1107 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1108 Michael Collison <michael.collison@arm.com>
1110 * arm-dis.c (enum mve_instructions): Add new instructions.
1111 (enum mve_undefined): Add new reasons.
1112 (is_mve_encoding_conflict): Handle new instructions.
1113 (is_mve_undefined): Likewise.
1114 (is_mve_unpredictable): Likewise.
1115 (print_mve_undefined): Likewise.
1116 (print_mve_size): Likewise.
1117 (print_mve_shift_n): Likewise.
1118 (print_insn_mve): Likewise.
1120 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1121 Michael Collison <michael.collison@arm.com>
1123 * arm-dis.c (enum mve_instructions): Add new instructions.
1124 (is_mve_encoding_conflict): Handle new instructions.
1125 (is_mve_unpredictable): Likewise.
1126 (print_mve_rotate): Likewise.
1127 (print_mve_size): Likewise.
1128 (print_insn_mve): Likewise.
1130 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1131 Michael Collison <michael.collison@arm.com>
1133 * arm-dis.c (enum mve_instructions): Add new instructions.
1134 (is_mve_encoding_conflict): Handle new instructions.
1135 (is_mve_unpredictable): Likewise.
1136 (print_mve_size): Likewise.
1137 (print_insn_mve): Likewise.
1139 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1140 Michael Collison <michael.collison@arm.com>
1142 * arm-dis.c (enum mve_instructions): Add new instructions.
1143 (enum mve_undefined): Add new reasons.
1144 (is_mve_encoding_conflict): Handle new instructions.
1145 (is_mve_undefined): Likewise.
1146 (is_mve_unpredictable): Likewise.
1147 (print_mve_undefined): Likewise.
1148 (print_mve_size): Likewise.
1149 (print_insn_mve): Likewise.
1151 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1152 Michael Collison <michael.collison@arm.com>
1154 * arm-dis.c (enum mve_instructions): Add new instructions.
1155 (is_mve_encoding_conflict): Handle new instructions.
1156 (is_mve_undefined): Likewise.
1157 (is_mve_unpredictable): Likewise.
1158 (print_mve_size): Likewise.
1159 (print_insn_mve): Likewise.
1161 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1162 Michael Collison <michael.collison@arm.com>
1164 * arm-dis.c (enum mve_instructions): Add new instructions.
1165 (enum mve_unpredictable): Add new reasons.
1166 (enum mve_undefined): Likewise.
1167 (is_mve_okay_in_it): Handle new isntructions.
1168 (is_mve_encoding_conflict): Likewise.
1169 (is_mve_undefined): Likewise.
1170 (is_mve_unpredictable): Likewise.
1171 (print_mve_vmov_index): Likewise.
1172 (print_simd_imm8): Likewise.
1173 (print_mve_undefined): Likewise.
1174 (print_mve_unpredictable): Likewise.
1175 (print_mve_size): Likewise.
1176 (print_insn_mve): Likewise.
1178 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1179 Michael Collison <michael.collison@arm.com>
1181 * arm-dis.c (enum mve_instructions): Add new instructions.
1182 (enum mve_unpredictable): Add new reasons.
1183 (enum mve_undefined): Likewise.
1184 (is_mve_encoding_conflict): Handle new instructions.
1185 (is_mve_undefined): Likewise.
1186 (is_mve_unpredictable): Likewise.
1187 (print_mve_undefined): Likewise.
1188 (print_mve_unpredictable): Likewise.
1189 (print_mve_rounding_mode): Likewise.
1190 (print_mve_vcvt_size): Likewise.
1191 (print_mve_size): Likewise.
1192 (print_insn_mve): Likewise.
1194 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1195 Michael Collison <michael.collison@arm.com>
1197 * arm-dis.c (enum mve_instructions): Add new instructions.
1198 (enum mve_unpredictable): Add new reasons.
1199 (enum mve_undefined): Likewise.
1200 (is_mve_undefined): Handle new instructions.
1201 (is_mve_unpredictable): Likewise.
1202 (print_mve_undefined): Likewise.
1203 (print_mve_unpredictable): Likewise.
1204 (print_mve_size): Likewise.
1205 (print_insn_mve): Likewise.
1207 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1208 Michael Collison <michael.collison@arm.com>
1210 * arm-dis.c (enum mve_instructions): Add new instructions.
1211 (enum mve_undefined): Add new reasons.
1212 (insns): Add new instructions.
1213 (is_mve_encoding_conflict):
1214 (print_mve_vld_str_addr): New print function.
1215 (is_mve_undefined): Handle new instructions.
1216 (is_mve_unpredictable): Likewise.
1217 (print_mve_undefined): Likewise.
1218 (print_mve_size): Likewise.
1219 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1220 (print_insn_mve): Handle new operands.
1222 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1223 Michael Collison <michael.collison@arm.com>
1225 * arm-dis.c (enum mve_instructions): Add new instructions.
1226 (enum mve_unpredictable): Add new reasons.
1227 (is_mve_encoding_conflict): Handle new instructions.
1228 (is_mve_unpredictable): Likewise.
1229 (mve_opcodes): Add new instructions.
1230 (print_mve_unpredictable): Handle new reasons.
1231 (print_mve_register_blocks): New print function.
1232 (print_mve_size): Handle new instructions.
1233 (print_insn_mve): Likewise.
1235 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1236 Michael Collison <michael.collison@arm.com>
1238 * arm-dis.c (enum mve_instructions): Add new instructions.
1239 (enum mve_unpredictable): Add new reasons.
1240 (enum mve_undefined): Likewise.
1241 (is_mve_encoding_conflict): Handle new instructions.
1242 (is_mve_undefined): Likewise.
1243 (is_mve_unpredictable): Likewise.
1244 (coprocessor_opcodes): Move NEON VDUP from here...
1245 (neon_opcodes): ... to here.
1246 (mve_opcodes): Add new instructions.
1247 (print_mve_undefined): Handle new reasons.
1248 (print_mve_unpredictable): Likewise.
1249 (print_mve_size): Handle new instructions.
1250 (print_insn_neon): Handle vdup.
1251 (print_insn_mve): Handle new operands.
1253 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1254 Michael Collison <michael.collison@arm.com>
1256 * arm-dis.c (enum mve_instructions): Add new instructions.
1257 (enum mve_unpredictable): Add new values.
1258 (mve_opcodes): Add new instructions.
1259 (vec_condnames): New array with vector conditions.
1260 (mve_predicatenames): New array with predicate suffixes.
1261 (mve_vec_sizename): New array with vector sizes.
1262 (enum vpt_pred_state): New enum with vector predication states.
1263 (struct vpt_block): New struct type for vpt blocks.
1264 (vpt_block_state): Global struct to keep track of state.
1265 (mve_extract_pred_mask): New helper function.
1266 (num_instructions_vpt_block): Likewise.
1267 (mark_outside_vpt_block): Likewise.
1268 (mark_inside_vpt_block): Likewise.
1269 (invert_next_predicate_state): Likewise.
1270 (update_next_predicate_state): Likewise.
1271 (update_vpt_block_state): Likewise.
1272 (is_vpt_instruction): Likewise.
1273 (is_mve_encoding_conflict): Add entries for new instructions.
1274 (is_mve_unpredictable): Likewise.
1275 (print_mve_unpredictable): Handle new cases.
1276 (print_instruction_predicate): Likewise.
1277 (print_mve_size): New function.
1278 (print_vec_condition): New function.
1279 (print_insn_mve): Handle vpt blocks and new print operands.
1281 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1283 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1284 8, 14 and 15 for Armv8.1-M Mainline.
1286 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1287 Michael Collison <michael.collison@arm.com>
1289 * arm-dis.c (enum mve_instructions): New enum.
1290 (enum mve_unpredictable): Likewise.
1291 (enum mve_undefined): Likewise.
1292 (struct mopcode32): New struct.
1293 (is_mve_okay_in_it): New function.
1294 (is_mve_architecture): Likewise.
1295 (arm_decode_field): Likewise.
1296 (arm_decode_field_multiple): Likewise.
1297 (is_mve_encoding_conflict): Likewise.
1298 (is_mve_undefined): Likewise.
1299 (is_mve_unpredictable): Likewise.
1300 (print_mve_undefined): Likewise.
1301 (print_mve_unpredictable): Likewise.
1302 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1303 (print_insn_mve): New function.
1304 (print_insn_thumb32): Handle MVE architecture.
1305 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1307 2019-05-10 Nick Clifton <nickc@redhat.com>
1310 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1311 end of the table prematurely.
1313 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1315 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1318 2019-05-11 Alan Modra <amodra@gmail.com>
1320 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1321 when -Mraw is in effect.
1323 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1325 * aarch64-dis-2.c: Regenerate.
1326 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1327 (OP_SVE_BBB): New variant set.
1328 (OP_SVE_DDDD): New variant set.
1329 (OP_SVE_HHH): New variant set.
1330 (OP_SVE_HHHU): New variant set.
1331 (OP_SVE_SSS): New variant set.
1332 (OP_SVE_SSSU): New variant set.
1333 (OP_SVE_SHH): New variant set.
1334 (OP_SVE_SBBU): New variant set.
1335 (OP_SVE_DSS): New variant set.
1336 (OP_SVE_DHHU): New variant set.
1337 (OP_SVE_VMV_HSD_BHS): New variant set.
1338 (OP_SVE_VVU_HSD_BHS): New variant set.
1339 (OP_SVE_VVVU_SD_BH): New variant set.
1340 (OP_SVE_VVVU_BHSD): New variant set.
1341 (OP_SVE_VVV_QHD_DBS): New variant set.
1342 (OP_SVE_VVV_HSD_BHS): New variant set.
1343 (OP_SVE_VVV_HSD_BHS2): New variant set.
1344 (OP_SVE_VVV_BHS_HSD): New variant set.
1345 (OP_SVE_VV_BHS_HSD): New variant set.
1346 (OP_SVE_VVV_SD): New variant set.
1347 (OP_SVE_VVU_BHS_HSD): New variant set.
1348 (OP_SVE_VZVV_SD): New variant set.
1349 (OP_SVE_VZVV_BH): New variant set.
1350 (OP_SVE_VZV_SD): New variant set.
1351 (aarch64_opcode_table): Add sve2 instructions.
1353 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1355 * aarch64-asm-2.c: Regenerated.
1356 * aarch64-dis-2.c: Regenerated.
1357 * aarch64-opc-2.c: Regenerated.
1358 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1359 for SVE_SHLIMM_UNPRED_22.
1360 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1361 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1364 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1366 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1367 sve_size_tsz_bhs iclass encode.
1368 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1369 sve_size_tsz_bhs iclass decode.
1371 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1373 * aarch64-asm-2.c: Regenerated.
1374 * aarch64-dis-2.c: Regenerated.
1375 * aarch64-opc-2.c: Regenerated.
1376 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1377 for SVE_Zm4_11_INDEX.
1378 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1379 (fields): Handle SVE_i2h field.
1380 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1381 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1383 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1385 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1386 sve_shift_tsz_bhsd iclass encode.
1387 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1388 sve_shift_tsz_bhsd iclass decode.
1390 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1392 * aarch64-asm-2.c: Regenerated.
1393 * aarch64-dis-2.c: Regenerated.
1394 * aarch64-opc-2.c: Regenerated.
1395 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1396 (aarch64_encode_variant_using_iclass): Handle
1397 sve_shift_tsz_hsd iclass encode.
1398 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1399 sve_shift_tsz_hsd iclass decode.
1400 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1401 for SVE_SHRIMM_UNPRED_22.
1402 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1403 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1406 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1408 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1409 sve_size_013 iclass encode.
1410 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1411 sve_size_013 iclass decode.
1413 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1415 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1416 sve_size_bh iclass encode.
1417 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1418 sve_size_bh iclass decode.
1420 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1422 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1423 sve_size_sd2 iclass encode.
1424 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1425 sve_size_sd2 iclass decode.
1426 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1427 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1429 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1431 * aarch64-asm-2.c: Regenerated.
1432 * aarch64-dis-2.c: Regenerated.
1433 * aarch64-opc-2.c: Regenerated.
1434 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1436 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1437 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1439 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1441 * aarch64-asm-2.c: Regenerated.
1442 * aarch64-dis-2.c: Regenerated.
1443 * aarch64-opc-2.c: Regenerated.
1444 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1445 for SVE_Zm3_11_INDEX.
1446 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1447 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1448 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1450 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1452 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1454 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1455 sve_size_hsd2 iclass encode.
1456 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1457 sve_size_hsd2 iclass decode.
1458 * aarch64-opc.c (fields): Handle SVE_size field.
1459 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1461 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1463 * aarch64-asm-2.c: Regenerated.
1464 * aarch64-dis-2.c: Regenerated.
1465 * aarch64-opc-2.c: Regenerated.
1466 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1468 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1469 (fields): Handle SVE_rot3 field.
1470 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1471 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1473 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1475 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1478 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1481 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1482 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1483 aarch64_feature_sve2bitperm): New feature sets.
1484 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1485 for feature set addresses.
1486 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1487 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1489 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1490 Faraz Shahbazker <fshahbazker@wavecomp.com>
1492 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1493 argument and set ASE_EVA_R6 appropriately.
1494 (set_default_mips_dis_options): Pass ISA to above.
1495 (parse_mips_dis_option): Likewise.
1496 * mips-opc.c (EVAR6): New macro.
1497 (mips_builtin_opcodes): Add llwpe, scwpe.
1499 2019-05-01 Sudakshina Das <sudi.das@arm.com>
1501 * aarch64-asm-2.c: Regenerated.
1502 * aarch64-dis-2.c: Regenerated.
1503 * aarch64-opc-2.c: Regenerated.
1504 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1505 AARCH64_OPND_TME_UIMM16.
1506 (aarch64_print_operand): Likewise.
1507 * aarch64-tbl.h (QL_IMM_NIL): New.
1510 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1512 2019-04-29 John Darrington <john@darrington.wattle.id.au>
1514 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1516 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1517 Faraz Shahbazker <fshahbazker@wavecomp.com>
1519 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1521 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1523 * s12z-opc.h: Add extern "C" bracketing to help
1524 users who wish to use this interface in c++ code.
1526 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1528 * s12z-opc.c (bm_decode): Handle bit map operations with the
1531 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1533 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1534 specifier. Add entries for VLDR and VSTR of system registers.
1535 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1536 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1537 of %J and %K format specifier.
1539 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1541 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1542 Add new entries for VSCCLRM instruction.
1543 (print_insn_coprocessor): Handle new %C format control code.
1545 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1547 * arm-dis.c (enum isa): New enum.
1548 (struct sopcode32): New structure.
1549 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1550 set isa field of all current entries to ANY.
1551 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1552 Only match an entry if its isa field allows the current mode.
1554 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1556 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1558 (print_insn_thumb32): Add logic to print %n CLRM register list.
1560 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1562 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1565 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1567 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1568 (print_insn_thumb32): Edit the switch case for %Z.
1570 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1572 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1574 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1576 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1578 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1580 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1582 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1584 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1585 Arm register with r13 and r15 unpredictable.
1586 (thumb32_opcodes): New instructions for bfx and bflx.
1588 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1590 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1592 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1594 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1596 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1598 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1600 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1602 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1604 2019-04-12 John Darrington <john@darrington.wattle.id.au>
1606 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1607 "optr". ("operator" is a reserved word in c++).
1609 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1611 * aarch64-opc.c (aarch64_print_operand): Add case for
1613 (verify_constraints): Likewise.
1614 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1615 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1616 to accept Rt|SP as first operand.
1617 (AARCH64_OPERANDS): Add new Rt_SP.
1618 * aarch64-asm-2.c: Regenerated.
1619 * aarch64-dis-2.c: Regenerated.
1620 * aarch64-opc-2.c: Regenerated.
1622 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1624 * aarch64-asm-2.c: Regenerated.
1625 * aarch64-dis-2.c: Likewise.
1626 * aarch64-opc-2.c: Likewise.
1627 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1629 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1631 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1633 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1635 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1636 * i386-init.h: Regenerated.
1638 2019-04-07 Alan Modra <amodra@gmail.com>
1640 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1641 op_separator to control printing of spaces, comma and parens
1642 rather than need_comma, need_paren and spaces vars.
1644 2019-04-07 Alan Modra <amodra@gmail.com>
1647 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1648 (print_insn_neon, print_insn_arm): Likewise.
1650 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1652 * i386-dis-evex.h (evex_table): Updated to support BF16
1654 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1655 and EVEX_W_0F3872_P_3.
1656 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1657 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1658 * i386-opc.h (enum): Add CpuAVX512_BF16.
1659 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1660 * i386-opc.tbl: Add AVX512 BF16 instructions.
1661 * i386-init.h: Regenerated.
1662 * i386-tbl.h: Likewise.
1664 2019-04-05 Alan Modra <amodra@gmail.com>
1666 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1667 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1668 to favour printing of "-" branch hint when using the "y" bit.
1669 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1671 2019-04-05 Alan Modra <amodra@gmail.com>
1673 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1674 opcode until first operand is output.
1676 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1679 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1680 (valid_bo_post_v2): Add support for 'at' branch hints.
1681 (insert_bo): Only error on branch on ctr.
1682 (get_bo_hint_mask): New function.
1683 (insert_boe): Add new 'branch_taken' formal argument. Add support
1684 for inserting 'at' branch hints.
1685 (extract_boe): Add new 'branch_taken' formal argument. Add support
1686 for extracting 'at' branch hints.
1687 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1688 (BOE): Delete operand.
1689 (BOM, BOP): New operands.
1691 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1692 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1693 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1694 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1695 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1696 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1697 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1698 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1699 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1700 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1701 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1702 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1703 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1704 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1705 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1706 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1707 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1708 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1709 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1710 bttarl+>: New extended mnemonics.
1712 2019-03-28 Alan Modra <amodra@gmail.com>
1715 * ppc-opc.c (BTF): Define.
1716 (powerpc_opcodes): Use for mtfsb*.
1717 * ppc-dis.c (print_insn_powerpc): Print fields with both
1718 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1720 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1722 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1723 (mapping_symbol_for_insn): Implement new algorithm.
1724 (print_insn): Remove duplicate code.
1726 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1728 * aarch64-dis.c (print_insn_aarch64):
1731 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1733 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1736 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1738 * aarch64-dis.c (last_stop_offset): New.
1739 (print_insn_aarch64): Use stop_offset.
1741 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1744 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1746 * i386-init.h: Regenerated.
1748 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1751 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1752 vmovdqu16, vmovdqu32 and vmovdqu64.
1753 * i386-tbl.h: Regenerated.
1755 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1757 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1758 from vstrszb, vstrszh, and vstrszf.
1760 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1762 * s390-opc.txt: Add instruction descriptions.
1764 2019-02-08 Jim Wilson <jimw@sifive.com>
1766 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1769 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1771 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1773 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1776 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1777 * aarch64-opc.c (verify_elem_sd): New.
1778 (fields): Add FLD_sz entr.
1779 * aarch64-tbl.h (_SIMD_INSN): New.
1780 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1781 fmulx scalar and vector by element isns.
1783 2019-02-07 Nick Clifton <nickc@redhat.com>
1785 * po/sv.po: Updated Swedish translation.
1787 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1789 * s390-mkopc.c (main): Accept arch13 as cpu string.
1790 * s390-opc.c: Add new instruction formats and instruction opcode
1792 * s390-opc.txt: Add new arch13 instructions.
1794 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1796 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1797 (aarch64_opcode): Change encoding for stg, stzg
1799 * aarch64-asm-2.c: Regenerated.
1800 * aarch64-dis-2.c: Regenerated.
1801 * aarch64-opc-2.c: Regenerated.
1803 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1805 * aarch64-asm-2.c: Regenerated.
1806 * aarch64-dis-2.c: Likewise.
1807 * aarch64-opc-2.c: Likewise.
1808 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1810 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1811 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1813 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1814 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1815 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1816 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1817 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1818 case for ldstgv_indexed.
1819 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1820 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1821 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1822 * aarch64-asm-2.c: Regenerated.
1823 * aarch64-dis-2.c: Regenerated.
1824 * aarch64-opc-2.c: Regenerated.
1826 2019-01-23 Nick Clifton <nickc@redhat.com>
1828 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1830 2019-01-21 Nick Clifton <nickc@redhat.com>
1832 * po/de.po: Updated German translation.
1833 * po/uk.po: Updated Ukranian translation.
1835 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1836 * mips-dis.c (mips_arch_choices): Fix typo in
1837 gs464, gs464e and gs264e descriptors.
1839 2019-01-19 Nick Clifton <nickc@redhat.com>
1841 * configure: Regenerate.
1842 * po/opcodes.pot: Regenerate.
1844 2018-06-24 Nick Clifton <nickc@redhat.com>
1846 2.32 branch created.
1848 2019-01-09 John Darrington <john@darrington.wattle.id.au>
1850 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1852 -dis.c (opr_emit_disassembly): Do not omit an index if it is
1855 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1857 * configure: Regenerate.
1859 2019-01-07 Alan Modra <amodra@gmail.com>
1861 * configure: Regenerate.
1862 * po/POTFILES.in: Regenerate.
1864 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1866 * s12z-opc.c: New file.
1867 * s12z-opc.h: New file.
1868 * s12z-dis.c: Removed all code not directly related to display
1869 of instructions. Used the interface provided by the new files
1871 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1872 * Makefile.in: Regenerate.
1873 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1874 * configure: Regenerate.
1876 2019-01-01 Alan Modra <amodra@gmail.com>
1878 Update year range in copyright notice of all files.
1880 For older changes see ChangeLog-2018
1882 Copyright (C) 2019 Free Software Foundation, Inc.
1884 Copying and distribution of this file, with or without modification,
1885 are permitted in any medium without royalty provided the copyright
1886 notice and this notice are preserved.
1892 version-control: never