1 2020-03-06 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
4 * i386-tbl.h: Re-generate.
6 2020-03-06 Jan Beulich <jbeulich@suse.com>
8 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
9 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
10 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
11 VexW0 on SSE2AVX variants.
12 (vmovq): Drop NoRex64 from XMM/XMM variants.
13 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
14 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
16 * i386-tbl.h: Re-generate.
18 2020-03-06 Jan Beulich <jbeulich@suse.com>
20 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
21 * i386-opc.h (Rex64): Delete.
22 (struct i386_opcode_modifier): Remove rex64 field.
23 * i386-opc.tbl (crc32): Drop Rex64.
24 Replace Rex64 with Size64 everywhere else.
25 * i386-tbl.h: Re-generate.
27 2020-03-06 Jan Beulich <jbeulich@suse.com>
29 * i386-dis.c (OP_E_memory): Exclude recording of used address
30 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
31 addressed memory operands for MPX insns.
33 2020-03-06 Jan Beulich <jbeulich@suse.com>
35 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
36 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
37 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
38 (ptwrite): Split into non-64-bit and 64-bit forms.
39 * i386-tbl.h: Re-generate.
41 2020-03-06 Jan Beulich <jbeulich@suse.com>
43 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
45 * i386-tbl.h: Re-generate.
47 2020-03-04 Jan Beulich <jbeulich@suse.com>
49 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
50 (prefix_table): Move vmmcall here. Add vmgexit.
51 (rm_table): Replace vmmcall entry by prefix_table[] escape.
52 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
53 (cpu_flags): Add CpuSEV_ES entry.
54 * i386-opc.h (CpuSEV_ES): New.
55 (union i386_cpu_flags): Add cpusev_es field.
56 * i386-opc.tbl (vmgexit): New.
57 * i386-init.h, i386-tbl.h: Re-generate.
59 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
61 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
63 * i386-opc.h (IGNORESIZE): New.
64 (DEFAULTSIZE): Likewise.
65 (IgnoreSize): Removed.
66 (DefaultSize): Likewise.
68 (i386_opcode_modifier): Replace ignoresize/defaultsize with
70 * i386-opc.tbl (IgnoreSize): New.
71 (DefaultSize): Likewise.
72 * i386-tbl.h: Regenerated.
74 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
77 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
80 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
83 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
84 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
85 * i386-tbl.h: Regenerated.
87 2020-02-26 Alan Modra <amodra@gmail.com>
89 * aarch64-asm.c: Indent labels correctly.
90 * aarch64-dis.c: Likewise.
91 * aarch64-gen.c: Likewise.
92 * aarch64-opc.c: Likewise.
93 * alpha-dis.c: Likewise.
94 * i386-dis.c: Likewise.
95 * nds32-asm.c: Likewise.
96 * nfp-dis.c: Likewise.
97 * visium-dis.c: Likewise.
99 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
101 * arc-regs.h (int_vector_base): Make it available for all ARC
104 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
106 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
109 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
111 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
112 c.mv/c.li if rs1 is zero.
114 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
116 * i386-gen.c (cpu_flag_init): Replace CpuABM with
117 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
119 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
120 * i386-opc.h (CpuABM): Removed.
122 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
123 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
124 popcnt. Remove CpuABM from lzcnt.
125 * i386-init.h: Regenerated.
126 * i386-tbl.h: Likewise.
128 2020-02-17 Jan Beulich <jbeulich@suse.com>
130 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
131 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
132 VexW1 instead of open-coding them.
133 * i386-tbl.h: Re-generate.
135 2020-02-17 Jan Beulich <jbeulich@suse.com>
137 * i386-opc.tbl (AddrPrefixOpReg): Define.
138 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
139 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
140 templates. Drop NoRex64.
141 * i386-tbl.h: Re-generate.
143 2020-02-17 Jan Beulich <jbeulich@suse.com>
146 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
147 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
148 into Intel syntax instance (with Unpsecified) and AT&T one
150 (vcvtneps2bf16): Likewise, along with folding the two so far
152 * i386-tbl.h: Re-generate.
154 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
156 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
159 2020-02-17 Alan Modra <amodra@gmail.com>
161 * i386-gen.c (cpu_flag_init): Correct last change.
163 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
165 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
168 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
170 * i386-opc.tbl (movsx): Remove Intel syntax comments.
173 2020-02-14 Jan Beulich <jbeulich@suse.com>
176 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
177 destination for Cpu64-only variant.
178 (movzx): Fold patterns.
179 * i386-tbl.h: Re-generate.
181 2020-02-13 Jan Beulich <jbeulich@suse.com>
183 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
184 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
185 CPU_ANY_SSE4_FLAGS entry.
186 * i386-init.h: Re-generate.
188 2020-02-12 Jan Beulich <jbeulich@suse.com>
190 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
191 with Unspecified, making the present one AT&T syntax only.
192 * i386-tbl.h: Re-generate.
194 2020-02-12 Jan Beulich <jbeulich@suse.com>
196 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
197 * i386-tbl.h: Re-generate.
199 2020-02-12 Jan Beulich <jbeulich@suse.com>
202 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
203 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
204 Amd64 and Intel64 templates.
205 (call, jmp): Likewise for far indirect variants. Dro
207 * i386-tbl.h: Re-generate.
209 2020-02-11 Jan Beulich <jbeulich@suse.com>
211 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
212 * i386-opc.h (ShortForm): Delete.
213 (struct i386_opcode_modifier): Remove shortform field.
214 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
215 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
216 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
217 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
219 * i386-tbl.h: Re-generate.
221 2020-02-11 Jan Beulich <jbeulich@suse.com>
223 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
224 fucompi): Drop ShortForm from operand-less templates.
225 * i386-tbl.h: Re-generate.
227 2020-02-11 Alan Modra <amodra@gmail.com>
229 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
230 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
231 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
232 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
233 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
235 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
237 * arm-dis.c (print_insn_cde): Define 'V' parse character.
238 (cde_opcodes): Add VCX* instructions.
240 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
241 Matthew Malcomson <matthew.malcomson@arm.com>
243 * arm-dis.c (struct cdeopcode32): New.
244 (CDE_OPCODE): New macro.
245 (cde_opcodes): New disassembly table.
246 (regnames): New option to table.
247 (cde_coprocs): New global variable.
248 (print_insn_cde): New
249 (print_insn_thumb32): Use print_insn_cde.
250 (parse_arm_disassembler_options): Parse coprocN args.
252 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
255 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
257 * i386-opc.h (AMD64): Removed.
261 (INTEL64ONLY): Likewise.
262 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
263 * i386-opc.tbl (Amd64): New.
265 (Intel64Only): Likewise.
266 Replace AMD64 with Amd64. Update sysenter/sysenter with
267 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
268 * i386-tbl.h: Regenerated.
270 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
273 * z80-dis.c: Add support for GBZ80 opcodes.
275 2020-02-04 Alan Modra <amodra@gmail.com>
277 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
279 2020-02-03 Alan Modra <amodra@gmail.com>
281 * m32c-ibld.c: Regenerate.
283 2020-02-01 Alan Modra <amodra@gmail.com>
285 * frv-ibld.c: Regenerate.
287 2020-01-31 Jan Beulich <jbeulich@suse.com>
289 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
290 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
291 (OP_E_memory): Replace xmm_mdq_mode case label by
292 vex_scalar_w_dq_mode one.
293 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
295 2020-01-31 Jan Beulich <jbeulich@suse.com>
297 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
298 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
299 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
300 (intel_operand_size): Drop vex_w_dq_mode case label.
302 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
304 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
305 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
307 2020-01-30 Alan Modra <amodra@gmail.com>
309 * m32c-ibld.c: Regenerate.
311 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
313 * bpf-opc.c: Regenerate.
315 2020-01-30 Jan Beulich <jbeulich@suse.com>
317 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
318 (dis386): Use them to replace C2/C3 table entries.
319 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
320 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
321 ones. Use Size64 instead of DefaultSize on Intel64 ones.
322 * i386-tbl.h: Re-generate.
324 2020-01-30 Jan Beulich <jbeulich@suse.com>
326 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
328 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
330 * i386-tbl.h: Re-generate.
332 2020-01-30 Alan Modra <amodra@gmail.com>
334 * tic4x-dis.c (tic4x_dp): Make unsigned.
336 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
337 Jan Beulich <jbeulich@suse.com>
340 * i386-dis.c (MOVSXD_Fixup): New function.
341 (movsxd_mode): New enum.
342 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
343 (intel_operand_size): Handle movsxd_mode.
344 (OP_E_register): Likewise.
346 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
347 register on movsxd. Add movsxd with 16-bit destination register
348 for AMD64 and Intel64 ISAs.
349 * i386-tbl.h: Regenerated.
351 2020-01-27 Tamar Christina <tamar.christina@arm.com>
354 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
355 * aarch64-asm-2.c: Regenerate
356 * aarch64-dis-2.c: Likewise.
357 * aarch64-opc-2.c: Likewise.
359 2020-01-21 Jan Beulich <jbeulich@suse.com>
361 * i386-opc.tbl (sysret): Drop DefaultSize.
362 * i386-tbl.h: Re-generate.
364 2020-01-21 Jan Beulich <jbeulich@suse.com>
366 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
368 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
369 * i386-tbl.h: Re-generate.
371 2020-01-20 Nick Clifton <nickc@redhat.com>
373 * po/de.po: Updated German translation.
374 * po/pt_BR.po: Updated Brazilian Portuguese translation.
375 * po/uk.po: Updated Ukranian translation.
377 2020-01-20 Alan Modra <amodra@gmail.com>
379 * hppa-dis.c (fput_const): Remove useless cast.
381 2020-01-20 Alan Modra <amodra@gmail.com>
383 * arm-dis.c (print_insn_arm): Wrap 'T' value.
385 2020-01-18 Nick Clifton <nickc@redhat.com>
387 * configure: Regenerate.
388 * po/opcodes.pot: Regenerate.
390 2020-01-18 Nick Clifton <nickc@redhat.com>
392 Binutils 2.34 branch created.
394 2020-01-17 Christian Biesinger <cbiesinger@google.com>
396 * opintl.h: Fix spelling error (seperate).
398 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
400 * i386-opc.tbl: Add {vex} pseudo prefix.
401 * i386-tbl.h: Regenerated.
403 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
406 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
407 (neon_opcodes): Likewise.
408 (select_arm_features): Make sure we enable MVE bits when selecting
409 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
412 2020-01-16 Jan Beulich <jbeulich@suse.com>
414 * i386-opc.tbl: Drop stale comment from XOP section.
416 2020-01-16 Jan Beulich <jbeulich@suse.com>
418 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
419 (extractps): Add VexWIG to SSE2AVX forms.
420 * i386-tbl.h: Re-generate.
422 2020-01-16 Jan Beulich <jbeulich@suse.com>
424 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
425 Size64 from and use VexW1 on SSE2AVX forms.
426 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
427 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
428 * i386-tbl.h: Re-generate.
430 2020-01-15 Alan Modra <amodra@gmail.com>
432 * tic4x-dis.c (tic4x_version): Make unsigned long.
433 (optab, optab_special, registernames): New file scope vars.
434 (tic4x_print_register): Set up registernames rather than
435 malloc'd registertable.
436 (tic4x_disassemble): Delete optable and optable_special. Use
437 optab and optab_special instead. Throw away old optab,
438 optab_special and registernames when info->mach changes.
440 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
443 * z80-dis.c (suffix): Use .db instruction to generate double
446 2020-01-14 Alan Modra <amodra@gmail.com>
448 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
449 values to unsigned before shifting.
451 2020-01-13 Thomas Troeger <tstroege@gmx.de>
453 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
455 (print_insn_thumb16, print_insn_thumb32): Likewise.
456 (print_insn): Initialize the insn info.
457 * i386-dis.c (print_insn): Initialize the insn info fields, and
460 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
462 * arc-opc.c (C_NE): Make it required.
464 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
466 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
467 reserved register name.
469 2020-01-13 Alan Modra <amodra@gmail.com>
471 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
472 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
474 2020-01-13 Alan Modra <amodra@gmail.com>
476 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
477 result of wasm_read_leb128 in a uint64_t and check that bits
478 are not lost when copying to other locals. Use uint32_t for
479 most locals. Use PRId64 when printing int64_t.
481 2020-01-13 Alan Modra <amodra@gmail.com>
483 * score-dis.c: Formatting.
484 * score7-dis.c: Formatting.
486 2020-01-13 Alan Modra <amodra@gmail.com>
488 * score-dis.c (print_insn_score48): Use unsigned variables for
489 unsigned values. Don't left shift negative values.
490 (print_insn_score32): Likewise.
491 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
493 2020-01-13 Alan Modra <amodra@gmail.com>
495 * tic4x-dis.c (tic4x_print_register): Remove dead code.
497 2020-01-13 Alan Modra <amodra@gmail.com>
499 * fr30-ibld.c: Regenerate.
501 2020-01-13 Alan Modra <amodra@gmail.com>
503 * xgate-dis.c (print_insn): Don't left shift signed value.
504 (ripBits): Formatting, use 1u.
506 2020-01-10 Alan Modra <amodra@gmail.com>
508 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
509 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
511 2020-01-10 Alan Modra <amodra@gmail.com>
513 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
514 and XRREG value earlier to avoid a shift with negative exponent.
515 * m10200-dis.c (disassemble): Similarly.
517 2020-01-09 Nick Clifton <nickc@redhat.com>
520 * z80-dis.c (ld_ii_ii): Use correct cast.
522 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
525 * z80-dis.c (ld_ii_ii): Use character constant when checking
528 2020-01-09 Jan Beulich <jbeulich@suse.com>
530 * i386-dis.c (SEP_Fixup): New.
532 (dis386_twobyte): Use it for sysenter/sysexit.
533 (enum x86_64_isa): Change amd64 enumerator to value 1.
534 (OP_J): Compare isa64 against intel64 instead of amd64.
535 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
537 * i386-tbl.h: Re-generate.
539 2020-01-08 Alan Modra <amodra@gmail.com>
541 * z8k-dis.c: Include libiberty.h
542 (instr_data_s): Make max_fetched unsigned.
543 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
544 Don't exceed byte_info bounds.
545 (output_instr): Make num_bytes unsigned.
546 (unpack_instr): Likewise for nibl_count and loop.
547 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
549 * z8k-opc.h: Regenerate.
551 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
553 * arc-tbl.h (llock): Use 'LLOCK' as class.
555 (scond): Use 'SCOND' as class.
557 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
560 2020-01-06 Alan Modra <amodra@gmail.com>
562 * m32c-ibld.c: Regenerate.
564 2020-01-06 Alan Modra <amodra@gmail.com>
567 * z80-dis.c (suffix): Don't use a local struct buffer copy.
568 Peek at next byte to prevent recursion on repeated prefix bytes.
569 Ensure uninitialised "mybuf" is not accessed.
570 (print_insn_z80): Don't zero n_fetch and n_used here,..
571 (print_insn_z80_buf): ..do it here instead.
573 2020-01-04 Alan Modra <amodra@gmail.com>
575 * m32r-ibld.c: Regenerate.
577 2020-01-04 Alan Modra <amodra@gmail.com>
579 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
581 2020-01-04 Alan Modra <amodra@gmail.com>
583 * crx-dis.c (match_opcode): Avoid shift left of signed value.
585 2020-01-04 Alan Modra <amodra@gmail.com>
587 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
589 2020-01-03 Jan Beulich <jbeulich@suse.com>
591 * aarch64-tbl.h (aarch64_opcode_table): Use
592 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
594 2020-01-03 Jan Beulich <jbeulich@suse.com>
596 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
597 forms of SUDOT and USDOT.
599 2020-01-03 Jan Beulich <jbeulich@suse.com>
601 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
603 * opcodes/aarch64-dis-2.c: Re-generate.
605 2020-01-03 Jan Beulich <jbeulich@suse.com>
607 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
609 * opcodes/aarch64-dis-2.c: Re-generate.
611 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
613 * z80-dis.c: Add support for eZ80 and Z80 instructions.
615 2020-01-01 Alan Modra <amodra@gmail.com>
617 Update year range in copyright notice of all files.
619 For older changes see ChangeLog-2019
621 Copyright (C) 2020 Free Software Foundation, Inc.
623 Copying and distribution of this file, with or without modification,
624 are permitted in any medium without royalty provided the copyright
625 notice and this notice are preserved.
631 version-control: never