1 2020-02-11 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
4 fucompi): Drop ShortForm from operand-less templates.
5 * i386-tbl.h: Re-generate.
7 2020-02-11 Alan Modra <amodra@gmail.com>
9 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
10 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
11 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
12 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
13 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
15 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
17 * arm-dis.c (print_insn_cde): Define 'V' parse character.
18 (cde_opcodes): Add VCX* instructions.
20 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
21 Matthew Malcomson <matthew.malcomson@arm.com>
23 * arm-dis.c (struct cdeopcode32): New.
24 (CDE_OPCODE): New macro.
25 (cde_opcodes): New disassembly table.
26 (regnames): New option to table.
27 (cde_coprocs): New global variable.
29 (print_insn_thumb32): Use print_insn_cde.
30 (parse_arm_disassembler_options): Parse coprocN args.
32 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
35 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
37 * i386-opc.h (AMD64): Removed.
41 (INTEL64ONLY): Likewise.
42 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
43 * i386-opc.tbl (Amd64): New.
45 (Intel64Only): Likewise.
46 Replace AMD64 with Amd64. Update sysenter/sysenter with
47 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
48 * i386-tbl.h: Regenerated.
50 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
53 * z80-dis.c: Add support for GBZ80 opcodes.
55 2020-02-04 Alan Modra <amodra@gmail.com>
57 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
59 2020-02-03 Alan Modra <amodra@gmail.com>
61 * m32c-ibld.c: Regenerate.
63 2020-02-01 Alan Modra <amodra@gmail.com>
65 * frv-ibld.c: Regenerate.
67 2020-01-31 Jan Beulich <jbeulich@suse.com>
69 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
70 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
71 (OP_E_memory): Replace xmm_mdq_mode case label by
72 vex_scalar_w_dq_mode one.
73 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
75 2020-01-31 Jan Beulich <jbeulich@suse.com>
77 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
78 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
79 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
80 (intel_operand_size): Drop vex_w_dq_mode case label.
82 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
84 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
85 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
87 2020-01-30 Alan Modra <amodra@gmail.com>
89 * m32c-ibld.c: Regenerate.
91 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
93 * bpf-opc.c: Regenerate.
95 2020-01-30 Jan Beulich <jbeulich@suse.com>
97 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
98 (dis386): Use them to replace C2/C3 table entries.
99 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
100 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
101 ones. Use Size64 instead of DefaultSize on Intel64 ones.
102 * i386-tbl.h: Re-generate.
104 2020-01-30 Jan Beulich <jbeulich@suse.com>
106 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
108 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
110 * i386-tbl.h: Re-generate.
112 2020-01-30 Alan Modra <amodra@gmail.com>
114 * tic4x-dis.c (tic4x_dp): Make unsigned.
116 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
117 Jan Beulich <jbeulich@suse.com>
120 * i386-dis.c (MOVSXD_Fixup): New function.
121 (movsxd_mode): New enum.
122 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
123 (intel_operand_size): Handle movsxd_mode.
124 (OP_E_register): Likewise.
126 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
127 register on movsxd. Add movsxd with 16-bit destination register
128 for AMD64 and Intel64 ISAs.
129 * i386-tbl.h: Regenerated.
131 2020-01-27 Tamar Christina <tamar.christina@arm.com>
134 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
135 * aarch64-asm-2.c: Regenerate
136 * aarch64-dis-2.c: Likewise.
137 * aarch64-opc-2.c: Likewise.
139 2020-01-21 Jan Beulich <jbeulich@suse.com>
141 * i386-opc.tbl (sysret): Drop DefaultSize.
142 * i386-tbl.h: Re-generate.
144 2020-01-21 Jan Beulich <jbeulich@suse.com>
146 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
148 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
149 * i386-tbl.h: Re-generate.
151 2020-01-20 Nick Clifton <nickc@redhat.com>
153 * po/de.po: Updated German translation.
154 * po/pt_BR.po: Updated Brazilian Portuguese translation.
155 * po/uk.po: Updated Ukranian translation.
157 2020-01-20 Alan Modra <amodra@gmail.com>
159 * hppa-dis.c (fput_const): Remove useless cast.
161 2020-01-20 Alan Modra <amodra@gmail.com>
163 * arm-dis.c (print_insn_arm): Wrap 'T' value.
165 2020-01-18 Nick Clifton <nickc@redhat.com>
167 * configure: Regenerate.
168 * po/opcodes.pot: Regenerate.
170 2020-01-18 Nick Clifton <nickc@redhat.com>
172 Binutils 2.34 branch created.
174 2020-01-17 Christian Biesinger <cbiesinger@google.com>
176 * opintl.h: Fix spelling error (seperate).
178 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
180 * i386-opc.tbl: Add {vex} pseudo prefix.
181 * i386-tbl.h: Regenerated.
183 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
186 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
187 (neon_opcodes): Likewise.
188 (select_arm_features): Make sure we enable MVE bits when selecting
189 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
192 2020-01-16 Jan Beulich <jbeulich@suse.com>
194 * i386-opc.tbl: Drop stale comment from XOP section.
196 2020-01-16 Jan Beulich <jbeulich@suse.com>
198 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
199 (extractps): Add VexWIG to SSE2AVX forms.
200 * i386-tbl.h: Re-generate.
202 2020-01-16 Jan Beulich <jbeulich@suse.com>
204 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
205 Size64 from and use VexW1 on SSE2AVX forms.
206 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
207 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
208 * i386-tbl.h: Re-generate.
210 2020-01-15 Alan Modra <amodra@gmail.com>
212 * tic4x-dis.c (tic4x_version): Make unsigned long.
213 (optab, optab_special, registernames): New file scope vars.
214 (tic4x_print_register): Set up registernames rather than
215 malloc'd registertable.
216 (tic4x_disassemble): Delete optable and optable_special. Use
217 optab and optab_special instead. Throw away old optab,
218 optab_special and registernames when info->mach changes.
220 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
223 * z80-dis.c (suffix): Use .db instruction to generate double
226 2020-01-14 Alan Modra <amodra@gmail.com>
228 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
229 values to unsigned before shifting.
231 2020-01-13 Thomas Troeger <tstroege@gmx.de>
233 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
235 (print_insn_thumb16, print_insn_thumb32): Likewise.
236 (print_insn): Initialize the insn info.
237 * i386-dis.c (print_insn): Initialize the insn info fields, and
240 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
242 * arc-opc.c (C_NE): Make it required.
244 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
246 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
247 reserved register name.
249 2020-01-13 Alan Modra <amodra@gmail.com>
251 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
252 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
254 2020-01-13 Alan Modra <amodra@gmail.com>
256 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
257 result of wasm_read_leb128 in a uint64_t and check that bits
258 are not lost when copying to other locals. Use uint32_t for
259 most locals. Use PRId64 when printing int64_t.
261 2020-01-13 Alan Modra <amodra@gmail.com>
263 * score-dis.c: Formatting.
264 * score7-dis.c: Formatting.
266 2020-01-13 Alan Modra <amodra@gmail.com>
268 * score-dis.c (print_insn_score48): Use unsigned variables for
269 unsigned values. Don't left shift negative values.
270 (print_insn_score32): Likewise.
271 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
273 2020-01-13 Alan Modra <amodra@gmail.com>
275 * tic4x-dis.c (tic4x_print_register): Remove dead code.
277 2020-01-13 Alan Modra <amodra@gmail.com>
279 * fr30-ibld.c: Regenerate.
281 2020-01-13 Alan Modra <amodra@gmail.com>
283 * xgate-dis.c (print_insn): Don't left shift signed value.
284 (ripBits): Formatting, use 1u.
286 2020-01-10 Alan Modra <amodra@gmail.com>
288 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
289 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
291 2020-01-10 Alan Modra <amodra@gmail.com>
293 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
294 and XRREG value earlier to avoid a shift with negative exponent.
295 * m10200-dis.c (disassemble): Similarly.
297 2020-01-09 Nick Clifton <nickc@redhat.com>
300 * z80-dis.c (ld_ii_ii): Use correct cast.
302 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
305 * z80-dis.c (ld_ii_ii): Use character constant when checking
308 2020-01-09 Jan Beulich <jbeulich@suse.com>
310 * i386-dis.c (SEP_Fixup): New.
312 (dis386_twobyte): Use it for sysenter/sysexit.
313 (enum x86_64_isa): Change amd64 enumerator to value 1.
314 (OP_J): Compare isa64 against intel64 instead of amd64.
315 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
317 * i386-tbl.h: Re-generate.
319 2020-01-08 Alan Modra <amodra@gmail.com>
321 * z8k-dis.c: Include libiberty.h
322 (instr_data_s): Make max_fetched unsigned.
323 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
324 Don't exceed byte_info bounds.
325 (output_instr): Make num_bytes unsigned.
326 (unpack_instr): Likewise for nibl_count and loop.
327 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
329 * z8k-opc.h: Regenerate.
331 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
333 * arc-tbl.h (llock): Use 'LLOCK' as class.
335 (scond): Use 'SCOND' as class.
337 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
340 2020-01-06 Alan Modra <amodra@gmail.com>
342 * m32c-ibld.c: Regenerate.
344 2020-01-06 Alan Modra <amodra@gmail.com>
347 * z80-dis.c (suffix): Don't use a local struct buffer copy.
348 Peek at next byte to prevent recursion on repeated prefix bytes.
349 Ensure uninitialised "mybuf" is not accessed.
350 (print_insn_z80): Don't zero n_fetch and n_used here,..
351 (print_insn_z80_buf): ..do it here instead.
353 2020-01-04 Alan Modra <amodra@gmail.com>
355 * m32r-ibld.c: Regenerate.
357 2020-01-04 Alan Modra <amodra@gmail.com>
359 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
361 2020-01-04 Alan Modra <amodra@gmail.com>
363 * crx-dis.c (match_opcode): Avoid shift left of signed value.
365 2020-01-04 Alan Modra <amodra@gmail.com>
367 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
369 2020-01-03 Jan Beulich <jbeulich@suse.com>
371 * aarch64-tbl.h (aarch64_opcode_table): Use
372 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
374 2020-01-03 Jan Beulich <jbeulich@suse.com>
376 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
377 forms of SUDOT and USDOT.
379 2020-01-03 Jan Beulich <jbeulich@suse.com>
381 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
383 * opcodes/aarch64-dis-2.c: Re-generate.
385 2020-01-03 Jan Beulich <jbeulich@suse.com>
387 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
389 * opcodes/aarch64-dis-2.c: Re-generate.
391 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
393 * z80-dis.c: Add support for eZ80 and Z80 instructions.
395 2020-01-01 Alan Modra <amodra@gmail.com>
397 Update year range in copyright notice of all files.
399 For older changes see ChangeLog-2019
401 Copyright (C) 2020 Free Software Foundation, Inc.
403 Copying and distribution of this file, with or without modification,
404 are permitted in any medium without royalty provided the copyright
405 notice and this notice are preserved.
411 version-control: never