opcodes/ChangeLog

   1 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
   4         CPU_ANY_SSE4_FLAGS.
   5
   6 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
   7
   8         * i386-opc.tbl (movsx): Remove Intel syntax comments.
   9         (movzx): Likewise.
  10
  11 2020-02-14  Jan Beulich  <jbeulich@suse.com>
  12
  13         PR gas/25438
  14         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
  15         destination for Cpu64-only variant.
  16         (movzx): Fold patterns.
  17         * i386-tbl.h: Re-generate.
  18
  19 2020-02-13  Jan Beulich  <jbeulich@suse.com>
  20
  21         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
  22         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
  23         CPU_ANY_SSE4_FLAGS entry.
  24         * i386-init.h: Re-generate.
  25
  26 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  27
  28         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
  29         with Unspecified, making the present one AT&T syntax only.
  30         * i386-tbl.h: Re-generate.
  31
  32 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  33
  34         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
  35         * i386-tbl.h: Re-generate.
  36
  37 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  38
  39         PR gas/24546
  40         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
  41         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
  42         Amd64 and Intel64 templates.
  43         (call, jmp): Likewise for far indirect variants. Dro
  44         Unspecified.
  45         * i386-tbl.h: Re-generate.
  46
  47 2020-02-11  Jan Beulich  <jbeulich@suse.com>
  48
  49         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
  50         * i386-opc.h (ShortForm): Delete.
  51         (struct i386_opcode_modifier): Remove shortform field.
  52         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
  53         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
  54         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
  55         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
  56         Drop ShortForm.
  57         * i386-tbl.h: Re-generate.
  58
  59 2020-02-11  Jan Beulich  <jbeulich@suse.com>
  60
  61         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
  62         fucompi): Drop ShortForm from operand-less templates.
  63         * i386-tbl.h: Re-generate.
  64
  65 2020-02-11  Alan Modra  <amodra@gmail.com>
  66
  67         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
  68         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
  69         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
  70         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
  71         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
  72
  73 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
  74
  75         * arm-dis.c (print_insn_cde): Define 'V' parse character.
  76         (cde_opcodes): Add VCX* instructions.
  77
  78 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
  79             Matthew Malcomson  <matthew.malcomson@arm.com>
  80
  81         * arm-dis.c (struct cdeopcode32): New.
  82         (CDE_OPCODE): New macro.
  83         (cde_opcodes): New disassembly table.
  84         (regnames): New option to table.
  85         (cde_coprocs): New global variable.
  86         (print_insn_cde): New
  87         (print_insn_thumb32): Use print_insn_cde.
  88         (parse_arm_disassembler_options): Parse coprocN args.
  89
  90 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
  91
  92         PR gas/25516
  93         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
  94         with ISA64.
  95         * i386-opc.h (AMD64): Removed.
  96         (Intel64): Likewose.
  97         (AMD64): New.
  98         (INTEL64): Likewise.
  99         (INTEL64ONLY): Likewise.
 100         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 101         * i386-opc.tbl (Amd64): New.
 102         (Intel64): Likewise.
 103         (Intel64Only): Likewise.
 104         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 105         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 106         * i386-tbl.h: Regenerated.
 107
 108 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 109
 110         PR 25469
 111         * z80-dis.c: Add support for GBZ80 opcodes.
 112
 113 2020-02-04  Alan Modra  <amodra@gmail.com>
 114
 115         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 116
 117 2020-02-03  Alan Modra  <amodra@gmail.com>
 118
 119         * m32c-ibld.c: Regenerate.
 120
 121 2020-02-01  Alan Modra  <amodra@gmail.com>
 122
 123         * frv-ibld.c: Regenerate.
 124
 125 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 126
 127         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 128         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 129         (OP_E_memory): Replace xmm_mdq_mode case label by
 130         vex_scalar_w_dq_mode one.
 131         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 132
 133 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 134
 135         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 136         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 137         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 138         (intel_operand_size): Drop vex_w_dq_mode case label.
 139
 140 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 141
 142         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 143         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 144
 145 2020-01-30  Alan Modra  <amodra@gmail.com>
 146
 147         * m32c-ibld.c: Regenerate.
 148
 149 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 150
 151         * bpf-opc.c: Regenerate.
 152
 153 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 154
 155         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 156         (dis386): Use them to replace C2/C3 table entries.
 157         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 158         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 159         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 160         * i386-tbl.h: Re-generate.
 161
 162 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 163
 164         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 165         forms.
 166         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 167         DefaultSize.
 168         * i386-tbl.h: Re-generate.
 169
 170 2020-01-30  Alan Modra  <amodra@gmail.com>
 171
 172         * tic4x-dis.c (tic4x_dp): Make unsigned.
 173
 174 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 175             Jan Beulich  <jbeulich@suse.com>
 176
 177         PR binutils/25445
 178         * i386-dis.c (MOVSXD_Fixup): New function.
 179         (movsxd_mode): New enum.
 180         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 181         (intel_operand_size): Handle movsxd_mode.
 182         (OP_E_register): Likewise.
 183         (OP_G): Likewise.
 184         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 185         register on movsxd.  Add movsxd with 16-bit destination register
 186         for AMD64 and Intel64 ISAs.
 187         * i386-tbl.h: Regenerated.
 188
 189 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 190
 191         PR 25403
 192         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 193         * aarch64-asm-2.c: Regenerate
 194         * aarch64-dis-2.c: Likewise.
 195         * aarch64-opc-2.c: Likewise.
 196
 197 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 198
 199         * i386-opc.tbl (sysret): Drop DefaultSize.
 200         * i386-tbl.h: Re-generate.
 201
 202 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 203
 204         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 205         Dword.
 206         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 207         * i386-tbl.h: Re-generate.
 208
 209 2020-01-20  Nick Clifton  <nickc@redhat.com>
 210
 211         * po/de.po: Updated German translation.
 212         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 213         * po/uk.po: Updated Ukranian translation.
 214
 215 2020-01-20  Alan Modra  <amodra@gmail.com>
 216
 217         * hppa-dis.c (fput_const): Remove useless cast.
 218
 219 2020-01-20  Alan Modra  <amodra@gmail.com>
 220
 221         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 222
 223 2020-01-18  Nick Clifton  <nickc@redhat.com>
 224
 225         * configure: Regenerate.
 226         * po/opcodes.pot: Regenerate.
 227
 228 2020-01-18  Nick Clifton  <nickc@redhat.com>
 229
 230         Binutils 2.34 branch created.
 231
 232 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 233
 234         * opintl.h: Fix spelling error (seperate).
 235
 236 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 237
 238         * i386-opc.tbl: Add {vex} pseudo prefix.
 239         * i386-tbl.h: Regenerated.
 240
 241 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 242
 243         PR 25376
 244         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 245         (neon_opcodes): Likewise.
 246         (select_arm_features): Make sure we enable MVE bits when selecting
 247         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 248         any architecture.
 249
 250 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 251
 252         * i386-opc.tbl: Drop stale comment from XOP section.
 253
 254 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 255
 256         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 257         (extractps): Add VexWIG to SSE2AVX forms.
 258         * i386-tbl.h: Re-generate.
 259
 260 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 261
 262         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 263         Size64 from and use VexW1 on SSE2AVX forms.
 264         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 265         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 266         * i386-tbl.h: Re-generate.
 267
 268 2020-01-15  Alan Modra  <amodra@gmail.com>
 269
 270         * tic4x-dis.c (tic4x_version): Make unsigned long.
 271         (optab, optab_special, registernames): New file scope vars.
 272         (tic4x_print_register): Set up registernames rather than
 273         malloc'd registertable.
 274         (tic4x_disassemble): Delete optable and optable_special.  Use
 275         optab and optab_special instead.  Throw away old optab,
 276         optab_special and registernames when info->mach changes.
 277
 278 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 279
 280         PR 25377
 281         * z80-dis.c (suffix): Use .db instruction to generate double
 282         prefix.
 283
 284 2020-01-14  Alan Modra  <amodra@gmail.com>
 285
 286         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 287         values to unsigned before shifting.
 288
 289 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 290
 291         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 292         flow instructions.
 293         (print_insn_thumb16, print_insn_thumb32): Likewise.
 294         (print_insn): Initialize the insn info.
 295         * i386-dis.c (print_insn): Initialize the insn info fields, and
 296         detect jumps.
 297
 298 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 299
 300         * arc-opc.c (C_NE): Make it required.
 301
 302 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 303
 304         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 305         reserved register name.
 306
 307 2020-01-13  Alan Modra  <amodra@gmail.com>
 308
 309         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 310         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 311
 312 2020-01-13  Alan Modra  <amodra@gmail.com>
 313
 314         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 315         result of wasm_read_leb128 in a uint64_t and check that bits
 316         are not lost when copying to other locals.  Use uint32_t for
 317         most locals.  Use PRId64 when printing int64_t.
 318
 319 2020-01-13  Alan Modra  <amodra@gmail.com>
 320
 321         * score-dis.c: Formatting.
 322         * score7-dis.c: Formatting.
 323
 324 2020-01-13  Alan Modra  <amodra@gmail.com>
 325
 326         * score-dis.c (print_insn_score48): Use unsigned variables for
 327         unsigned values.  Don't left shift negative values.
 328         (print_insn_score32): Likewise.
 329         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 330
 331 2020-01-13  Alan Modra  <amodra@gmail.com>
 332
 333         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 334
 335 2020-01-13  Alan Modra  <amodra@gmail.com>
 336
 337         * fr30-ibld.c: Regenerate.
 338
 339 2020-01-13  Alan Modra  <amodra@gmail.com>
 340
 341         * xgate-dis.c (print_insn): Don't left shift signed value.
 342         (ripBits): Formatting, use 1u.
 343
 344 2020-01-10  Alan Modra  <amodra@gmail.com>
 345
 346         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 347         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 348
 349 2020-01-10  Alan Modra  <amodra@gmail.com>
 350
 351         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 352         and XRREG value earlier to avoid a shift with negative exponent.
 353         * m10200-dis.c (disassemble): Similarly.
 354
 355 2020-01-09  Nick Clifton  <nickc@redhat.com>
 356
 357         PR 25224
 358         * z80-dis.c (ld_ii_ii): Use correct cast.
 359
 360 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 361
 362         PR 25224
 363         * z80-dis.c (ld_ii_ii): Use character constant when checking
 364         opcode byte value.
 365
 366 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 367
 368         * i386-dis.c (SEP_Fixup): New.
 369         (SEP): Define.
 370         (dis386_twobyte): Use it for sysenter/sysexit.
 371         (enum x86_64_isa): Change amd64 enumerator to value 1.
 372         (OP_J): Compare isa64 against intel64 instead of amd64.
 373         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 374         forms.
 375         * i386-tbl.h: Re-generate.
 376
 377 2020-01-08  Alan Modra  <amodra@gmail.com>
 378
 379         * z8k-dis.c: Include libiberty.h
 380         (instr_data_s): Make max_fetched unsigned.
 381         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 382         Don't exceed byte_info bounds.
 383         (output_instr): Make num_bytes unsigned.
 384         (unpack_instr): Likewise for nibl_count and loop.
 385         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 386         idx unsigned.
 387         * z8k-opc.h: Regenerate.
 388
 389 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 390
 391         * arc-tbl.h (llock): Use 'LLOCK' as class.
 392         (llockd): Likewise.
 393         (scond): Use 'SCOND' as class.
 394         (scondd): Likewise.
 395         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 396         (scondd): Likewise.
 397
 398 2020-01-06  Alan Modra  <amodra@gmail.com>
 399
 400         * m32c-ibld.c: Regenerate.
 401
 402 2020-01-06  Alan Modra  <amodra@gmail.com>
 403
 404         PR 25344
 405         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 406         Peek at next byte to prevent recursion on repeated prefix bytes.
 407         Ensure uninitialised "mybuf" is not accessed.
 408         (print_insn_z80): Don't zero n_fetch and n_used here,..
 409         (print_insn_z80_buf): ..do it here instead.
 410
 411 2020-01-04  Alan Modra  <amodra@gmail.com>
 412
 413         * m32r-ibld.c: Regenerate.
 414
 415 2020-01-04  Alan Modra  <amodra@gmail.com>
 416
 417         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 418
 419 2020-01-04  Alan Modra  <amodra@gmail.com>
 420
 421         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 422
 423 2020-01-04  Alan Modra  <amodra@gmail.com>
 424
 425         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 426
 427 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 428
 429         * aarch64-tbl.h (aarch64_opcode_table): Use
 430         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 431
 432 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 433
 434         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 435         forms of SUDOT and USDOT.
 436
 437 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 438
 439         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 440         uzip{1,2}.
 441         * opcodes/aarch64-dis-2.c: Re-generate.
 442
 443 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 444
 445         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 446         FMMLA encoding.
 447         * opcodes/aarch64-dis-2.c: Re-generate.
 448
 449 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 450
 451         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 452
 453 2020-01-01  Alan Modra  <amodra@gmail.com>
 454
 455         Update year range in copyright notice of all files.
 456
 457 For older changes see ChangeLog-2019
 458 \f
 459 Copyright (C) 2020 Free Software Foundation, Inc.
 460
 461 Copying and distribution of this file, with or without modification,
 462 are permitted in any medium without royalty provided the copyright
 463 notice and this notice are preserved.
 464
 465 Local Variables:
 466 mode: change-log
 467 left-margin: 8
 468 fill-column: 74
 469 version-control: never
 470 End: