1 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
3 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
6 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
8 * i386-opc.tbl (movsx): Remove Intel syntax comments.
11 2020-02-14 Jan Beulich <jbeulich@suse.com>
14 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
15 destination for Cpu64-only variant.
16 (movzx): Fold patterns.
17 * i386-tbl.h: Re-generate.
19 2020-02-13 Jan Beulich <jbeulich@suse.com>
21 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
22 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
23 CPU_ANY_SSE4_FLAGS entry.
24 * i386-init.h: Re-generate.
26 2020-02-12 Jan Beulich <jbeulich@suse.com>
28 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
29 with Unspecified, making the present one AT&T syntax only.
30 * i386-tbl.h: Re-generate.
32 2020-02-12 Jan Beulich <jbeulich@suse.com>
34 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
35 * i386-tbl.h: Re-generate.
37 2020-02-12 Jan Beulich <jbeulich@suse.com>
40 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
41 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
42 Amd64 and Intel64 templates.
43 (call, jmp): Likewise for far indirect variants. Dro
45 * i386-tbl.h: Re-generate.
47 2020-02-11 Jan Beulich <jbeulich@suse.com>
49 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
50 * i386-opc.h (ShortForm): Delete.
51 (struct i386_opcode_modifier): Remove shortform field.
52 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
53 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
54 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
55 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
57 * i386-tbl.h: Re-generate.
59 2020-02-11 Jan Beulich <jbeulich@suse.com>
61 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
62 fucompi): Drop ShortForm from operand-less templates.
63 * i386-tbl.h: Re-generate.
65 2020-02-11 Alan Modra <amodra@gmail.com>
67 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
68 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
69 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
70 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
71 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
73 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
75 * arm-dis.c (print_insn_cde): Define 'V' parse character.
76 (cde_opcodes): Add VCX* instructions.
78 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
79 Matthew Malcomson <matthew.malcomson@arm.com>
81 * arm-dis.c (struct cdeopcode32): New.
82 (CDE_OPCODE): New macro.
83 (cde_opcodes): New disassembly table.
84 (regnames): New option to table.
85 (cde_coprocs): New global variable.
87 (print_insn_thumb32): Use print_insn_cde.
88 (parse_arm_disassembler_options): Parse coprocN args.
90 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
93 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
95 * i386-opc.h (AMD64): Removed.
99 (INTEL64ONLY): Likewise.
100 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
101 * i386-opc.tbl (Amd64): New.
103 (Intel64Only): Likewise.
104 Replace AMD64 with Amd64. Update sysenter/sysenter with
105 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
106 * i386-tbl.h: Regenerated.
108 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
111 * z80-dis.c: Add support for GBZ80 opcodes.
113 2020-02-04 Alan Modra <amodra@gmail.com>
115 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
117 2020-02-03 Alan Modra <amodra@gmail.com>
119 * m32c-ibld.c: Regenerate.
121 2020-02-01 Alan Modra <amodra@gmail.com>
123 * frv-ibld.c: Regenerate.
125 2020-01-31 Jan Beulich <jbeulich@suse.com>
127 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
128 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
129 (OP_E_memory): Replace xmm_mdq_mode case label by
130 vex_scalar_w_dq_mode one.
131 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
133 2020-01-31 Jan Beulich <jbeulich@suse.com>
135 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
136 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
137 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
138 (intel_operand_size): Drop vex_w_dq_mode case label.
140 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
142 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
143 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
145 2020-01-30 Alan Modra <amodra@gmail.com>
147 * m32c-ibld.c: Regenerate.
149 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
151 * bpf-opc.c: Regenerate.
153 2020-01-30 Jan Beulich <jbeulich@suse.com>
155 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
156 (dis386): Use them to replace C2/C3 table entries.
157 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
158 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
159 ones. Use Size64 instead of DefaultSize on Intel64 ones.
160 * i386-tbl.h: Re-generate.
162 2020-01-30 Jan Beulich <jbeulich@suse.com>
164 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
166 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
168 * i386-tbl.h: Re-generate.
170 2020-01-30 Alan Modra <amodra@gmail.com>
172 * tic4x-dis.c (tic4x_dp): Make unsigned.
174 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
175 Jan Beulich <jbeulich@suse.com>
178 * i386-dis.c (MOVSXD_Fixup): New function.
179 (movsxd_mode): New enum.
180 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
181 (intel_operand_size): Handle movsxd_mode.
182 (OP_E_register): Likewise.
184 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
185 register on movsxd. Add movsxd with 16-bit destination register
186 for AMD64 and Intel64 ISAs.
187 * i386-tbl.h: Regenerated.
189 2020-01-27 Tamar Christina <tamar.christina@arm.com>
192 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
193 * aarch64-asm-2.c: Regenerate
194 * aarch64-dis-2.c: Likewise.
195 * aarch64-opc-2.c: Likewise.
197 2020-01-21 Jan Beulich <jbeulich@suse.com>
199 * i386-opc.tbl (sysret): Drop DefaultSize.
200 * i386-tbl.h: Re-generate.
202 2020-01-21 Jan Beulich <jbeulich@suse.com>
204 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
206 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
207 * i386-tbl.h: Re-generate.
209 2020-01-20 Nick Clifton <nickc@redhat.com>
211 * po/de.po: Updated German translation.
212 * po/pt_BR.po: Updated Brazilian Portuguese translation.
213 * po/uk.po: Updated Ukranian translation.
215 2020-01-20 Alan Modra <amodra@gmail.com>
217 * hppa-dis.c (fput_const): Remove useless cast.
219 2020-01-20 Alan Modra <amodra@gmail.com>
221 * arm-dis.c (print_insn_arm): Wrap 'T' value.
223 2020-01-18 Nick Clifton <nickc@redhat.com>
225 * configure: Regenerate.
226 * po/opcodes.pot: Regenerate.
228 2020-01-18 Nick Clifton <nickc@redhat.com>
230 Binutils 2.34 branch created.
232 2020-01-17 Christian Biesinger <cbiesinger@google.com>
234 * opintl.h: Fix spelling error (seperate).
236 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
238 * i386-opc.tbl: Add {vex} pseudo prefix.
239 * i386-tbl.h: Regenerated.
241 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
244 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
245 (neon_opcodes): Likewise.
246 (select_arm_features): Make sure we enable MVE bits when selecting
247 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
250 2020-01-16 Jan Beulich <jbeulich@suse.com>
252 * i386-opc.tbl: Drop stale comment from XOP section.
254 2020-01-16 Jan Beulich <jbeulich@suse.com>
256 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
257 (extractps): Add VexWIG to SSE2AVX forms.
258 * i386-tbl.h: Re-generate.
260 2020-01-16 Jan Beulich <jbeulich@suse.com>
262 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
263 Size64 from and use VexW1 on SSE2AVX forms.
264 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
265 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
266 * i386-tbl.h: Re-generate.
268 2020-01-15 Alan Modra <amodra@gmail.com>
270 * tic4x-dis.c (tic4x_version): Make unsigned long.
271 (optab, optab_special, registernames): New file scope vars.
272 (tic4x_print_register): Set up registernames rather than
273 malloc'd registertable.
274 (tic4x_disassemble): Delete optable and optable_special. Use
275 optab and optab_special instead. Throw away old optab,
276 optab_special and registernames when info->mach changes.
278 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
281 * z80-dis.c (suffix): Use .db instruction to generate double
284 2020-01-14 Alan Modra <amodra@gmail.com>
286 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
287 values to unsigned before shifting.
289 2020-01-13 Thomas Troeger <tstroege@gmx.de>
291 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
293 (print_insn_thumb16, print_insn_thumb32): Likewise.
294 (print_insn): Initialize the insn info.
295 * i386-dis.c (print_insn): Initialize the insn info fields, and
298 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
300 * arc-opc.c (C_NE): Make it required.
302 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
304 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
305 reserved register name.
307 2020-01-13 Alan Modra <amodra@gmail.com>
309 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
310 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
312 2020-01-13 Alan Modra <amodra@gmail.com>
314 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
315 result of wasm_read_leb128 in a uint64_t and check that bits
316 are not lost when copying to other locals. Use uint32_t for
317 most locals. Use PRId64 when printing int64_t.
319 2020-01-13 Alan Modra <amodra@gmail.com>
321 * score-dis.c: Formatting.
322 * score7-dis.c: Formatting.
324 2020-01-13 Alan Modra <amodra@gmail.com>
326 * score-dis.c (print_insn_score48): Use unsigned variables for
327 unsigned values. Don't left shift negative values.
328 (print_insn_score32): Likewise.
329 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
331 2020-01-13 Alan Modra <amodra@gmail.com>
333 * tic4x-dis.c (tic4x_print_register): Remove dead code.
335 2020-01-13 Alan Modra <amodra@gmail.com>
337 * fr30-ibld.c: Regenerate.
339 2020-01-13 Alan Modra <amodra@gmail.com>
341 * xgate-dis.c (print_insn): Don't left shift signed value.
342 (ripBits): Formatting, use 1u.
344 2020-01-10 Alan Modra <amodra@gmail.com>
346 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
347 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
349 2020-01-10 Alan Modra <amodra@gmail.com>
351 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
352 and XRREG value earlier to avoid a shift with negative exponent.
353 * m10200-dis.c (disassemble): Similarly.
355 2020-01-09 Nick Clifton <nickc@redhat.com>
358 * z80-dis.c (ld_ii_ii): Use correct cast.
360 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
363 * z80-dis.c (ld_ii_ii): Use character constant when checking
366 2020-01-09 Jan Beulich <jbeulich@suse.com>
368 * i386-dis.c (SEP_Fixup): New.
370 (dis386_twobyte): Use it for sysenter/sysexit.
371 (enum x86_64_isa): Change amd64 enumerator to value 1.
372 (OP_J): Compare isa64 against intel64 instead of amd64.
373 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
375 * i386-tbl.h: Re-generate.
377 2020-01-08 Alan Modra <amodra@gmail.com>
379 * z8k-dis.c: Include libiberty.h
380 (instr_data_s): Make max_fetched unsigned.
381 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
382 Don't exceed byte_info bounds.
383 (output_instr): Make num_bytes unsigned.
384 (unpack_instr): Likewise for nibl_count and loop.
385 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
387 * z8k-opc.h: Regenerate.
389 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
391 * arc-tbl.h (llock): Use 'LLOCK' as class.
393 (scond): Use 'SCOND' as class.
395 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
398 2020-01-06 Alan Modra <amodra@gmail.com>
400 * m32c-ibld.c: Regenerate.
402 2020-01-06 Alan Modra <amodra@gmail.com>
405 * z80-dis.c (suffix): Don't use a local struct buffer copy.
406 Peek at next byte to prevent recursion on repeated prefix bytes.
407 Ensure uninitialised "mybuf" is not accessed.
408 (print_insn_z80): Don't zero n_fetch and n_used here,..
409 (print_insn_z80_buf): ..do it here instead.
411 2020-01-04 Alan Modra <amodra@gmail.com>
413 * m32r-ibld.c: Regenerate.
415 2020-01-04 Alan Modra <amodra@gmail.com>
417 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
419 2020-01-04 Alan Modra <amodra@gmail.com>
421 * crx-dis.c (match_opcode): Avoid shift left of signed value.
423 2020-01-04 Alan Modra <amodra@gmail.com>
425 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
427 2020-01-03 Jan Beulich <jbeulich@suse.com>
429 * aarch64-tbl.h (aarch64_opcode_table): Use
430 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
432 2020-01-03 Jan Beulich <jbeulich@suse.com>
434 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
435 forms of SUDOT and USDOT.
437 2020-01-03 Jan Beulich <jbeulich@suse.com>
439 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
441 * opcodes/aarch64-dis-2.c: Re-generate.
443 2020-01-03 Jan Beulich <jbeulich@suse.com>
445 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
447 * opcodes/aarch64-dis-2.c: Re-generate.
449 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
451 * z80-dis.c: Add support for eZ80 and Z80 instructions.
453 2020-01-01 Alan Modra <amodra@gmail.com>
455 Update year range in copyright notice of all files.
457 For older changes see ChangeLog-2019
459 Copyright (C) 2020 Free Software Foundation, Inc.
461 Copying and distribution of this file, with or without modification,
462 are permitted in any medium without royalty provided the copyright
463 notice and this notice are preserved.
469 version-control: never