1 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
3 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
5 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
7 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
8 loongson3a as an alias of gs464 for compatibility.
9 * mips-opc.c (mips_opcodes): Change Comments.
11 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
13 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
15 (print_mips_disassembler_options): Document -M loongson-ext.
16 * mips-opc.c (LEXT2): New macro.
17 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
19 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
21 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
23 (parse_mips_ase_option): Handle -M loongson-ext option.
24 (print_mips_disassembler_options): Document -M loongson-ext.
25 * mips-opc.c (IL3A): Delete.
26 * mips-opc.c (LEXT): New macro.
27 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
30 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
32 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
34 (parse_mips_ase_option): Handle -M loongson-cam option.
35 (print_mips_disassembler_options): Document -M loongson-cam.
36 * mips-opc.c (LCAM): New macro.
37 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
40 2018-08-21 Alan Modra <amodra@gmail.com>
42 * ppc-dis.c (operand_value_powerpc): Init "invalid".
43 (skip_optional_operands): Count optional operands, and update
44 ppc_optional_operand_value call.
45 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
46 (extract_vlensi): Likewise.
47 (extract_fxm): Return default value for missing optional operand.
48 (extract_ls, extract_raq, extract_tbr): Likewise.
49 (insert_sxl, extract_sxl): New functions.
50 (insert_esync, extract_esync): Remove Power9 handling and simplify.
51 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
53 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
56 2018-08-20 Alan Modra <amodra@gmail.com>
58 * sh-opc.h (MASK): Simplify.
60 2018-08-18 John Darrington <john@darrington.wattle.id.au>
62 * s12z-dis.c (bm_decode): Deal with cases where the mode is
63 BM_RESERVED0 or BM_RESERVED1
64 (bm_rel_decode, bm_n_bytes): Ditto.
66 2018-08-18 John Darrington <john@darrington.wattle.id.au>
70 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
72 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
73 address with the addr32 prefix and without base nor index
76 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
78 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
79 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
80 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
81 (cpu_flags): Add CpuCMOV and CpuFXSR.
82 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
83 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
84 * i386-init.h: Regenerated.
85 * i386-tbl.h: Likewise.
87 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
89 * arc-regs.h: Update auxiliary registers.
91 2018-08-06 Jan Beulich <jbeulich@suse.com>
93 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
94 (RegIP, RegIZ): Define.
95 * i386-reg.tbl: Adjust comments.
96 (rip): Use Qword instead of BaseIndex. Use RegIP.
97 (eip): Use Dword instead of BaseIndex. Use RegIP.
98 (riz): Add Qword. Use RegIZ.
99 (eiz): Add Dword. Use RegIZ.
100 * i386-tbl.h: Re-generate.
102 2018-08-03 Jan Beulich <jbeulich@suse.com>
104 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
105 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
106 vpmovzxdq, vpmovzxwd): Remove NoRex64.
107 * i386-tbl.h: Re-generate.
109 2018-08-03 Jan Beulich <jbeulich@suse.com>
111 * i386-gen.c (operand_types): Remove Mem field.
112 * i386-opc.h (union i386_operand_type): Remove mem field.
113 * i386-init.h, i386-tbl.h: Re-generate.
115 2018-08-01 Alan Modra <amodra@gmail.com>
117 * po/POTFILES.in: Regenerate.
119 2018-07-31 Nick Clifton <nickc@redhat.com>
121 * po/sv.po: Updated Swedish translation.
123 2018-07-31 Jan Beulich <jbeulich@suse.com>
125 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
126 * i386-init.h, i386-tbl.h: Re-generate.
128 2018-07-31 Jan Beulich <jbeulich@suse.com>
130 * i386-opc.h (ZEROING_MASKING) Rename to ...
131 (DYNAMIC_MASKING): ... this. Adjust comment.
132 * i386-opc.tbl (MaskingMorZ): Define.
133 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
134 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
135 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
136 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
137 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
138 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
139 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
140 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
141 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
143 2018-07-31 Jan Beulich <jbeulich@suse.com>
145 * i386-opc.tbl: Use element rather than vector size for AVX512*
146 scatter/gather insns.
147 * i386-tbl.h: Re-generate.
149 2018-07-31 Jan Beulich <jbeulich@suse.com>
151 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
152 (cpu_flags): Drop CpuVREX.
153 * i386-opc.h (CpuVREX): Delete.
154 (union i386_cpu_flags): Remove cpuvrex.
155 * i386-init.h, i386-tbl.h: Re-generate.
157 2018-07-30 Jim Wilson <jimw@sifive.com>
159 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
161 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
163 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
165 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
166 * Makefile.in: Regenerated.
167 * configure.ac: Add C-SKY.
168 * configure: Regenerated.
169 * csky-dis.c: New file.
170 * csky-opc.h: New file.
171 * disassemble.c (ARCH_csky): Define.
172 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
173 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
175 2018-07-27 Alan Modra <amodra@gmail.com>
177 * ppc-opc.c (insert_sprbat): Correct function parameter and
179 (extract_sprbat): Likewise, variable too.
181 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
182 Alan Modra <amodra@gmail.com>
184 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
185 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
186 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
187 support disjointed BAT.
188 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
189 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
190 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
192 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
193 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
195 * i386-gen.c (adjust_broadcast_modifier): New function.
196 (process_i386_opcode_modifier): Add an argument for operands.
197 Adjust the Broadcast value based on operands.
198 (output_i386_opcode): Pass operand_types to
199 process_i386_opcode_modifier.
200 (process_i386_opcodes): Pass NULL as operands to
201 process_i386_opcode_modifier.
202 * i386-opc.h (BYTE_BROADCAST): New.
203 (WORD_BROADCAST): Likewise.
204 (DWORD_BROADCAST): Likewise.
205 (QWORD_BROADCAST): Likewise.
206 (i386_opcode_modifier): Expand broadcast to 3 bits.
207 * i386-tbl.h: Regenerated.
209 2018-07-24 Alan Modra <amodra@gmail.com>
212 * or1k-desc.h: Regenerate.
214 2018-07-24 Jan Beulich <jbeulich@suse.com>
216 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
217 vcvtusi2ss, and vcvtusi2sd.
218 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
219 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
220 * i386-tbl.h: Re-generate.
222 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
224 * arc-opc.c (extract_w6): Fix extending the sign.
226 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
228 * arc-tbl.h (vewt): Allow it for ARC EM family.
230 2018-07-23 Alan Modra <amodra@gmail.com>
233 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
234 opcode variants for mtspr/mfspr encodings.
236 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
237 Maciej W. Rozycki <macro@mips.com>
239 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
240 loongson3a descriptors.
241 (parse_mips_ase_option): Handle -M loongson-mmi option.
242 (print_mips_disassembler_options): Document -M loongson-mmi.
243 * mips-opc.c (LMMI): New macro.
244 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
247 2018-07-19 Jan Beulich <jbeulich@suse.com>
249 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
250 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
251 IgnoreSize and [XYZ]MMword where applicable.
252 * i386-tbl.h: Re-generate.
254 2018-07-19 Jan Beulich <jbeulich@suse.com>
256 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
257 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
258 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
259 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
260 * i386-tbl.h: Re-generate.
262 2018-07-19 Jan Beulich <jbeulich@suse.com>
264 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
265 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
266 VPCLMULQDQ templates into their respective AVX512VL counterparts
267 where possible, using Disp8ShiftVL and CheckRegSize instead of
268 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
269 * i386-tbl.h: Re-generate.
271 2018-07-19 Jan Beulich <jbeulich@suse.com>
273 * i386-opc.tbl: Fold AVX512DQ templates into their respective
274 AVX512VL counterparts where possible, using Disp8ShiftVL and
275 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
276 IgnoreSize) as appropriate.
277 * i386-tbl.h: Re-generate.
279 2018-07-19 Jan Beulich <jbeulich@suse.com>
281 * i386-opc.tbl: Fold AVX512BW templates into their respective
282 AVX512VL counterparts where possible, using Disp8ShiftVL and
283 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
284 IgnoreSize) as appropriate.
285 * i386-tbl.h: Re-generate.
287 2018-07-19 Jan Beulich <jbeulich@suse.com>
289 * i386-opc.tbl: Fold AVX512CD templates into their respective
290 AVX512VL counterparts where possible, using Disp8ShiftVL and
291 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
292 IgnoreSize) as appropriate.
293 * i386-tbl.h: Re-generate.
295 2018-07-19 Jan Beulich <jbeulich@suse.com>
297 * i386-opc.h (DISP8_SHIFT_VL): New.
298 * i386-opc.tbl (Disp8ShiftVL): Define.
299 (various): Fold AVX512VL templates into their respective
300 AVX512F counterparts where possible, using Disp8ShiftVL and
301 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
302 IgnoreSize) as appropriate.
303 * i386-tbl.h: Re-generate.
305 2018-07-19 Jan Beulich <jbeulich@suse.com>
307 * Makefile.am: Change dependencies and rule for
308 $(srcdir)/i386-init.h.
309 * Makefile.in: Re-generate.
310 * i386-gen.c (process_i386_opcodes): New local variable
311 "marker". Drop opening of input file. Recognize marker and line
313 * i386-opc.tbl (OPCODE_I386_H): Define.
314 (i386-opc.h): Include it.
317 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
320 * i386-opc.h (Byte): Update comments.
329 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
331 * i386-tbl.h: Regenerated.
333 2018-07-12 Sudakshina Das <sudi.das@arm.com>
335 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
336 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
337 * aarch64-asm-2.c: Regenerate.
338 * aarch64-dis-2.c: Regenerate.
339 * aarch64-opc-2.c: Regenerate.
341 2018-07-12 Tamar Christina <tamar.christina@arm.com>
344 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
345 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
346 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
347 sqdmulh, sqrdmulh): Use Em16.
349 2018-07-11 Sudakshina Das <sudi.das@arm.com>
351 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
352 csdb together with them.
353 (thumb32_opcodes): Likewise.
355 2018-07-11 Jan Beulich <jbeulich@suse.com>
357 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
358 requiring 32-bit registers as operands 2 and 3. Improve
360 (mwait, mwaitx): Fold templates. Improve comments.
361 OPERAND_TYPE_INOUTPORTREG.
362 * i386-tbl.h: Re-generate.
364 2018-07-11 Jan Beulich <jbeulich@suse.com>
366 * i386-gen.c (operand_type_init): Remove
367 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
368 OPERAND_TYPE_INOUTPORTREG.
369 * i386-init.h: Re-generate.
371 2018-07-11 Jan Beulich <jbeulich@suse.com>
373 * i386-opc.tbl (wrssd, wrussd): Add Dword.
374 (wrssq, wrussq): Add Qword.
375 * i386-tbl.h: Re-generate.
377 2018-07-11 Jan Beulich <jbeulich@suse.com>
379 * i386-opc.h: Rename OTMax to OTNum.
380 (OTNumOfUints): Adjust calculation.
381 (OTUnused): Directly alias to OTNum.
383 2018-07-09 Maciej W. Rozycki <macro@mips.com>
385 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
387 (lea_reg_xys): Likewise.
388 (print_insn_loop_primitive): Rename `reg' local variable to
391 2018-07-06 Tamar Christina <tamar.christina@arm.com>
394 * aarch64-tbl.h (ldarh): Fix disassembly mask.
396 2018-07-06 Tamar Christina <tamar.christina@arm.com>
399 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
400 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
402 2018-07-02 Maciej W. Rozycki <macro@mips.com>
405 * mips-dis.c (mips_option_arg_t): New enumeration.
406 (mips_options): New variable.
407 (disassembler_options_mips): New function.
408 (print_mips_disassembler_options): Reimplement in terms of
409 `disassembler_options_mips'.
410 * arm-dis.c (disassembler_options_arm): Adapt to using the
411 `disasm_options_and_args_t' structure.
412 * ppc-dis.c (disassembler_options_powerpc): Likewise.
413 * s390-dis.c (disassembler_options_s390): Likewise.
415 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
417 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
419 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
420 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
421 * testsuite/ld-arm/tls-longplt.d: Likewise.
423 2018-06-29 Tamar Christina <tamar.christina@arm.com>
426 * aarch64-asm-2.c: Regenerate.
427 * aarch64-dis-2.c: Likewise.
428 * aarch64-opc-2.c: Likewise.
429 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
430 * aarch64-opc.c (operand_general_constraint_met_p,
431 aarch64_print_operand): Likewise.
432 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
433 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
435 (AARCH64_OPERANDS): Add Em2.
437 2018-06-26 Nick Clifton <nickc@redhat.com>
439 * po/uk.po: Updated Ukranian translation.
440 * po/de.po: Updated German translation.
441 * po/pt_BR.po: Updated Brazilian Portuguese translation.
443 2018-06-26 Nick Clifton <nickc@redhat.com>
445 * nfp-dis.c: Fix spelling mistake.
447 2018-06-24 Nick Clifton <nickc@redhat.com>
449 * configure: Regenerate.
450 * po/opcodes.pot: Regenerate.
452 2018-06-24 Nick Clifton <nickc@redhat.com>
456 2018-06-19 Tamar Christina <tamar.christina@arm.com>
458 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
459 * aarch64-asm-2.c: Regenerate.
460 * aarch64-dis-2.c: Likewise.
462 2018-06-21 Maciej W. Rozycki <macro@mips.com>
464 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
465 `-M ginv' option description.
467 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
470 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
473 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
475 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
476 * configure.ac: Remove AC_PREREQ.
477 * Makefile.in: Re-generate.
478 * aclocal.m4: Re-generate.
479 * configure: Re-generate.
481 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
483 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
484 mips64r6 descriptors.
485 (parse_mips_ase_option): Handle -Mginv option.
486 (print_mips_disassembler_options): Document -Mginv.
487 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
489 (mips_opcodes): Define ginvi and ginvt.
491 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
492 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
494 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
495 * mips-opc.c (CRC, CRC64): New macros.
496 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
497 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
500 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
503 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
504 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
506 2018-06-06 Alan Modra <amodra@gmail.com>
508 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
509 setjmp. Move init for some other vars later too.
511 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
513 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
514 (dis_private): Add new fields for property section tracking.
515 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
516 (xtensa_instruction_fits): New functions.
517 (fetch_data): Bump minimal fetch size to 4.
518 (print_insn_xtensa): Make struct dis_private static.
519 Load and prepare property table on section change.
520 Don't disassemble literals. Don't disassemble instructions that
521 cross property table boundaries.
523 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
525 * configure: Regenerated.
527 2018-06-01 Jan Beulich <jbeulich@suse.com>
529 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
530 * i386-tbl.h: Re-generate.
532 2018-06-01 Jan Beulich <jbeulich@suse.com>
534 * i386-opc.tbl (sldt, str): Add NoRex64.
535 * i386-tbl.h: Re-generate.
537 2018-06-01 Jan Beulich <jbeulich@suse.com>
539 * i386-opc.tbl (invpcid): Add Oword.
540 * i386-tbl.h: Re-generate.
542 2018-06-01 Alan Modra <amodra@gmail.com>
544 * sysdep.h (_bfd_error_handler): Don't declare.
545 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
546 * rl78-decode.opc: Likewise.
547 * msp430-decode.c: Regenerate.
548 * rl78-decode.c: Regenerate.
550 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
552 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
553 * i386-init.h : Regenerated.
555 2018-05-25 Alan Modra <amodra@gmail.com>
557 * Makefile.in: Regenerate.
558 * po/POTFILES.in: Regenerate.
560 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
562 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
563 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
564 (insert_bab, extract_bab, insert_btab, extract_btab,
565 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
566 (BAT, BBA VBA RBS XB6S): Delete macros.
567 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
568 (BB, BD, RBX, XC6): Update for new macros.
569 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
570 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
571 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
572 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
574 2018-05-18 John Darrington <john@darrington.wattle.id.au>
576 * Makefile.am: Add support for s12z architecture.
577 * configure.ac: Likewise.
578 * disassemble.c: Likewise.
579 * disassemble.h: Likewise.
580 * Makefile.in: Regenerate.
581 * configure: Regenerate.
582 * s12z-dis.c: New file.
585 2018-05-18 Alan Modra <amodra@gmail.com>
587 * nfp-dis.c: Don't #include libbfd.h.
588 (init_nfp3200_priv): Use bfd_get_section_contents.
589 (nit_nfp6000_mecsr_sec): Likewise.
591 2018-05-17 Nick Clifton <nickc@redhat.com>
593 * po/zh_CN.po: Updated simplified Chinese translation.
595 2018-05-16 Tamar Christina <tamar.christina@arm.com>
598 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
599 * aarch64-dis-2.c: Regenerate.
601 2018-05-15 Tamar Christina <tamar.christina@arm.com>
604 * aarch64-asm.c (opintl.h): Include.
605 (aarch64_ins_sysreg): Enforce read/write constraints.
606 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
607 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
608 (F_REG_READ, F_REG_WRITE): New.
609 * aarch64-opc.c (aarch64_print_operand): Generate notes for
611 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
612 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
613 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
614 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
615 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
616 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
617 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
618 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
619 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
620 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
621 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
622 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
623 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
624 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
625 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
626 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
627 msr (F_SYS_WRITE), mrs (F_SYS_READ).
629 2018-05-15 Tamar Christina <tamar.christina@arm.com>
632 * aarch64-dis.c (no_notes: New.
633 (parse_aarch64_dis_option): Support notes.
634 (aarch64_decode_insn, print_operands): Likewise.
635 (print_aarch64_disassembler_options): Document notes.
636 * aarch64-opc.c (aarch64_print_operand): Support notes.
638 2018-05-15 Tamar Christina <tamar.christina@arm.com>
641 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
642 and take error struct.
643 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
644 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
645 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
646 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
647 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
648 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
649 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
650 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
651 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
652 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
653 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
654 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
655 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
656 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
657 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
658 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
659 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
660 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
661 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
662 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
663 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
664 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
665 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
666 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
667 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
668 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
669 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
670 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
671 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
672 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
673 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
674 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
675 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
676 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
677 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
678 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
679 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
680 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
681 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
682 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
683 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
684 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
685 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
686 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
687 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
688 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
689 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
690 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
691 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
692 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
693 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
694 (determine_disassembling_preference, aarch64_decode_insn,
695 print_insn_aarch64_word, print_insn_data): Take errors struct.
696 (print_insn_aarch64): Use errors.
697 * aarch64-asm-2.c: Regenerate.
698 * aarch64-dis-2.c: Regenerate.
699 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
700 boolean in aarch64_insert_operan.
701 (print_operand_extractor): Likewise.
702 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
704 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
706 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
708 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
710 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
712 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
714 * cr16-opc.c (cr16_instruction): Comment typo fix.
715 * hppa-dis.c (print_insn_hppa): Likewise.
717 2018-05-08 Jim Wilson <jimw@sifive.com>
719 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
720 (match_c_slli64, match_srxi_as_c_srxi): New.
721 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
722 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
723 <c.slli, c.srli, c.srai>: Use match_s_slli.
724 <c.slli64, c.srli64, c.srai64>: New.
726 2018-05-08 Alan Modra <amodra@gmail.com>
728 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
729 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
730 partition opcode space for index lookup.
732 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
734 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
735 <insn_length>: ...with this. Update usage.
736 Remove duplicate call to *info->memory_error_func.
738 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
739 H.J. Lu <hongjiu.lu@intel.com>
741 * i386-dis.c (Gva): New.
742 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
743 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
744 (prefix_table): New instructions (see prefix above).
745 (mod_table): New instructions (see prefix above).
746 (OP_G): Handle va_mode.
747 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
749 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
750 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
751 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
752 * i386-opc.tbl: Add movidir{i,64b}.
753 * i386-init.h: Regenerated.
754 * i386-tbl.h: Likewise.
756 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
758 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
760 * i386-opc.h (AddrPrefixOp0): Renamed to ...
761 (AddrPrefixOpReg): This.
762 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
763 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
765 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
767 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
768 (vle_num_opcodes): Likewise.
769 (spe2_num_opcodes): Likewise.
770 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
772 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
773 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
776 2018-05-01 Tamar Christina <tamar.christina@arm.com>
778 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
780 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
782 Makefile.am: Added nfp-dis.c.
783 configure.ac: Added bfd_nfp_arch.
784 disassemble.h: Added print_insn_nfp prototype.
785 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
786 nfp-dis.c: New, for NFP support.
787 po/POTFILES.in: Added nfp-dis.c to the list.
788 Makefile.in: Regenerate.
789 configure: Regenerate.
791 2018-04-26 Jan Beulich <jbeulich@suse.com>
793 * i386-opc.tbl: Fold various non-memory operand AVX512VL
794 templates into their base ones.
795 * i386-tlb.h: Re-generate.
797 2018-04-26 Jan Beulich <jbeulich@suse.com>
799 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
800 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
801 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
802 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
803 * i386-init.h: Re-generate.
805 2018-04-26 Jan Beulich <jbeulich@suse.com>
807 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
808 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
809 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
810 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
812 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
814 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
816 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
817 cpuregzmm, and cpuregmask.
818 * i386-init.h: Re-generate.
819 * i386-tbl.h: Re-generate.
821 2018-04-26 Jan Beulich <jbeulich@suse.com>
823 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
824 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
825 * i386-init.h: Re-generate.
827 2018-04-26 Jan Beulich <jbeulich@suse.com>
829 * i386-gen.c (VexImmExt): Delete.
830 * i386-opc.h (VexImmExt, veximmext): Delete.
831 * i386-opc.tbl: Drop all VexImmExt uses.
832 * i386-tlb.h: Re-generate.
834 2018-04-25 Jan Beulich <jbeulich@suse.com>
836 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
838 * i386-tlb.h: Re-generate.
840 2018-04-25 Tamar Christina <tamar.christina@arm.com>
842 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
844 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
846 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
848 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
849 (cpu_flags): Add CpuCLDEMOTE.
850 * i386-init.h: Regenerate.
851 * i386-opc.h (enum): Add CpuCLDEMOTE,
852 (i386_cpu_flags): Add cpucldemote.
853 * i386-opc.tbl: Add cldemote.
854 * i386-tbl.h: Regenerate.
856 2018-04-16 Alan Modra <amodra@gmail.com>
858 * Makefile.am: Remove sh5 and sh64 support.
859 * configure.ac: Likewise.
860 * disassemble.c: Likewise.
861 * disassemble.h: Likewise.
862 * sh-dis.c: Likewise.
863 * sh64-dis.c: Delete.
864 * sh64-opc.c: Delete.
865 * sh64-opc.h: Delete.
866 * Makefile.in: Regenerate.
867 * configure: Regenerate.
868 * po/POTFILES.in: Regenerate.
870 2018-04-16 Alan Modra <amodra@gmail.com>
872 * Makefile.am: Remove w65 support.
873 * configure.ac: Likewise.
874 * disassemble.c: Likewise.
875 * disassemble.h: Likewise.
878 * Makefile.in: Regenerate.
879 * configure: Regenerate.
880 * po/POTFILES.in: Regenerate.
882 2018-04-16 Alan Modra <amodra@gmail.com>
884 * configure.ac: Remove we32k support.
885 * configure: Regenerate.
887 2018-04-16 Alan Modra <amodra@gmail.com>
889 * Makefile.am: Remove m88k support.
890 * configure.ac: Likewise.
891 * disassemble.c: Likewise.
892 * disassemble.h: Likewise.
893 * m88k-dis.c: Delete.
894 * Makefile.in: Regenerate.
895 * configure: Regenerate.
896 * po/POTFILES.in: Regenerate.
898 2018-04-16 Alan Modra <amodra@gmail.com>
900 * Makefile.am: Remove i370 support.
901 * configure.ac: Likewise.
902 * disassemble.c: Likewise.
903 * disassemble.h: Likewise.
904 * i370-dis.c: Delete.
905 * i370-opc.c: Delete.
906 * Makefile.in: Regenerate.
907 * configure: Regenerate.
908 * po/POTFILES.in: Regenerate.
910 2018-04-16 Alan Modra <amodra@gmail.com>
912 * Makefile.am: Remove h8500 support.
913 * configure.ac: Likewise.
914 * disassemble.c: Likewise.
915 * disassemble.h: Likewise.
916 * h8500-dis.c: Delete.
917 * h8500-opc.h: Delete.
918 * Makefile.in: Regenerate.
919 * configure: Regenerate.
920 * po/POTFILES.in: Regenerate.
922 2018-04-16 Alan Modra <amodra@gmail.com>
924 * configure.ac: Remove tahoe support.
925 * configure: Regenerate.
927 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
929 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
931 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
933 * i386-tbl.h: Regenerated.
935 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
937 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
938 PREFIX_MOD_1_0FAE_REG_6.
940 (OP_E_register): Use va_mode.
941 * i386-dis-evex.h (prefix_table):
942 New instructions (see prefixes above).
943 * i386-gen.c (cpu_flag_init): Add WAITPKG.
944 (cpu_flags): Likewise.
945 * i386-opc.h (enum): Likewise.
946 (i386_cpu_flags): Likewise.
947 * i386-opc.tbl: Add umonitor, umwait, tpause.
948 * i386-init.h: Regenerate.
949 * i386-tbl.h: Likewise.
951 2018-04-11 Alan Modra <amodra@gmail.com>
953 * opcodes/i860-dis.c: Delete.
954 * opcodes/i960-dis.c: Delete.
955 * Makefile.am: Remove i860 and i960 support.
956 * configure.ac: Likewise.
957 * disassemble.c: Likewise.
958 * disassemble.h: Likewise.
959 * Makefile.in: Regenerate.
960 * configure: Regenerate.
961 * po/POTFILES.in: Regenerate.
963 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
966 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
968 (print_insn): Clear vex instead of vex.evex.
970 2018-04-04 Nick Clifton <nickc@redhat.com>
972 * po/es.po: Updated Spanish translation.
974 2018-03-28 Jan Beulich <jbeulich@suse.com>
976 * i386-gen.c (opcode_modifiers): Delete VecESize.
977 * i386-opc.h (VecESize): Delete.
978 (struct i386_opcode_modifier): Delete vecesize.
979 * i386-opc.tbl: Drop VecESize.
980 * i386-tlb.h: Re-generate.
982 2018-03-28 Jan Beulich <jbeulich@suse.com>
984 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
985 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
986 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
987 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
988 * i386-tlb.h: Re-generate.
990 2018-03-28 Jan Beulich <jbeulich@suse.com>
992 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
994 * i386-tlb.h: Re-generate.
996 2018-03-28 Jan Beulich <jbeulich@suse.com>
998 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
999 (vex_len_table): Drop Y for vcvt*2si.
1000 (putop): Replace plain 'Y' handling by abort().
1002 2018-03-28 Nick Clifton <nickc@redhat.com>
1005 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1006 instructions with only a base address register.
1007 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1008 handle AARHC64_OPND_SVE_ADDR_R.
1009 (aarch64_print_operand): Likewise.
1010 * aarch64-asm-2.c: Regenerate.
1011 * aarch64_dis-2.c: Regenerate.
1012 * aarch64-opc-2.c: Regenerate.
1014 2018-03-22 Jan Beulich <jbeulich@suse.com>
1016 * i386-opc.tbl: Drop VecESize from register only insn forms and
1017 memory forms not allowing broadcast.
1018 * i386-tlb.h: Re-generate.
1020 2018-03-22 Jan Beulich <jbeulich@suse.com>
1022 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1023 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1024 sha256*): Drop Disp<N>.
1026 2018-03-22 Jan Beulich <jbeulich@suse.com>
1028 * i386-dis.c (EbndS, bnd_swap_mode): New.
1029 (prefix_table): Use EbndS.
1030 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1031 * i386-opc.tbl (bndmov): Move misplaced Load.
1032 * i386-tlb.h: Re-generate.
1034 2018-03-22 Jan Beulich <jbeulich@suse.com>
1036 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1037 templates allowing memory operands and folded ones for register
1039 * i386-tlb.h: Re-generate.
1041 2018-03-22 Jan Beulich <jbeulich@suse.com>
1043 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1044 256-bit templates. Drop redundant leftover Disp<N>.
1045 * i386-tlb.h: Re-generate.
1047 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1049 * riscv-opc.c (riscv_insn_types): New.
1051 2018-03-13 Nick Clifton <nickc@redhat.com>
1053 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1055 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1057 * i386-opc.tbl: Add Optimize to clr.
1058 * i386-tbl.h: Regenerated.
1060 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1062 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1063 * i386-opc.h (OldGcc): Removed.
1064 (i386_opcode_modifier): Remove oldgcc.
1065 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1066 instructions for old (<= 2.8.1) versions of gcc.
1067 * i386-tbl.h: Regenerated.
1069 2018-03-08 Jan Beulich <jbeulich@suse.com>
1071 * i386-opc.h (EVEXDYN): New.
1072 * i386-opc.tbl: Fold various AVX512VL templates.
1073 * i386-tlb.h: Re-generate.
1075 2018-03-08 Jan Beulich <jbeulich@suse.com>
1077 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1078 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1079 vpexpandd, vpexpandq): Fold AFX512VF templates.
1080 * i386-tlb.h: Re-generate.
1082 2018-03-08 Jan Beulich <jbeulich@suse.com>
1084 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1085 Fold 128- and 256-bit VEX-encoded templates.
1086 * i386-tlb.h: Re-generate.
1088 2018-03-08 Jan Beulich <jbeulich@suse.com>
1090 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1091 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1092 vpexpandd, vpexpandq): Fold AVX512F templates.
1093 * i386-tlb.h: Re-generate.
1095 2018-03-08 Jan Beulich <jbeulich@suse.com>
1097 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1098 64-bit templates. Drop Disp<N>.
1099 * i386-tlb.h: Re-generate.
1101 2018-03-08 Jan Beulich <jbeulich@suse.com>
1103 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1104 and 256-bit templates.
1105 * i386-tlb.h: Re-generate.
1107 2018-03-08 Jan Beulich <jbeulich@suse.com>
1109 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1110 * i386-tlb.h: Re-generate.
1112 2018-03-08 Jan Beulich <jbeulich@suse.com>
1114 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1116 * i386-tlb.h: Re-generate.
1118 2018-03-08 Jan Beulich <jbeulich@suse.com>
1120 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1121 * i386-tlb.h: Re-generate.
1123 2018-03-08 Jan Beulich <jbeulich@suse.com>
1125 * i386-gen.c (opcode_modifiers): Delete FloatD.
1126 * i386-opc.h (FloatD): Delete.
1127 (struct i386_opcode_modifier): Delete floatd.
1128 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1130 * i386-tlb.h: Re-generate.
1132 2018-03-08 Jan Beulich <jbeulich@suse.com>
1134 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1136 2018-03-08 Jan Beulich <jbeulich@suse.com>
1138 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1139 * i386-tlb.h: Re-generate.
1141 2018-03-08 Jan Beulich <jbeulich@suse.com>
1143 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1145 * i386-tlb.h: Re-generate.
1147 2018-03-07 Alan Modra <amodra@gmail.com>
1149 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1151 * disassemble.h (print_insn_rs6000): Delete.
1152 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1153 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1154 (print_insn_rs6000): Delete.
1156 2018-03-03 Alan Modra <amodra@gmail.com>
1158 * sysdep.h (opcodes_error_handler): Define.
1159 (_bfd_error_handler): Declare.
1160 * Makefile.am: Remove stray #.
1161 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1163 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1164 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1165 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1166 opcodes_error_handler to print errors. Standardize error messages.
1167 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1168 and include opintl.h.
1169 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1170 * i386-gen.c: Standardize error messages.
1171 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1172 * Makefile.in: Regenerate.
1173 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1174 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1175 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1176 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1177 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1178 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1179 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1180 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1181 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1182 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1183 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1184 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1185 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1187 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1189 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1190 vpsub[bwdq] instructions.
1191 * i386-tbl.h: Regenerated.
1193 2018-03-01 Alan Modra <amodra@gmail.com>
1195 * configure.ac (ALL_LINGUAS): Sort.
1196 * configure: Regenerate.
1198 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1200 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1201 macro by assignements.
1203 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1206 * i386-gen.c (opcode_modifiers): Add Optimize.
1207 * i386-opc.h (Optimize): New enum.
1208 (i386_opcode_modifier): Add optimize.
1209 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1210 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1211 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1212 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1213 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1215 * i386-tbl.h: Regenerated.
1217 2018-02-26 Alan Modra <amodra@gmail.com>
1219 * crx-dis.c (getregliststring): Allocate a large enough buffer
1220 to silence false positive gcc8 warning.
1222 2018-02-22 Shea Levy <shea@shealevy.com>
1224 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1226 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1228 * i386-opc.tbl: Add {rex},
1229 * i386-tbl.h: Regenerated.
1231 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1233 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1234 (mips16_opcodes): Replace `M' with `m' for "restore".
1236 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1238 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1240 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1242 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1243 variable to `function_index'.
1245 2018-02-13 Nick Clifton <nickc@redhat.com>
1248 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1249 about truncation of printing.
1251 2018-02-12 Henry Wong <henry@stuffedcow.net>
1253 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1255 2018-02-05 Nick Clifton <nickc@redhat.com>
1257 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1259 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1261 * i386-dis.c (enum): Add pconfig.
1262 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1263 (cpu_flags): Add CpuPCONFIG.
1264 * i386-opc.h (enum): Add CpuPCONFIG.
1265 (i386_cpu_flags): Add cpupconfig.
1266 * i386-opc.tbl: Add PCONFIG instruction.
1267 * i386-init.h: Regenerate.
1268 * i386-tbl.h: Likewise.
1270 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1272 * i386-dis.c (enum): Add PREFIX_0F09.
1273 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1274 (cpu_flags): Add CpuWBNOINVD.
1275 * i386-opc.h (enum): Add CpuWBNOINVD.
1276 (i386_cpu_flags): Add cpuwbnoinvd.
1277 * i386-opc.tbl: Add WBNOINVD instruction.
1278 * i386-init.h: Regenerate.
1279 * i386-tbl.h: Likewise.
1281 2018-01-17 Jim Wilson <jimw@sifive.com>
1283 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1285 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1287 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1288 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1289 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1290 (cpu_flags): Add CpuIBT, CpuSHSTK.
1291 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1292 (i386_cpu_flags): Add cpuibt, cpushstk.
1293 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1294 * i386-init.h: Regenerate.
1295 * i386-tbl.h: Likewise.
1297 2018-01-16 Nick Clifton <nickc@redhat.com>
1299 * po/pt_BR.po: Updated Brazilian Portugese translation.
1300 * po/de.po: Updated German translation.
1302 2018-01-15 Jim Wilson <jimw@sifive.com>
1304 * riscv-opc.c (match_c_nop): New.
1305 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1307 2018-01-15 Nick Clifton <nickc@redhat.com>
1309 * po/uk.po: Updated Ukranian translation.
1311 2018-01-13 Nick Clifton <nickc@redhat.com>
1313 * po/opcodes.pot: Regenerated.
1315 2018-01-13 Nick Clifton <nickc@redhat.com>
1317 * configure: Regenerate.
1319 2018-01-13 Nick Clifton <nickc@redhat.com>
1321 2.30 branch created.
1323 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1325 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1326 * i386-tbl.h: Regenerate.
1328 2018-01-10 Jan Beulich <jbeulich@suse.com>
1330 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1331 * i386-tbl.h: Re-generate.
1333 2018-01-10 Jan Beulich <jbeulich@suse.com>
1335 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1336 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1337 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1338 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1339 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1340 Disp8MemShift of AVX512VL forms.
1341 * i386-tbl.h: Re-generate.
1343 2018-01-09 Jim Wilson <jimw@sifive.com>
1345 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1346 then the hi_addr value is zero.
1348 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1350 * arm-dis.c (arm_opcodes): Add csdb.
1351 (thumb32_opcodes): Add csdb.
1353 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1355 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1356 * aarch64-asm-2.c: Regenerate.
1357 * aarch64-dis-2.c: Regenerate.
1358 * aarch64-opc-2.c: Regenerate.
1360 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1363 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1364 Remove AVX512 vmovd with 64-bit operands.
1365 * i386-tbl.h: Regenerated.
1367 2018-01-05 Jim Wilson <jimw@sifive.com>
1369 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1372 2018-01-03 Alan Modra <amodra@gmail.com>
1374 Update year range in copyright notice of all files.
1376 2018-01-02 Jan Beulich <jbeulich@suse.com>
1378 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1379 and OPERAND_TYPE_REGZMM entries.
1381 For older changes see ChangeLog-2017
1383 Copyright (C) 2018 Free Software Foundation, Inc.
1385 Copying and distribution of this file, with or without modification,
1386 are permitted in any medium without royalty provided the copyright
1387 notice and this notice are preserved.
1393 version-control: never