1 2020-05-11 Alan Modra <amodra@gmail.com>
3 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
4 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
5 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
6 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
7 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
9 2020-05-11 Alan Modra <amodra@gmail.com>
11 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
12 (XTP, DQXP, DQXP_MASK): Define.
13 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
14 (prefix_opcodes): Add plxvp and pstxvp.
16 2020-05-11 Alan Modra <amodra@gmail.com>
18 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
19 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
20 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
22 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
24 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
26 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
28 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
30 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
32 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
34 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
36 2020-05-11 Alan Modra <amodra@gmail.com>
38 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
40 2020-05-11 Alan Modra <amodra@gmail.com>
42 * ppc-dis.c (ppc_opts): Add "power10" entry.
43 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
44 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
46 2020-05-11 Nick Clifton <nickc@redhat.com>
48 * po/fr.po: Updated French translation.
50 2020-04-30 Alex Coplan <alex.coplan@arm.com>
52 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
53 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
54 (operand_general_constraint_met_p): validate
55 AARCH64_OPND_UNDEFINED.
56 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
58 * aarch64-asm-2.c: Regenerated.
59 * aarch64-dis-2.c: Regenerated.
60 * aarch64-opc-2.c: Regenerated.
62 2020-04-29 Nick Clifton <nickc@redhat.com>
65 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
68 2020-04-29 Nick Clifton <nickc@redhat.com>
70 * po/sv.po: Updated Swedish translation.
72 2020-04-29 Nick Clifton <nickc@redhat.com>
75 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
76 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
77 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
80 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
83 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
84 cmpi only on m68020up and cpu32.
86 2020-04-20 Sudakshina Das <sudi.das@arm.com>
88 * aarch64-asm.c (aarch64_ins_none): New.
89 * aarch64-asm.h (ins_none): New declaration.
90 * aarch64-dis.c (aarch64_ext_none): New.
91 * aarch64-dis.h (ext_none): New declaration.
92 * aarch64-opc.c (aarch64_print_operand): Update case for
93 AARCH64_OPND_BARRIER_PSB.
94 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
95 (AARCH64_OPERANDS): Update inserter/extracter for
96 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
97 * aarch64-asm-2.c: Regenerated.
98 * aarch64-dis-2.c: Regenerated.
99 * aarch64-opc-2.c: Regenerated.
101 2020-04-20 Sudakshina Das <sudi.das@arm.com>
103 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
104 (aarch64_feature_ras, RAS): Likewise.
105 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
106 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
107 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
108 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
109 * aarch64-asm-2.c: Regenerated.
110 * aarch64-dis-2.c: Regenerated.
111 * aarch64-opc-2.c: Regenerated.
113 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
115 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
116 (print_insn_neon): Support disassembly of conditional
119 2020-02-16 David Faust <david.faust@oracle.com>
121 * bpf-desc.c: Regenerate.
122 * bpf-desc.h: Likewise.
123 * bpf-opc.c: Regenerate.
124 * bpf-opc.h: Likewise.
126 2020-04-07 Lili Cui <lili.cui@intel.com>
128 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
129 (prefix_table): New instructions (see prefixes above).
131 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
132 CPU_ANY_TSXLDTRK_FLAGS.
133 (cpu_flags): Add CpuTSXLDTRK.
134 * i386-opc.h (enum): Add CpuTSXLDTRK.
135 (i386_cpu_flags): Add cputsxldtrk.
136 * i386-opc.tbl: Add XSUSPLDTRK insns.
137 * i386-init.h: Regenerate.
138 * i386-tbl.h: Likewise.
140 2020-04-02 Lili Cui <lili.cui@intel.com>
142 * i386-dis.c (prefix_table): New instructions serialize.
143 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
144 CPU_ANY_SERIALIZE_FLAGS.
145 (cpu_flags): Add CpuSERIALIZE.
146 * i386-opc.h (enum): Add CpuSERIALIZE.
147 (i386_cpu_flags): Add cpuserialize.
148 * i386-opc.tbl: Add SERIALIZE insns.
149 * i386-init.h: Regenerate.
150 * i386-tbl.h: Likewise.
152 2020-03-26 Alan Modra <amodra@gmail.com>
154 * disassemble.h (opcodes_assert): Declare.
155 (OPCODES_ASSERT): Define.
156 * disassemble.c: Don't include assert.h. Include opintl.h.
157 (opcodes_assert): New function.
158 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
159 (bfd_h8_disassemble): Reduce size of data array. Correctly
160 calculate maxlen. Omit insn decoding when insn length exceeds
161 maxlen. Exit from nibble loop when looking for E, before
162 accessing next data byte. Move processing of E outside loop.
163 Replace tests of maxlen in loop with assertions.
165 2020-03-26 Alan Modra <amodra@gmail.com>
167 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
169 2020-03-25 Alan Modra <amodra@gmail.com>
171 * z80-dis.c (suffix): Init mybuf.
173 2020-03-22 Alan Modra <amodra@gmail.com>
175 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
176 successflly read from section.
178 2020-03-22 Alan Modra <amodra@gmail.com>
180 * arc-dis.c (find_format): Use ISO C string concatenation rather
181 than line continuation within a string. Don't access needs_limm
182 before testing opcode != NULL.
184 2020-03-22 Alan Modra <amodra@gmail.com>
186 * ns32k-dis.c (print_insn_arg): Update comment.
187 (print_insn_ns32k): Reduce size of index_offset array, and
188 initialize, passing -1 to print_insn_arg for args that are not
189 an index. Don't exit arg loop early. Abort on bad arg number.
191 2020-03-22 Alan Modra <amodra@gmail.com>
193 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
194 * s12z-opc.c: Formatting.
195 (operands_f): Return an int.
196 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
197 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
198 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
199 (exg_sex_discrim): Likewise.
200 (create_immediate_operand, create_bitfield_operand),
201 (create_register_operand_with_size, create_register_all_operand),
202 (create_register_all16_operand, create_simple_memory_operand),
203 (create_memory_operand, create_memory_auto_operand): Don't
204 segfault on malloc failure.
205 (z_ext24_decode): Return an int status, negative on fail, zero
207 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
208 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
209 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
210 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
211 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
212 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
213 (loop_primitive_decode, shift_decode, psh_pul_decode),
214 (bit_field_decode): Similarly.
215 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
216 to return value, update callers.
217 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
218 Don't segfault on NULL operand.
219 (decode_operation): Return OP_INVALID on first fail.
220 (decode_s12z): Check all reads, returning -1 on fail.
222 2020-03-20 Alan Modra <amodra@gmail.com>
224 * metag-dis.c (print_insn_metag): Don't ignore status from
227 2020-03-20 Alan Modra <amodra@gmail.com>
229 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
230 Initialize parts of buffer not written when handling a possible
231 2-byte insn at end of section. Don't attempt decoding of such
232 an insn by the 4-byte machinery.
234 2020-03-20 Alan Modra <amodra@gmail.com>
236 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
237 partially filled buffer. Prevent lookup of 4-byte insns when
238 only VLE 2-byte insns are possible due to section size. Print
239 ".word" rather than ".long" for 2-byte leftovers.
241 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
244 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
246 2020-03-13 Jan Beulich <jbeulich@suse.com>
248 * i386-dis.c (X86_64_0D): Rename to ...
249 (X86_64_0E): ... this.
251 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
253 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
254 * Makefile.in: Regenerated.
256 2020-03-09 Jan Beulich <jbeulich@suse.com>
258 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
260 * i386-tbl.h: Re-generate.
262 2020-03-09 Jan Beulich <jbeulich@suse.com>
264 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
265 vprot*, vpsha*, and vpshl*.
266 * i386-tbl.h: Re-generate.
268 2020-03-09 Jan Beulich <jbeulich@suse.com>
270 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
271 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
272 * i386-tbl.h: Re-generate.
274 2020-03-09 Jan Beulich <jbeulich@suse.com>
276 * i386-gen.c (set_bitfield): Ignore zero-length field names.
277 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
278 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
279 * i386-tbl.h: Re-generate.
281 2020-03-09 Jan Beulich <jbeulich@suse.com>
283 * i386-gen.c (struct template_arg, struct template_instance,
284 struct template_param, struct template, templates,
285 parse_template, expand_templates): New.
286 (process_i386_opcodes): Various local variables moved to
287 expand_templates. Call parse_template and expand_templates.
288 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
289 * i386-tbl.h: Re-generate.
291 2020-03-06 Jan Beulich <jbeulich@suse.com>
293 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
294 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
295 register and memory source templates. Replace VexW= by VexW*
297 * i386-tbl.h: Re-generate.
299 2020-03-06 Jan Beulich <jbeulich@suse.com>
301 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
302 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
303 * i386-tbl.h: Re-generate.
305 2020-03-06 Jan Beulich <jbeulich@suse.com>
307 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
308 * i386-tbl.h: Re-generate.
310 2020-03-06 Jan Beulich <jbeulich@suse.com>
312 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
313 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
314 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
315 VexW0 on SSE2AVX variants.
316 (vmovq): Drop NoRex64 from XMM/XMM variants.
317 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
318 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
319 applicable use VexW0.
320 * i386-tbl.h: Re-generate.
322 2020-03-06 Jan Beulich <jbeulich@suse.com>
324 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
325 * i386-opc.h (Rex64): Delete.
326 (struct i386_opcode_modifier): Remove rex64 field.
327 * i386-opc.tbl (crc32): Drop Rex64.
328 Replace Rex64 with Size64 everywhere else.
329 * i386-tbl.h: Re-generate.
331 2020-03-06 Jan Beulich <jbeulich@suse.com>
333 * i386-dis.c (OP_E_memory): Exclude recording of used address
334 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
335 addressed memory operands for MPX insns.
337 2020-03-06 Jan Beulich <jbeulich@suse.com>
339 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
340 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
341 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
342 (ptwrite): Split into non-64-bit and 64-bit forms.
343 * i386-tbl.h: Re-generate.
345 2020-03-06 Jan Beulich <jbeulich@suse.com>
347 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
349 * i386-tbl.h: Re-generate.
351 2020-03-04 Jan Beulich <jbeulich@suse.com>
353 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
354 (prefix_table): Move vmmcall here. Add vmgexit.
355 (rm_table): Replace vmmcall entry by prefix_table[] escape.
356 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
357 (cpu_flags): Add CpuSEV_ES entry.
358 * i386-opc.h (CpuSEV_ES): New.
359 (union i386_cpu_flags): Add cpusev_es field.
360 * i386-opc.tbl (vmgexit): New.
361 * i386-init.h, i386-tbl.h: Re-generate.
363 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
365 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
367 * i386-opc.h (IGNORESIZE): New.
368 (DEFAULTSIZE): Likewise.
369 (IgnoreSize): Removed.
370 (DefaultSize): Likewise.
372 (i386_opcode_modifier): Replace ignoresize/defaultsize with
374 * i386-opc.tbl (IgnoreSize): New.
375 (DefaultSize): Likewise.
376 * i386-tbl.h: Regenerated.
378 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
381 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
384 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
387 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
388 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
389 * i386-tbl.h: Regenerated.
391 2020-02-26 Alan Modra <amodra@gmail.com>
393 * aarch64-asm.c: Indent labels correctly.
394 * aarch64-dis.c: Likewise.
395 * aarch64-gen.c: Likewise.
396 * aarch64-opc.c: Likewise.
397 * alpha-dis.c: Likewise.
398 * i386-dis.c: Likewise.
399 * nds32-asm.c: Likewise.
400 * nfp-dis.c: Likewise.
401 * visium-dis.c: Likewise.
403 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
405 * arc-regs.h (int_vector_base): Make it available for all ARC
408 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
410 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
413 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
415 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
416 c.mv/c.li if rs1 is zero.
418 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
420 * i386-gen.c (cpu_flag_init): Replace CpuABM with
421 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
423 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
424 * i386-opc.h (CpuABM): Removed.
426 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
427 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
428 popcnt. Remove CpuABM from lzcnt.
429 * i386-init.h: Regenerated.
430 * i386-tbl.h: Likewise.
432 2020-02-17 Jan Beulich <jbeulich@suse.com>
434 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
435 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
436 VexW1 instead of open-coding them.
437 * i386-tbl.h: Re-generate.
439 2020-02-17 Jan Beulich <jbeulich@suse.com>
441 * i386-opc.tbl (AddrPrefixOpReg): Define.
442 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
443 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
444 templates. Drop NoRex64.
445 * i386-tbl.h: Re-generate.
447 2020-02-17 Jan Beulich <jbeulich@suse.com>
450 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
451 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
452 into Intel syntax instance (with Unpsecified) and AT&T one
454 (vcvtneps2bf16): Likewise, along with folding the two so far
456 * i386-tbl.h: Re-generate.
458 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
460 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
463 2020-02-17 Alan Modra <amodra@gmail.com>
465 * i386-gen.c (cpu_flag_init): Correct last change.
467 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
469 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
472 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
474 * i386-opc.tbl (movsx): Remove Intel syntax comments.
477 2020-02-14 Jan Beulich <jbeulich@suse.com>
480 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
481 destination for Cpu64-only variant.
482 (movzx): Fold patterns.
483 * i386-tbl.h: Re-generate.
485 2020-02-13 Jan Beulich <jbeulich@suse.com>
487 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
488 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
489 CPU_ANY_SSE4_FLAGS entry.
490 * i386-init.h: Re-generate.
492 2020-02-12 Jan Beulich <jbeulich@suse.com>
494 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
495 with Unspecified, making the present one AT&T syntax only.
496 * i386-tbl.h: Re-generate.
498 2020-02-12 Jan Beulich <jbeulich@suse.com>
500 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
501 * i386-tbl.h: Re-generate.
503 2020-02-12 Jan Beulich <jbeulich@suse.com>
506 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
507 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
508 Amd64 and Intel64 templates.
509 (call, jmp): Likewise for far indirect variants. Dro
511 * i386-tbl.h: Re-generate.
513 2020-02-11 Jan Beulich <jbeulich@suse.com>
515 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
516 * i386-opc.h (ShortForm): Delete.
517 (struct i386_opcode_modifier): Remove shortform field.
518 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
519 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
520 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
521 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
523 * i386-tbl.h: Re-generate.
525 2020-02-11 Jan Beulich <jbeulich@suse.com>
527 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
528 fucompi): Drop ShortForm from operand-less templates.
529 * i386-tbl.h: Re-generate.
531 2020-02-11 Alan Modra <amodra@gmail.com>
533 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
534 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
535 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
536 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
537 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
539 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
541 * arm-dis.c (print_insn_cde): Define 'V' parse character.
542 (cde_opcodes): Add VCX* instructions.
544 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
545 Matthew Malcomson <matthew.malcomson@arm.com>
547 * arm-dis.c (struct cdeopcode32): New.
548 (CDE_OPCODE): New macro.
549 (cde_opcodes): New disassembly table.
550 (regnames): New option to table.
551 (cde_coprocs): New global variable.
552 (print_insn_cde): New
553 (print_insn_thumb32): Use print_insn_cde.
554 (parse_arm_disassembler_options): Parse coprocN args.
556 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
559 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
561 * i386-opc.h (AMD64): Removed.
565 (INTEL64ONLY): Likewise.
566 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
567 * i386-opc.tbl (Amd64): New.
569 (Intel64Only): Likewise.
570 Replace AMD64 with Amd64. Update sysenter/sysenter with
571 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
572 * i386-tbl.h: Regenerated.
574 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
577 * z80-dis.c: Add support for GBZ80 opcodes.
579 2020-02-04 Alan Modra <amodra@gmail.com>
581 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
583 2020-02-03 Alan Modra <amodra@gmail.com>
585 * m32c-ibld.c: Regenerate.
587 2020-02-01 Alan Modra <amodra@gmail.com>
589 * frv-ibld.c: Regenerate.
591 2020-01-31 Jan Beulich <jbeulich@suse.com>
593 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
594 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
595 (OP_E_memory): Replace xmm_mdq_mode case label by
596 vex_scalar_w_dq_mode one.
597 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
599 2020-01-31 Jan Beulich <jbeulich@suse.com>
601 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
602 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
603 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
604 (intel_operand_size): Drop vex_w_dq_mode case label.
606 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
608 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
609 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
611 2020-01-30 Alan Modra <amodra@gmail.com>
613 * m32c-ibld.c: Regenerate.
615 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
617 * bpf-opc.c: Regenerate.
619 2020-01-30 Jan Beulich <jbeulich@suse.com>
621 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
622 (dis386): Use them to replace C2/C3 table entries.
623 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
624 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
625 ones. Use Size64 instead of DefaultSize on Intel64 ones.
626 * i386-tbl.h: Re-generate.
628 2020-01-30 Jan Beulich <jbeulich@suse.com>
630 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
632 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
634 * i386-tbl.h: Re-generate.
636 2020-01-30 Alan Modra <amodra@gmail.com>
638 * tic4x-dis.c (tic4x_dp): Make unsigned.
640 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
641 Jan Beulich <jbeulich@suse.com>
644 * i386-dis.c (MOVSXD_Fixup): New function.
645 (movsxd_mode): New enum.
646 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
647 (intel_operand_size): Handle movsxd_mode.
648 (OP_E_register): Likewise.
650 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
651 register on movsxd. Add movsxd with 16-bit destination register
652 for AMD64 and Intel64 ISAs.
653 * i386-tbl.h: Regenerated.
655 2020-01-27 Tamar Christina <tamar.christina@arm.com>
658 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
659 * aarch64-asm-2.c: Regenerate
660 * aarch64-dis-2.c: Likewise.
661 * aarch64-opc-2.c: Likewise.
663 2020-01-21 Jan Beulich <jbeulich@suse.com>
665 * i386-opc.tbl (sysret): Drop DefaultSize.
666 * i386-tbl.h: Re-generate.
668 2020-01-21 Jan Beulich <jbeulich@suse.com>
670 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
672 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
673 * i386-tbl.h: Re-generate.
675 2020-01-20 Nick Clifton <nickc@redhat.com>
677 * po/de.po: Updated German translation.
678 * po/pt_BR.po: Updated Brazilian Portuguese translation.
679 * po/uk.po: Updated Ukranian translation.
681 2020-01-20 Alan Modra <amodra@gmail.com>
683 * hppa-dis.c (fput_const): Remove useless cast.
685 2020-01-20 Alan Modra <amodra@gmail.com>
687 * arm-dis.c (print_insn_arm): Wrap 'T' value.
689 2020-01-18 Nick Clifton <nickc@redhat.com>
691 * configure: Regenerate.
692 * po/opcodes.pot: Regenerate.
694 2020-01-18 Nick Clifton <nickc@redhat.com>
696 Binutils 2.34 branch created.
698 2020-01-17 Christian Biesinger <cbiesinger@google.com>
700 * opintl.h: Fix spelling error (seperate).
702 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
704 * i386-opc.tbl: Add {vex} pseudo prefix.
705 * i386-tbl.h: Regenerated.
707 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
710 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
711 (neon_opcodes): Likewise.
712 (select_arm_features): Make sure we enable MVE bits when selecting
713 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
716 2020-01-16 Jan Beulich <jbeulich@suse.com>
718 * i386-opc.tbl: Drop stale comment from XOP section.
720 2020-01-16 Jan Beulich <jbeulich@suse.com>
722 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
723 (extractps): Add VexWIG to SSE2AVX forms.
724 * i386-tbl.h: Re-generate.
726 2020-01-16 Jan Beulich <jbeulich@suse.com>
728 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
729 Size64 from and use VexW1 on SSE2AVX forms.
730 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
731 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
732 * i386-tbl.h: Re-generate.
734 2020-01-15 Alan Modra <amodra@gmail.com>
736 * tic4x-dis.c (tic4x_version): Make unsigned long.
737 (optab, optab_special, registernames): New file scope vars.
738 (tic4x_print_register): Set up registernames rather than
739 malloc'd registertable.
740 (tic4x_disassemble): Delete optable and optable_special. Use
741 optab and optab_special instead. Throw away old optab,
742 optab_special and registernames when info->mach changes.
744 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
747 * z80-dis.c (suffix): Use .db instruction to generate double
750 2020-01-14 Alan Modra <amodra@gmail.com>
752 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
753 values to unsigned before shifting.
755 2020-01-13 Thomas Troeger <tstroege@gmx.de>
757 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
759 (print_insn_thumb16, print_insn_thumb32): Likewise.
760 (print_insn): Initialize the insn info.
761 * i386-dis.c (print_insn): Initialize the insn info fields, and
764 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
766 * arc-opc.c (C_NE): Make it required.
768 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
770 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
771 reserved register name.
773 2020-01-13 Alan Modra <amodra@gmail.com>
775 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
776 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
778 2020-01-13 Alan Modra <amodra@gmail.com>
780 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
781 result of wasm_read_leb128 in a uint64_t and check that bits
782 are not lost when copying to other locals. Use uint32_t for
783 most locals. Use PRId64 when printing int64_t.
785 2020-01-13 Alan Modra <amodra@gmail.com>
787 * score-dis.c: Formatting.
788 * score7-dis.c: Formatting.
790 2020-01-13 Alan Modra <amodra@gmail.com>
792 * score-dis.c (print_insn_score48): Use unsigned variables for
793 unsigned values. Don't left shift negative values.
794 (print_insn_score32): Likewise.
795 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
797 2020-01-13 Alan Modra <amodra@gmail.com>
799 * tic4x-dis.c (tic4x_print_register): Remove dead code.
801 2020-01-13 Alan Modra <amodra@gmail.com>
803 * fr30-ibld.c: Regenerate.
805 2020-01-13 Alan Modra <amodra@gmail.com>
807 * xgate-dis.c (print_insn): Don't left shift signed value.
808 (ripBits): Formatting, use 1u.
810 2020-01-10 Alan Modra <amodra@gmail.com>
812 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
813 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
815 2020-01-10 Alan Modra <amodra@gmail.com>
817 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
818 and XRREG value earlier to avoid a shift with negative exponent.
819 * m10200-dis.c (disassemble): Similarly.
821 2020-01-09 Nick Clifton <nickc@redhat.com>
824 * z80-dis.c (ld_ii_ii): Use correct cast.
826 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
829 * z80-dis.c (ld_ii_ii): Use character constant when checking
832 2020-01-09 Jan Beulich <jbeulich@suse.com>
834 * i386-dis.c (SEP_Fixup): New.
836 (dis386_twobyte): Use it for sysenter/sysexit.
837 (enum x86_64_isa): Change amd64 enumerator to value 1.
838 (OP_J): Compare isa64 against intel64 instead of amd64.
839 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
841 * i386-tbl.h: Re-generate.
843 2020-01-08 Alan Modra <amodra@gmail.com>
845 * z8k-dis.c: Include libiberty.h
846 (instr_data_s): Make max_fetched unsigned.
847 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
848 Don't exceed byte_info bounds.
849 (output_instr): Make num_bytes unsigned.
850 (unpack_instr): Likewise for nibl_count and loop.
851 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
853 * z8k-opc.h: Regenerate.
855 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
857 * arc-tbl.h (llock): Use 'LLOCK' as class.
859 (scond): Use 'SCOND' as class.
861 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
864 2020-01-06 Alan Modra <amodra@gmail.com>
866 * m32c-ibld.c: Regenerate.
868 2020-01-06 Alan Modra <amodra@gmail.com>
871 * z80-dis.c (suffix): Don't use a local struct buffer copy.
872 Peek at next byte to prevent recursion on repeated prefix bytes.
873 Ensure uninitialised "mybuf" is not accessed.
874 (print_insn_z80): Don't zero n_fetch and n_used here,..
875 (print_insn_z80_buf): ..do it here instead.
877 2020-01-04 Alan Modra <amodra@gmail.com>
879 * m32r-ibld.c: Regenerate.
881 2020-01-04 Alan Modra <amodra@gmail.com>
883 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
885 2020-01-04 Alan Modra <amodra@gmail.com>
887 * crx-dis.c (match_opcode): Avoid shift left of signed value.
889 2020-01-04 Alan Modra <amodra@gmail.com>
891 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
893 2020-01-03 Jan Beulich <jbeulich@suse.com>
895 * aarch64-tbl.h (aarch64_opcode_table): Use
896 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
898 2020-01-03 Jan Beulich <jbeulich@suse.com>
900 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
901 forms of SUDOT and USDOT.
903 2020-01-03 Jan Beulich <jbeulich@suse.com>
905 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
907 * opcodes/aarch64-dis-2.c: Re-generate.
909 2020-01-03 Jan Beulich <jbeulich@suse.com>
911 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
913 * opcodes/aarch64-dis-2.c: Re-generate.
915 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
917 * z80-dis.c: Add support for eZ80 and Z80 instructions.
919 2020-01-01 Alan Modra <amodra@gmail.com>
921 Update year range in copyright notice of all files.
923 For older changes see ChangeLog-2019
925 Copyright (C) 2020 Free Software Foundation, Inc.
927 Copying and distribution of this file, with or without modification,
928 are permitted in any medium without royalty provided the copyright
929 notice and this notice are preserved.
935 version-control: never